Sg instruction implementation method and device based on dma architecture, equipment and storage medium

Abstract

Embodiments of the present application provide a kind of based on the SG instruction implementation method, device and equipment and storage medium of DMA architecture, involve neural network technical field.The method is based on SG instruction, obtains index tensor data, and index tensor data is parsed, obtains the index data reading address of index data;Based on the data reading address of the index data, index data is read;Based on the index data, data reading address and the data write address are calculated;Based on the data reading address, target data is read from source data storage unit, and based on the data write address, the target data is written into target storage unit, to complete data migration.Through the analysis of multi-dimensional index tensor data, data reading address and data write address are calculated, so that target data is read in source data storage unit, and moves to target storage unit, avoids the analysis of complex data, improves data migration efficiency.

Description

Technical Field

[0001] This invention relates to the field of neural network technology, and in particular to a method, apparatus, device and storage medium for implementing SG instructions based on DMA architecture. Background Technology

[0002] Data migration is a technology that integrates offline and online storage. It treats high-speed, high-capacity offline storage devices as the next level after disk devices, and then automatically migrates frequently used data from the disk to secondary high-capacity storage devices such as tape libraries according to specified strategies. DMA (Direct Memory Access) primarily enables high-speed data transfer, allowing the CPU (Central Processing Unit) to perform simple, repetitive data transfer tasks. This process requires no CPU intervention.

[0003] However, when migrating data via DMA, frequent interrupts and CPU intervention are required if large amounts of data need to be received, thus reducing data migration efficiency. Therefore, solving this inefficiency is a pressing technical problem. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for implementing SG instructions based on a DMA architecture, aiming to improve data migration efficiency.

[0005] In a first aspect, embodiments of the present invention provide a method for implementing SG instructions based on a DMA architecture, comprising:

[0006] Based on the SG instruction, the index tensor data is obtained, and the index tensor data is parsed to obtain the index data read address;

[0007] Read the index data based on the data read address of the index data;

[0008] Based on the index data, calculate the data read address and the data write address;

[0009] Based on the data read address, target data is read from the source data storage unit, and based on the data write address, the target data is written into the target storage unit to complete the data migration.

[0010] Secondly, embodiments of the present invention also provide an SG instruction implementation apparatus based on a DMA architecture, the SG instruction implementation apparatus based on a DMA architecture comprising:

[0011] The index tensor data parsing module is used to obtain index tensor data based on SG instructions, parse the index tensor data, and obtain the index data read address of the index data;

[0012] The index data reading module is used to read index data based on the data reading address of the index data;

[0013] The data read / write address calculation module is used to calculate the data read address and the data write address based on the index data;

[0014] The data migration module is used to read target data from the source data storage unit based on the data read address, and write the target data into the target storage unit based on the data write address to complete the data migration.

[0015] Thirdly, embodiments of the present invention also provide a computer device, the computer device including a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for implementing connection communication between the processor and the memory, wherein when the computer program is executed by the processor, it implements any of the SG instruction implementation methods based on the DMA architecture provided in this specification.

[0016] Fourthly, embodiments of the present invention also provide a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, which can be executed by one or more processors to implement any of the SG instruction implementation methods based on the DMA architecture provided in this specification.

[0017] This invention provides a method, apparatus, device, and storage medium for implementing SG instructions based on a DMA architecture. The method, based on SG instructions, acquires index tensor data and parses the index tensor data to obtain the index data read address; reads the index data based on the read address; calculates the data read address and the data write address based on the index data; reads target data from the source data storage unit based on the read address, and writes the target data to the target storage unit based on the write address, thereby completing data migration. By parsing multidimensional index tensor data, linear index data is obtained, simplifying multidimensional data and reducing the difficulty of data indexing; by calculating the data read address and data write address based on the index data, the target data can be read by querying the data read address in the source data storage unit, and the target data is moved to the corresponding data write address in the target storage unit, avoiding the parsing of complex data and improving data migration efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the first embodiment of the SG instruction implementation method based on DMA architecture provided in this application;

[0020] Figure 2 A schematic diagram of a DMA architecture for implementing SG instructions is provided in an embodiment of this application;

[0021] Figure 3 A flowchart illustrating a second embodiment of an SG instruction implementation method based on a DMA architecture provided in this application;

[0022] Figure 4 This is a schematic block diagram of an SG instruction implementation device based on a DMA architecture provided in an embodiment of this application;

[0023] Figure 5 This is a schematic block diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0026] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] Data migration is a technology that integrates offline and online storage. It treats high-speed, high-capacity offline storage devices as the next-level devices after disk drives, and then automatically migrates frequently used data from the disks to secondary high-capacity storage devices such as tape libraries according to specified strategies. DMA (Direct Memory Access) primarily enables high-speed data transfer, allowing the CPU (Central Processing Unit) to handle simple, repetitive data transfer tasks. This process requires no CPU intervention. However, when migrating data via DMA, if a large amount of data needs to be received, frequent interrupts are triggered, and CPU participation is required, thus reducing the efficiency of data migration.

[0028] To address the aforementioned issues, this invention provides a method, apparatus, device, and storage medium for implementing SG instructions based on a DMA architecture. By parsing multidimensional index tensor data, linear index data is obtained, simplifying multidimensional data and reducing the difficulty of data indexing. Data read and write addresses are calculated based on the index data. The target data can be read by querying the data read address in the source data storage unit, and the target data is then moved to the corresponding data write address in the target storage unit. This avoids parsing complex data and improves data migration efficiency.

[0029] The computer devices in these embodiments may include servers, terminal devices, embedded devices, edge computing devices, etc. Servers may be standalone servers or cloud servers providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Terminal devices may include mobile phones, tablets, laptops, and personal computers, etc.

[0030] Please see Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the SG instruction implementation method based on DMA architecture provided in this application.

[0031] like Figure 1 As shown, the SG instruction implementation method based on the DMA architecture includes steps S101 to S103.

[0032] Step S101: Based on the SG instruction, obtain the index tensor data, parse the index tensor data, and obtain the index data read address of the index data;

[0033] In this embodiment, an SG (scatter-gather) instruction is sent to the DMA architecture. By parsing the SG instruction, a request to read the index tensor is generated, and the read address of the index data is calculated.

[0034] In one exemplary embodiment, the DMA (Direct Memory Access) provided in this application is a dedicated architecture for data transfer in neural network processors, which can support data transfer in tensor format and support a variety of complex data processing instructions.

[0035] In one exemplary implementation, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a DMA architecture for implementing SG instructions, provided in an embodiment of this application. The DMA includes two paths: cmd_path and data_path. The cmd_path contains three sets of address calculation modules, two sets of req_fifo, and one cmd_buffer; the data_path contains two sets of data_fifo and a constant generation module.

[0036] The DMA command and control module is as follows: `cmd_path` is the request path, responsible for instruction parsing, sending read / write commands, and address calculation. `data_path` is the data path, responsible for collecting valid data and index data. `interface` is the data interface, responsible for receiving requests sent by `cmd_path` and returning data to `data_path`. `cmd_buffer` is the command buffer, responsible for collecting and storing DMA instructions. `index_addr_gen` is the index address calculation module, responsible for calculating the read address of index data. `gather_addr_gen` is the module for calculating the read / write address of collected instruction data. `scatter_addr_gen` is the module for calculating the read / write address of distributed instruction data. `rreq_fifo` is the first-in-first-out queue for read requests. `wreq_fifo` is the first-in-first-out queue for write requests. `index_fifo` is the first-in-first-out queue for index data. `data_fifo` is the first-in-first-out queue for valid data. `const_gen` is the constant generation module, responsible for determining whether the output data is a constant and outputting the constant.

[0037] In one exemplary implementation, the SG instruction is sent to the command buffer cmd_buffer, and then the command buffer cmd_buffer sends the SG instruction to the index address calculation module index_addr_gen. The index address calculation module index_addr_gen parses the SG instruction and generates a request to read the index tensor, that is, calculates the read address of the index data.

[0038] Step S102: Read the index data based on the data read address of the index data;

[0039] In this embodiment, after the DMA calculates the data read address of the index data, it sends a read request to the external storage unit through the data interface. After the handshake is completed with the external storage unit, the read request can be sent to the external storage unit, and then the external storage unit returns the corresponding index data.

[0040] In one exemplary implementation, the data input from the external storage unit to the DMA can be index data or valid data that needs to be migrated. The input data can be prioritized using a data selector (mux), with index data processed first. For example... Figure 2 As shown, the external device sends valid data to data_path through the rdata interface, and then selects data through mux. If it is index data, it is sent to the index first-in-first-out queue index_fifo; if it is valid data, it is sent to the valid data first-in-first-out queue data_fifo.

[0041] In one exemplary implementation, a mux (data selector) is a device that can select one signal from multiple input signals for output. It can select a specific signal from a set of input signals and send it to the output terminal based on a given input address code. For example, when all input data in a data queue is input into the data selector, the data selector will only select the input data corresponding to the preset input address code for output, while other data cannot be output, thereby achieving the splitting of input data or mask data.

[0042] Step S103: Based on the index data, calculate the data read address and the data write address;

[0043] In this embodiment, the index data can be used as a rule for data migration. Therefore, the index data includes the data read address and the data write address. The data read address is the data storage address of the source data storage unit, and the data write address is the data storage address of the target storage unit.

[0044] In one exemplary implementation, the data read address can be calculated by the gather_addr_gen module for collecting instruction data read / write address calculations, and the data write address can be calculated by the scatter_addr_gen module for distributing instruction data read / write address calculations.

[0045] Step S104: Based on the data read address, read the target data from the source data storage unit, and based on the data write address, write the target data into the target storage unit to complete the data migration.

[0046] In this embodiment, the data read address and the data write address are corresponding. The data read address is the data storage address where the target data is read from the source data storage unit, while the data write address is the data storage address where the target data is stored in the target storage unit.

[0047] In one exemplary implementation, each data read address can correspond to a data write address, but the data read addresses or data write addresses corresponding to different groups can be the same. For example, the data read address can be 00, and the data write address can be 10. In this case, the target data with data storage address 00 is read from the source data storage unit and written to the location with data storage address 10 in the target storage unit. The next group's data write address is 20, and the data read address can still be 00. In this case, the target data with data storage address 00 is read from the source data storage unit and written to the location with data storage address 20 in the target storage unit. At this time, the data stored at data storage addresses 10 and 20 in the target storage unit are both the source data corresponding to address 00 in the source data storage unit.

[0048] It should be noted that, in order to ensure the uniqueness of the instruction result, the data read address in the source data storage unit and the data write address in the target storage unit need to be distinguished to avoid the data read address and data write address in the same group from overlapping, which would lead to data transfer errors.

[0049] In one embodiment, the step of reading target data from the source data storage unit based on the data read address and writing the target data into the target storage unit based on the data write address to complete the data migration includes:

[0050] When there are multiple dimensions of data read addresses and data write addresses, based on the same index data and the corresponding data read addresses and data write addresses of the same dimension, the target data corresponding to each dimension in the source data storage unit is moved to the target storage unit.

[0051] In one exemplary embodiment, the data storage address data of the source data storage unit and the target storage unit can be multidimensional tensor data, and the index data can also be multidimensional data. By parsing the index data, the multidimensional index data can be transformed into linear data to facilitate address search. For data migration between the source and target storage units in each dimension, the same index data can be used to index and migrate the data in each dimension sequentially.

[0052] In one exemplary embodiment, the data tensor in the source data storage unit can be four-dimensional data, which can be divided into four dimensions, such as dimension one, dimension two, dimension three, and dimension four, and the data format of the four dimensions is the same. The target storage unit can also contain four dimensions, which can correspond to the dimensions of the source data storage unit, but the data storage formats of the two can be different. For example, one dimension in the source data storage unit can store four data items, while one dimension in the target storage unit can store three data items. The data format of the index data can be the same as the data format of the source data storage unit or the target storage unit, such as corresponding to four data items and their data read / write addresses. For the migration of data in the source data storage unit, the corresponding data of dimensions one to four can be migrated separately, and each dimension can follow the migration rules of the index data for data migration.

[0053] This application provides a method for implementing SG instructions based on a DMA architecture. This method uses SG instructions to acquire index tensor data, parses the index tensor data to obtain the index data read address, reads the index data based on the read address, calculates the data read address and the data write address based on the index data, reads target data from the source data storage unit based on the read address, and writes the target data to the target storage unit based on the write address, thus completing the data migration. By parsing multidimensional index tensor data, linear index data is obtained, simplifying multidimensional data and reducing the difficulty of data indexing. The data read address and data write address are calculated based on the index data, and the target data can be read by querying the data read address in the source data storage unit. The target data is then moved to the corresponding data write address in the target storage unit, avoiding the parsing of complex data and improving data migration efficiency.

[0054] Please see Figure 3 , Figure 3 This is a flowchart illustrating a second embodiment of an SG instruction implementation method based on a DMA architecture provided in this application.

[0055] In this embodiment, based on the above... Figure 1 In the illustrated embodiment, prior to step S104, the method further includes:

[0056] Step S201: Based on preset address indexing rules, obtain the source data read address list of the source data storage unit or the target write address list of the target storage unit.

[0057] In this embodiment, the preset address indexing rule can be the index source data reading address, that is, the index of the data storage address of the source data storage unit, or the index target data writing address, that is, the index of the data storage address of the target storage unit storing the target data.

[0058] In one embodiment, the SG instructions include distribution instructions and collection instructions.

[0059] In one embodiment, when the SG instruction is a collection instruction, the preset address indexing rule is to index the source data read address and obtain the source data read address list of the source data storage unit; when the SG instruction is a distribution instruction, the preset indexing rule is to index the target write address and obtain the target write address list of the target storage unit.

[0060] Optionally, the address index can be performed in the source data storage unit or in the target storage unit.

[0061] In one exemplary implementation, in the data collection instruction, address indexing is performed in the source data storage unit. At this time, all data read addresses in the source data storage unit can be obtained, and a source data read address list can be generated. In the data distribution instruction, address indexing is performed in the target storage unit. At this time, the target write addresses of all data in the target storage unit can be obtained, and a target write address list can be generated.

[0062] In an exemplary implementation, in the data distribution instruction, the target data can be read from the source data storage unit in sequence according to the read address pre-configured in the distribution instruction and the instruction arrangement order. The write address in the target storage unit is calculated by the index tensor, and the target data is written to each write address in sequence according to the order of the write addresses, that is, it is transported to the target storage unit for storage.

[0063] In one embodiment, based on the above Figure 3 In the illustrated embodiment, reading target data from the source data storage unit based on the data read address includes:

[0064] When the preset address indexing rule is to index the source data read / write address, the data read address is searched based on the source data read address list;

[0065] When the data read address is found in the source data read address list, the corresponding target data is read from the source data storage unit based on the data read address.

[0066] If the data read address is not found in the source data read address list, a constant is generated based on the constant generation module and used as the target data.

[0067] In this embodiment, the index data and the target data storage unit have the same data format in the data collection instruction. The index data read and write address needs to be indexed in the source data storage unit, and then the valid data corresponding to the data read address is read according to the index result as the target data.

[0068] In one exemplary implementation, the index result can be one of two cases: one is that the index address, i.e., the data read address, is within the range of the source data read address list, in which case the valid data at the corresponding data read address is directly read as the target data; the other is that the index address is outside the range of the source data read address list.

[0069] In one exemplary implementation, when the index address, i.e., the data read address, is outside the range of the source data read address list, the data read / write address cannot be found in the source data storage unit, meaning no valid data can be read. In this case, a constant output is generated by the constant generation module to respond to the index request, and this constant is used as the target data.

[0070] In one embodiment, based on the above Figure 3 In the illustrated embodiment, the step of writing the target data into the target storage unit based on the data write address to complete the data migration includes:

[0071] When the preset address indexing rule is to index the target data read / write address, the data write address is searched based on the target write address list;

[0072] If the data write address is not found in the target write address list, the target data will not be output.

[0073] In this embodiment, the index data has the same data format as the source data storage unit in the data distribution instruction. The index data write address needs to be entered in the target storage unit. Then, the target data read from the source data storage unit is written to the corresponding data write address according to the index result, that is, stored in the target storage unit.

[0074] In one exemplary implementation, when a data write address is found in the target write address list, the target data read from the source data storage unit is written to that data write address.

[0075] In one exemplary implementation, when data is already stored in the searched data write address, if a subsequent data write address is also that address, the target data corresponding to the subsequent data write address will overwrite the existing data at that address. For example, if the data write address for a certain dimension is 1, and it already stores data 001, and if there is a data write address for transfer data that is also 1 and corresponds to the same dimension, and the target data to be saved is 100, then 100 will overwrite 001, and the stored data at the data storage address with data write address 1 in that dimension will be updated to 100.

[0076] In one exemplary implementation, if a data write address cannot be found in the target data write address list, it means that the data write address does not exist, the target storage unit cannot store the corresponding target data, and therefore the target data does not need to be output.

[0077] Please see Figure 4 , Figure 4 This is a schematic block diagram of an SG instruction implementation device based on a DMA architecture, provided in an embodiment of this application. This SG instruction implementation device based on a DMA architecture is used to execute the aforementioned SG instruction implementation method based on a DMA architecture. The SG instruction implementation device based on a DMA architecture can be configured in a server or a terminal.

[0078] like Figure 4 As shown, the SG instruction implementation device 200 based on DMA architecture includes: an index tensor data parsing module 201, an index data reading module 202, a data read / write address calculation module 203, and a data migration module 204.

[0079] The index tensor data parsing module 201 is used to obtain index tensor data based on SG instructions, parse the index tensor data, and obtain the index data read address of the index data.

[0080] Index data reading module 202 is used to read index data based on the data reading address of the index data;

[0081] The data read / write address calculation module 203 is used to calculate the data read address and the data write address based on the index data;

[0082] The data migration module 204 is used to read target data from the source data storage unit based on the data read address, and write the target data into the target storage unit based on the data write address to complete the data migration.

[0083] In one embodiment, the SG instruction implementation device 200 based on DMA architecture further includes a data address list acquisition module, which is used to acquire the source data read address list of the source data storage unit or the target write address list of the target storage unit based on a preset address index rule.

[0084] In one embodiment, the SG instruction includes a distribution instruction and a collection instruction. The data address list acquisition module is further configured to, when the SG instruction is a collection instruction, use the preset address indexing rule to index the source data read address and acquire the source data read address list of the source data storage unit; and when the SG instruction is a distribution instruction, use the preset indexing rule to index the target write address and acquire the target write address list of the target storage unit.

[0085] In one embodiment, the data migration module 204 is further configured to, when the preset address index rule is the source data read / write address, search for the data read address based on the source data read address list; and when the data read address is found in the source data read address list, read the corresponding target data in the source data storage unit based on the data read address.

[0086] In one embodiment, the data migration module 204 is further configured to generate a constant as the target data based on the constant generation module when the data read address is not found in the source data read address list.

[0087] In one embodiment, the data migration module 204 is further configured to, when the preset address indexing rule is to index the target data read / write address, search for the data write address based on the target write address list; and when the data write address is not found in the target write address list, not output the target data.

[0088] In one embodiment, the data migration module 204 is further configured to, when there are multiple dimensions of the data read address and the data write address, migrate the target data corresponding to each dimension in the source data storage unit to the target storage unit based on the same index data and the data read address and the data write address corresponding to the same dimension.

[0089] It should be noted that those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device and each module described above can be referred to the corresponding process in the aforementioned embodiment of the SG instruction implementation method based on the DMA architecture, and will not be repeated here.

[0090] The apparatus provided in the above embodiments can be implemented as a computer program, which can be used in, for example... Figure 5It runs on the computer device shown.

[0091] Please see Figure 5 , Figure 5 This is a schematic block diagram of the structure of a computer device provided in an embodiment of the present invention.

[0092] like Figure 5 As shown, the computer device 300 includes a processor 301 and a memory 302, which are connected via a bus 303, such as an I2C (Inter-integrated Circuit) bus.

[0093] Specifically, processor 301 provides computing and control capabilities to support the operation of the entire computer device. Processor 301 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0094] Specifically, the memory 302 can be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a portable hard drive, etc.

[0095] Those skilled in the art will understand that Figure 5 The structures shown are merely block diagrams of some structures related to the embodiments of the present invention, and do not constitute a limitation on the computer devices on which the embodiments of the present invention are applied. Specific computer devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0096] The processor is used to run a computer program stored in a memory, and when executing the computer program, implements any of the SG instruction implementation methods based on the DMA architecture provided in the embodiments of the present invention.

[0097] In one embodiment, the processor is configured to run a computer program stored in memory, and when executing the computer program, to perform the following steps:

[0098] Based on the SG instruction, the index tensor data is obtained, and the index tensor data is parsed to obtain the index data read address;

[0099] Read the index data based on the data read address of the index data;

[0100] Based on the index data, calculate the data read address and the data write address;

[0101] Based on the data read address, target data is read from the source data storage unit, and based on the data write address, the target data is written into the target storage unit to complete the data migration.

[0102] In one embodiment, before implementing the process of reading target data from the source data storage unit based on the data read address and writing the target data into the target storage unit based on the data write address to complete the data migration, the processor is further configured to implement:

[0103] Based on preset address indexing rules, obtain the source data read address list of the source data storage unit or the target write address list of the target storage unit.

[0104] In one embodiment, the SG instruction includes a dispatch instruction and a collection instruction. When the processor implements the process of obtaining the source data read address list of the source data storage unit or the target write address list of the target storage unit based on a preset address index rule, it is configured to:

[0105] When the SG instruction is a collection instruction, the preset address indexing rule is to index the source data read address and obtain the source data read address list of the source data storage unit;

[0106] When the SG instruction is a dispatch instruction, the preset indexing rule is to index the target write address and obtain the target write address list of the target storage unit.

[0107] In one embodiment, when the processor reads target data from the source data storage unit based on the data read address, it is configured to:

[0108] When the preset address indexing rule is to index the source data read / write address, the data read address is searched based on the source data read address list;

[0109] When the data read address is found in the source data read address list, the corresponding target data is read from the source data storage unit based on the data read address.

[0110] In one embodiment, after the processor performs the step of searching for the data read address based on the source data read address list when the preset address index rule is the index source data read / write address, it is further configured to perform the following:

[0111] If the data read address is not found in the source data read address list, a constant is generated based on the constant generation module and used as the target data.

[0112] In one embodiment, when the processor implements the step of writing the target data into the target storage unit based on the data write address to complete the data migration, it is configured to:

[0113] When the preset address indexing rule is to index the target data read / write address, the data write address is searched based on the target write address list;

[0114] If the data write address is not found in the target write address list, the target data will not be output.

[0115] In one embodiment, when the processor implements the process of reading target data from the source data storage unit based on the data read address and writing the target data into the target storage unit based on the data write address to complete the data migration, it is configured to:

[0116] When there are multiple dimensions of data read addresses and data write addresses, based on the same index data and the corresponding data read addresses and data write addresses of the same dimension, the target data corresponding to each dimension in the source data storage unit is moved to the target storage unit.

[0117] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the computer device described above can be referred to the corresponding process in the aforementioned embodiment of the SG instruction implementation method based on the DMA architecture, and will not be repeated here.

[0118] This invention also provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs that can be executed by one or more processors to implement any of the SG instruction implementation methods based on DMA architecture provided in the specification of this invention.

[0119] The storage medium can be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The storage medium can also be an external storage device of the computer device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0120] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware embodiments, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0121] It should be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0122] The sequence numbers of the above embodiments of the present invention are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The above descriptions are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for implementing SG instructions based on a DMA architecture, characterized in that, The method includes: Based on the SG instruction, the index tensor data is obtained, and the index tensor data is parsed to obtain the index data read address; Read the index data based on the index data read address; Based on the index data, calculate the data read address and the data write address; Based on the data read address, target data is read from the source data storage unit, and based on the data write address, the target data is written into the target storage unit to complete the data migration. The data tensors in the source data storage unit and the data tensors in the target storage unit have the same number of dimensions, and their dimension formats may be the same or different. For data migration in each dimension of the source and target storage units, the same index data is used, and the data in each dimension is indexed and migrated sequentially. The step of obtaining index tensor data based on SG instructions and parsing the index tensor data to obtain the index data read address includes: sending SG instructions to a command buffer, sending SG instructions to an index address calculation module through the command buffer, parsing SG instructions through the index address calculation module to generate a request to read the index tensor, and calculating the index data read address.

2. The SG instruction implementation method based on DMA architecture according to claim 1, characterized in that, Before the step of reading target data from the source data storage unit based on the data read address and writing the target data into the target storage unit based on the data write address to complete the data migration, the method further includes: Based on preset address indexing rules, obtain the source data read address list of the source data storage unit or the target write address list of the target storage unit.

3. The SG instruction implementation method based on DMA architecture according to claim 2, characterized in that, The SG instructions include distribution instructions and collection instructions. The step of obtaining the source data read address list of the source data storage unit or the target write address list of the target storage unit based on a preset address indexing rule includes: When the SG instruction is a collection instruction, the preset address indexing rule is to index the source data read address and obtain the source data read address list of the source data storage unit; When the SG instruction is a dispatch instruction, the preset address indexing rule is to index the target write address and obtain the target write address list of the target storage unit.

4. The SG instruction implementation method based on DMA architecture according to claim 3, characterized in that, The step of reading target data from the source data storage unit based on the data read address includes: When the preset address indexing rule is to index the source data read / write address, the data read address is searched based on the source data read address list; When the data read address is found in the source data read address list, the corresponding target data is read from the source data storage unit based on the data read address.

5. The SG instruction implementation method based on DMA architecture according to claim 4, characterized in that, When the preset address indexing rule is the source data read / write address, after searching for the data read address based on the source data read address list, the method further includes: If the data read address is not found in the source data read address list, a constant is generated based on the constant generation module and used as the target data.

6. The SG instruction implementation method based on DMA architecture according to claim 3, characterized in that, The step of writing the target data into the target storage unit based on the data write address to complete the data migration includes: When the preset address indexing rule is to index the target data read / write address, the data write address is searched based on the target write address list; If the data write address is not found in the target write address list, the target data will not be output.

7. The SG instruction implementation method based on DMA architecture according to any one of claims 1-6, characterized in that, The step of reading target data from the source data storage unit based on the data read address and writing the target data into the target storage unit based on the data write address to complete the data migration includes: When there are multiple dimensions of data read addresses and data write addresses, based on the same index data and the corresponding data read addresses and data write addresses of the same dimension, the target data corresponding to each dimension in the source data storage unit is moved to the target storage unit.

8. An SG instruction implementation device based on a DMA architecture, characterized in that, include: The index tensor data parsing module is used to obtain index tensor data based on SG instructions, parse the index tensor data, and obtain the index data read address of the index data; The index data reading module is used to read index data based on the index data reading address of the index data; The data read / write address calculation module is used to calculate the data read address and data write address based on the index data; The data migration module is used to read target data from the source data storage unit based on the data read address, and write the target data into the target storage unit based on the data write address to complete the data migration. The data tensors in the source data storage unit and the data tensors in the target storage unit have the same number of dimensions, and their dimension formats may be the same or different. For data migration of each dimension in both the source and target storage units, the same index data is used, and the data of each dimension is indexed and migrated sequentially. The index tensor data parsing module is also used to send SG instructions to the command buffer, send the SG instructions to the index address calculation module through the command buffer, parse the SG instructions through the index address calculation module, generate a request to read the index tensor, and calculate the read address of the index data.

9. A computer device, characterized in that, The computer device includes a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for implementing communication between the processor and the memory, wherein when the computer program is executed by the processor, it implements the SG instruction implementation method based on the DMA architecture as described in any one of claims 1 to 7.

10. A storage medium for computer-readable storage, characterized in that, The storage medium stores one or more programs, which can be executed by one or more processors to implement the SG instruction implementation method based on the DMA architecture as described in any one of claims 1 to 7.

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