Method, apparatus, device and medium for implementing bandwidth allocation by SPS

Abstract

The application belongs to the technical field of BIOS bandwidth allocation, and specifically provides a method, device, equipment and medium for realizing bandwidth allocation through SPS, which comprises the following steps: setting communication between BIOS and CPLD through SPS; setting BIOS to issue a command to CPLD through SPS to obtain configuration information of a server; and configuring PCIe bandwidth according to the obtained configuration information of the server. Unused SMLink SMBus clock / SMLink SMBus Data pins are connected to CPLD; SPS files are configured, corresponding pins are set as SMLink functions, and PMBUS functions are enabled; and data interaction with CPLD is realized by calling HECI drivers to execute PMBUS commands to obtain configuration information of a server, so that Host SMBus is prevented from being used by multiple devices, thereby avoiding channel congestion.

Description

Technical Field

[0001] This invention relates to the field of BIOS bandwidth allocation technology, and specifically to a method, apparatus, device, and medium for bandwidth allocation via SPS. Background Technology

[0002] In current server application scenarios, more and more scenarios require the BIOS to automatically allocate the bandwidth of the PCIe Port according to different configurations, so as to adapt to changes in various scenarios, adapt to the needs of the scenario in a timely manner, and take effect immediately, thereby reducing boot time and improving work efficiency and complexity.

[0003] The current main methods for BIOS bandwidth allocation are: 1. Manually modifying the BIOS menu to adapt to the usage scenario. This method is complex, requires a reboot to take effect, and is time-consuming; 2. The BIOS obtains the PCIe bandwidth requirements that need to be adapted through the BMC and then configures the bandwidth for the server. This method requires the BMC to cooperate, which increases coupling and may cause failure to obtain bandwidth information due to BMC malfunction; 3. The BIOS uses a set of GPIO signal values ​​to correspond to the current configuration requirements and sets the PCIe bandwidth according to the configuration requirements. This method requires the BIOS to parse each combination of GPIO values ​​and set the PCIe bandwidth according to the configuration corresponding to the GPIO values. This results in poor scalability, and the entire method is only completed by the BIOS, which increases complexity. If the bandwidth is abnormal, it is also difficult to troubleshoot the cause.

[0004] In view of the problems existing in the current BIOS bandwidth allocation method, it is very necessary to provide a method, device, equipment, and medium for bandwidth allocation through SPS. Summary of the Invention

[0005] Regarding the implementation scheme of BIOS bandwidth adaptive allocation, this invention proposes a method for BIOS to communicate with CPLD via SPS. The CPLD obtains the server's configuration information, and the BIOS then sets the PCIe bandwidth allocation. This scheme avoids the strong coupling effect of BMC and the complexity and poor scalability issues caused by GPIO-based schemes. Furthermore, the method of obtaining CPLD registers via SPS avoids the Host SMBus being used by multiple devices, preventing channel congestion. This invention provides a method, apparatus, device, and medium for bandwidth allocation via SPS.

[0006] In a first aspect, the present invention provides a method for bandwidth allocation via SPS, comprising the following steps:

[0007] Configure BIOS to communicate with CPLD via SPS;

[0008] Configure the BIOS to send commands to the CPLD via SPS to obtain the server's configuration information;

[0009] Configure the PCIe bandwidth based on the obtained server configuration information.

[0010] As a further limitation of the technical solution of the present invention, the step of setting up communication between BIOS and CPLD via SPS includes:

[0011] Connect any unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD;

[0012] Configure the SPS file, set the corresponding SMLink pin for SMLink function, and enable the PMBUS function.

[0013] As a further limitation of the technical solution of the present invention, the step of setting up communication between BIOS and CPLD via SPS also includes:

[0014] Define the addresses and commands related to CPLD.

[0015] As a further limitation of the technical solution of the present invention, the step of setting the BIOS to issue commands to the CPLD via SPS to obtain the server's configuration information includes:

[0016] The BIOS loads the HECI driver during the boot process;

[0017] The HECI driver is invoked to issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information.

[0018] As a further limitation of the technical solution of this invention, the steps of loading the HECI driver in the BIOS during the boot phase include:

[0019] The BIOS loads the HECI driver during the boot process;

[0020] Determine if loading was successful;

[0021] If so, the execution steps are as follows: Invoke the HECI driver and issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information;

[0022] If not, the end.

[0023] As a further limitation of the technical solution of the present invention, the step of calling the HECI driver and issuing commands according to the address and command value provided by the CPLD to obtain the server's configuration information includes:

[0024] Call the HECI driver;

[0025] Based on the address and command value provided by the CPLD, execute the HECI communication function to obtain the CPLD register information.

[0026] As a further limitation of the technical solution of the present invention, the steps of configuring the SPS file, setting the corresponding SMLink pin for use as SMLink function, and enabling the PMBUS function include:

[0027] Configure the corresponding configuration script in SPS to enable SMLink and PMBUS functions, allowing the BIOS to interact with the CPLD through the SMLink channel of SPS.

[0028] Current BIOS bandwidth allocation methods mainly include: 1. Manually modifying the BIOS menu to adapt to the usage scenario. This method is complex, requires a reboot to take effect, and is time-consuming; 2. The BIOS obtains the current PCIe bandwidth requirements through the BMC and then configures the bandwidth for the server. This method requires the BMC to cooperate, increasing coupling and potentially causing bandwidth information acquisition failure due to BMC malfunctions; 3. The BIOS uses a set of GPIO signal values ​​to correspond to the current configuration requirements and sets the PCIe bandwidth accordingly. This method requires the BIOS to parse each combination of GPIO values ​​and set the PCIe bandwidth based on the configuration corresponding to the GPIO values. This results in poor scalability, and the entire method relies solely on the BIOS, increasing complexity. Furthermore, troubleshooting bandwidth anomalies is difficult. This invention utilizes the SMLink bus built into the SPS to achieve information exchange between the BIOS and CPLD, thereby obtaining configuration information for PCIe bandwidth allocation. First, the hardware engineer needs to connect the unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; second, configure the SPS file, set the corresponding SMLink pins to be used as SMLink functions, and enable the PMBUS function; finally, in the BIOS, data interaction with the CPLD is achieved by calling the HECI driver to execute the PMBUS command.

[0029] Secondly, the present invention also provides a device for bandwidth allocation via SPS, comprising a first setting module, a second setting module, and a bandwidth allocation module;

[0030] The first configuration module is used to configure BIOS to communicate with CPLD via SPS;

[0031] The second configuration module is used to configure the BIOS to send commands to the CPLD via SPS to obtain the server's configuration information;

[0032] The bandwidth allocation module is used to configure PCIe bandwidth based on the obtained server configuration information.

[0033] As a further limitation of the technical solution of the present invention, the first setting module includes a connection setting unit and a configuration unit;

[0034] The connection setup unit is used to connect unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD.

[0035] The configuration unit is used to configure the SPS file, set the corresponding SMLink pin for use as the SMLink function, and enable the PMBUS function.

[0036] As a further limitation of the technical solution of the present invention, the first setting module also includes a definition unit for defining CPLD-related addresses and commands.

[0037] As a further limitation of the technical solution of the present invention, the second setting module includes a loading setting unit and a configuration information acquisition unit;

[0038] The loading configuration unit is used to configure the BIOS to load the HECI driver during the boot process;

[0039] The configuration information acquisition unit is used to call the HECI driver and issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information.

[0040] As a further limitation of the technical solution of the present invention, the loading setting unit includes a loading setting submodule and a judgment submodule;

[0041] The loading settings submodule is used to configure the loading of the HECI driver during the boot process;

[0042] The judgment submodule is used to determine whether the loading was successful; if so, the configuration information retrieval unit is triggered.

[0043] As a further limitation of the technical solution of the present invention, the configuration information acquisition unit includes a calling submodule and an acquisition submodule;

[0044] Call the submodule to invoke the HECI driver;

[0045] The Acquisition submodule is used to obtain CPLD register information by executing HECI communication functions based on the address and command value provided by the CPLD.

[0046] As a further limitation of the technical solution of the present invention, the configuration unit is specifically used to set the corresponding configuration script in SPS, enable SMLink function and PMBUS function, so that BIOS can interact with CPLD information through the SMLink channel of SPS.

[0047] Current BIOS bandwidth allocation methods mainly include: 1. Manually modifying the BIOS menu to adapt to the usage scenario. This method is complex, requires a reboot to take effect, and is time-consuming; 2. The BIOS obtains the PCIe bandwidth requirements that need to be adapted through the BMC and then configures the bandwidth for the server. This method requires the BMC to cooperate, increasing coupling and potentially causing bandwidth information acquisition failure due to BMC malfunctions; 3. The BIOS uses a set of GPIO signal values ​​to correspond to the current configuration requirements and sets the PCIe bandwidth accordingly. This method requires the BIOS to parse each combination of GPIO values ​​and set the PCIe bandwidth based on the configuration corresponding to the GPIO values. This results in poor scalability, and the entire method relies solely on the BIOS, increasing complexity. Furthermore, troubleshooting bandwidth anomalies is difficult. This invention utilizes the SMLink bus built into the SPS to achieve information exchange between the BIOS and CPLD, thereby obtaining configuration information for PCIe bandwidth allocation. First, the hardware engineer needs to connect the unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; second, configure the SPS file, set the corresponding SMLink pins to be used as SMLink functions, and enable the PMBUS function; finally, in the BIOS, data interaction with the CPLD is achieved by calling the HECI driver to execute the PMBUS command.

[0048] Thirdly, the present invention also provides an electronic device, the electronic device comprising:

[0049] At least one processor; and,

[0050] A memory communicatively connected to the at least one processor; wherein,

[0051] The memory stores computer program instructions that can be executed by at least one processor to enable the at least one processor to perform the bandwidth allocation method via SPS as described in the first aspect.

[0052] The main approach uses the SPS manager as a platform. The BIOS sends commands to the CPLD via the SPS to obtain configuration information. After obtaining the information from the CPLD, it configures the PCIe bandwidth accordingly. This solves both the coupling problem caused by the BMC method and the poor scalability problem caused by the GPIO method, and also facilitates subsequent problem analysis.

[0053] Fourthly, the present invention also provides a non-transitory computer-readable storage medium storing computer instructions that cause the computer to execute the bandwidth allocation method via SPS as described in the first aspect. The BIOS then sets the PCIe bandwidth allocation by obtaining the server's configuration information through the CPLD. This solution avoids the strong coupling effect of the BMC and the complexity and poor scalability issues associated with GPIO-based solutions. Furthermore, the method of obtaining the CPLD register via SPS avoids the Host SMBus being used by multiple devices, preventing channel congestion.

[0054] As can be seen from the above technical solution, this invention has the following advantages: It mainly uses an SPS manager as a carrier. The BIOS sends commands to the CPLD via the SPS to obtain configuration information. After obtaining the information from the CPLD, it configures the PCIe bandwidth according to the configuration information. This solves both the coupling problem caused by the BMC method and the poor scalability problem caused by the GPIO method, and also facilitates subsequent problem analysis.

[0055] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects.

[0056] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention.

[0059] Figure 2 This is a schematic flowchart of a method according to another embodiment of the present invention.

[0060] Figure 3 This is a schematic block diagram of an apparatus according to an embodiment of the present invention. Detailed Implementation

[0061] Current BIOS bandwidth allocation methods mainly include: 1. Manually modifying the BIOS menu to adapt to the usage scenario. This method is complex, requires a reboot to take effect, and is time-consuming; 2. The BIOS obtains the current PCIe bandwidth requirements through the BMC and then configures the bandwidth for the server. This method requires the BMC to cooperate, increasing coupling and potentially causing bandwidth information acquisition failure due to BMC malfunctions; 3. The BIOS uses a set of GPIO signal values ​​to correspond to the current configuration requirements and sets the PCIe bandwidth accordingly. This method requires the BIOS to parse each combination of GPIO values ​​and set the PCIe bandwidth based on the configuration corresponding to the GPIO values. This results in poor scalability, and the entire method relies solely on the BIOS, increasing complexity. Furthermore, troubleshooting bandwidth anomalies is difficult. This invention utilizes the SMLink bus built into the SPS to achieve information exchange between the BIOS and CPLD, thereby obtaining configuration information for PCIe bandwidth allocation. First, hardware engineers need to connect unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD. Second, they need to configure the SPS file, setting the corresponding SMLink pins for SMLink function and enabling PMBUS function. Finally, in the BIOS, data interaction with the CPLD is achieved by calling the HECI driver to execute the PMBUS command. The BIOS then configures the PCIe bandwidth allocation. This solution avoids the strong coupling effect of the BMC and the complexity and poor scalability issues caused by the GPIO solution. Furthermore, the solution of obtaining the CPLD registers through SPS avoids the Host SMBus being used by multiple devices, preventing channel congestion. To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0062] It should be noted that BIOS stands for Basic Input Output System.

[0063] SPS (Intel Server Platform Services) is a server platform management service.

[0064] CPLD (Complex Programmable Logic Device) generally refers to a complex programmable logic device.

[0065] like Figure 1 As shown, this embodiment of the invention provides a method for bandwidth allocation via SPS, comprising the following steps:

[0066] Step 1: Configure BIOS to communicate with CPLD via SPS;

[0067] Step 2: Configure the BIOS to send commands to the CPLD via SPS to obtain the server's configuration information;

[0068] Step 3: Configure PCIe bandwidth based on the obtained server configuration information.

[0069] The BIOS then uses the CPLD to obtain server configuration information and configures PCIe bandwidth allocation. This approach avoids the strong coupling of the BMC and the complexity and poor scalability issues associated with GPIO-based solutions. Furthermore, using the SPS to obtain CPLD register information prevents multiple devices from using the Host SMBus, thus avoiding channel congestion.

[0070] like Figure 2 As shown, this embodiment of the invention provides a method for bandwidth allocation via SPS, comprising the following steps:

[0071] S1: Connect any unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD;

[0072] S2: Define the addresses and commands related to the CPLD;

[0073] S3: Configure the SPS file, set the corresponding SMLink pin for SMLink function, and enable PMBUS function. In essence, this configures the corresponding script in the SPS, enabling both SMLink and PMBUS functions, allowing the BIOS to interact with the CPLD via the SPS's SMLink channel.

[0074] S4: The BIOS loads the HECI driver during the boot process;

[0075] S5: Determine if loading was successful;

[0076] If so, proceed to step S6;

[0077] If not, the end.

[0078] S6: Call the HECI driver and issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information;

[0079] S7: Configure PCIe bandwidth based on the obtained server configuration information.

[0080] This invention enables information exchange between the BIOS and CPLD via the SMLink bus built into the SPS, thereby obtaining configuration information for PCIe bandwidth allocation. First, the hardware engineer needs to connect any unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; second, configure the SPS file, setting the corresponding SMLink pins for SMLink function and enabling PMBUS functionality; finally, in the BIOS, data exchange with the CPLD is achieved by calling the HECI driver to execute the PMBUS command.

[0081] This invention provides a method for bandwidth allocation via SPS, with the following preliminary work:

[0082] First, the hardware engineer needs to connect the unused SMB_SML4_SCL and SMB_SML4_SDA pins to the CPLD to ensure that the hardware lines are properly connected.

[0083] Secondly, as the Master device, the CPLD defines the relevant address and command, and the BIOS obtains the relevant data information by issuing the command through the corresponding address;

[0084] Then, configure the corresponding script in SPS to enable SMLink and Pmbus functions, so that the BIOS can interact with CPLD information through the SMLink channel of SPS.

[0085] The preliminary work has been completed. The next step is for the BIOS to call the driver and exchange information with the CPLD. The specific steps are as follows:

[0086] 1. The BIOS successfully loads the HECI driver during the boot process;

[0087] 2. The HECI driver is invoked, using the Address and Command values ​​provided by the CPLD, as well as the Flag, sensorBus, and channel information required by the SPS communication protocol, as input parameters to execute the HeciSendAndReceive driver function.

[0088] 3. Obtain the data information from the CPLD through the returned information and save the data for later use.

[0089] The main approach uses the SPS manager as a platform. The BIOS sends commands to the CPLD via the SPS to obtain configuration information. After obtaining the information from the CPLD, it configures the PCIe bandwidth accordingly. This solves both the coupling problem caused by the BMC method and the poor scalability problem caused by the GPIO method, and also facilitates subsequent problem analysis.

[0090] like Figure 3 As shown, this embodiment of the invention also provides an apparatus for bandwidth allocation via SPS, including a first setting module, a second setting module, and a bandwidth allocation module;

[0091] The first configuration module is used to configure BIOS to communicate with CPLD via SPS;

[0092] The second configuration module is used to configure the BIOS to send commands to the CPLD via SPS to obtain the server's configuration information;

[0093] The bandwidth allocation module is used to configure PCIe bandwidth based on the obtained server configuration information.

[0094] This invention also provides an apparatus for bandwidth allocation via SPS, comprising a first setting module, a second setting module, and a bandwidth allocation module;

[0095] The first configuration module is used to configure the communication between the BIOS and the CPLD via SPS; the first configuration module includes a connection configuration unit, a configuration unit, and a definition unit.

[0096] The connection setup unit is used to connect unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; the configuration unit is used to configure the SPS file, set the corresponding SMLink pins for SMLink function use, and enable PMBUS function; the definition unit is used to define CPLD-related addresses and commands.

[0097] The second setting module is used to configure the BIOS to issue commands to the CPLD via SPS to obtain the server's configuration information; the second setting module includes a loading setting unit and a configuration information acquisition unit;

[0098] The loading and setting unit is used to configure the BIOS to load the HECI driver during the boot process; the configuration information acquisition unit is used to call the HECI driver and issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information.

[0099] The bandwidth allocation module is used to configure PCIe bandwidth based on the obtained server configuration information.

[0100] The loading settings unit includes a loading settings submodule and a judgment submodule;

[0101] The loading settings submodule is used to configure the loading of the HECI driver during the boot process; the judgment submodule is used to determine whether the loading was successful; if so, the configuration information acquisition unit is triggered.

[0102] The configuration information acquisition unit includes calling submodules and acquiring submodules;

[0103] The calling submodule is used to call the HECI driver; the obtaining submodule is used to execute the HECI communication function to obtain CPLD register information based on the address and command value provided by the CPLD.

[0104] The configuration unit is specifically used to set the corresponding configuration script in the SPS, enable the SMLink and PMBUS functions, and enable the BIOS to interact with the CPLD through the SMLink channel of the SPS.

[0105] This invention also provides an electronic device, comprising: a processor, a communication interface, a memory, and a bus, wherein the processor, communication interface, and memory communicate with each other via the bus. The bus can be used for information transmission between the electronic device and sensors. The processor can call logical instructions in the memory to execute the following methods: S1: Connect unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; S2: Define CPLD-related addresses and commands; S3: Configure the SPS file, set the corresponding SMLink pins for SMLink function use, and enable PMBUS function. In practice, setting the corresponding configuration script in the SPS enables SMLink and PMBUS functions, allowing the BIOS to interact with the CPLD through the SMLink channel of the SPS. S4: The BIOS loads the HECI driver during the boot phase; S5: Determine if loading is successful; if yes, proceed to step S6; if no, end. S6: Call the HECI driver, and issue commands based on the address and command values ​​provided by the CPLD to obtain server configuration information; S7: Configure PCIe bandwidth based on the obtained server configuration information. Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] This invention provides a non-transitory computer-readable storage medium storing computer instructions that cause a computer to execute the methods provided in the above-described method embodiments. For example, the instructions include: S1: Connecting unused SMLink SMBus clock / SMLink SMBus Data pins to the CPLD; S2: Defining CPLD-related addresses and commands; S3: Configuring the SPS file, setting the corresponding SMLink pins for SMLink function use, and enabling the PMBUS function. In practice, the corresponding configuration script in the SPS is set to enable the SMLink and PMBUS functions, allowing the BIOS to interact with the CPLD through the SMLink channel of the SPS. S4: The BIOS loads the HECI driver during the boot process; S5: Determining if loading was successful; if yes, proceed to step S6; otherwise, end. S6: Calling the HECI driver, issuing commands based on the address and command values ​​provided by the CPLD to obtain server configuration information; S7: Configuring PCIe bandwidth based on the obtained server configuration information.

[0107] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A method for bandwidth allocation via SPS, characterized in that, Includes the following steps: Configure BIOS to communicate with CPLD via SPS; connect unused SMLink SMBus clock / SMLinkSMBus Data pins to CPLD; define CPLD-related addresses and commands; configure the SPS file, set the corresponding SMLink pins for SMLink function, and enable PMBUS function, so that BIOS can interact with CPLD through the SMLink channel of SPS. The BIOS is configured to issue commands to the CPLD via SPS to obtain the server's configuration information. Specifically, during the boot process, the BIOS loads the HECI driver, calls the HECI driver, and issues PMBUS commands based on the address and command value provided by the CPLD to obtain the server configuration information in the CPLD registers. Configure the PCIe bandwidth based on the obtained server configuration information.

2. The method for bandwidth allocation via SPS according to claim 1, characterized in that, The steps by which the BIOS loads the HECI driver during the boot process include: The BIOS loads the HECI driver during the boot process; Determine if loading was successful; If so, the execution steps are as follows: Invoke the HECI driver and issue commands based on the address and command value provided by the CPLD to obtain the server's configuration information; If not, the end.

3. The method for bandwidth allocation via SPS according to claim 2, characterized in that, The steps involved in using the HECI driver to issue commands based on the address and command values ​​provided by the CPLD to obtain server configuration information include: Call the HECI driver; Based on the address and command value provided by the CPLD, execute the HECI communication function to obtain the CPLD register information.

4. An apparatus for bandwidth allocation via SPS, characterized in that, The apparatus for implementing the method according to any one of claims 1-3 includes a first setting module, a second setting module, and a bandwidth allocation module; The first configuration module is used to configure BIOS to communicate with CPLD via SPS; The second configuration module is used to configure the BIOS to send commands to the CPLD via SPS to obtain the server's configuration information; The bandwidth allocation module is used to configure PCIe bandwidth based on the obtained server configuration information.

5. An electronic device, characterized in that, The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores computer program instructions executable by the at least one processor, the computer program instructions being executed by the at least one processor to enable the at least one processor to perform the method of bandwidth allocation via SPS as described in any one of claims 1 to 3.

6. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions that cause the computer to perform the method of bandwidth allocation via SPS as described in any one of claims 1 to 3.

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