A data transmission system, method, device, and medium

Abstract

The application discloses a data transmission system, method, device and medium. The data transmission system comprises a first motion control board and a second motion control board. The first motion control board comprises a first programmable logic array and a first digital signal processing module. The first programmable logic array is used for receiving a target data packet to be written sent by the second motion control board, and sending a first GPIO level signal to the first digital signal processing module when sending the target data packet to be written to the first digital signal processing module. The first digital signal processing module is used for entering an interrupt service routine based on the received first GPIO level signal after receiving the first GPIO level signal, and reading the received data. The technical scheme of the embodiment of the application reduces the SRIO data transmission time, improves the data transmission efficiency, and reduces the limitation of the application scene.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a data transmission system, method, device, and medium. Background Technology

[0002] SRIO (Serial Rapid I / O), an important branch of RapidIO, is a next-generation high-speed interconnect technology based on packet switching, offering high reliability and performance for embedded system development. It achieves a minimal pin count, supports complex and scalable topologies, and enables multi-point transmission. It is ideally suited for large-scale data transmission between chips and boards.

[0003] like Figure 1 As shown, the classic SRIO data transmission process is as follows: (1) The DSP (Digital Signal Processing) of MCB (Motion Control Board) ① first writes the target data into the FPGA (Field Programmable Gate Array) of MCB ①; (2) The FPGA of MCB ① writes the target data into the FPGA of MCB ②; (3) After receiving the target data, the FPGA of MCB ② writes the target data into the address corresponding to the DSP of MCB ②; (4) The DSP of MCB ① transmits the DOORBELL (doorbell event), and the FPGA of MCB ① transmits the DOORBELL transparently; (5) After receiving the DOORBELL, the FPGA of MCB ② transmits the DOORBELL to the DSP of MCB ②, triggering an interrupt. See the timing diagram of the classic SRIO data transmission process. Figure 2A classic SRIO data transmission process involves the following steps: The DSP of MCB1 configures the SRIO transmission parameters; the SRIO module packages the target data from the DSP's memory (e.g., DDR3) and transmits it to the FPGA of MCB1; the FPGA of MCB1 receives the data packet carrying the target data and transmits it via fiber optic cable; the FPGA of MCB2 receives and transmits the data packet carrying the target data; the SRIO module of the MCB2 DSP saves the target data to the DSP's memory; the DSP of MCB1 configures the SRIO transmission parameters; the SRIO module transmits the DOORBELL-type data packet from the DSP of MCB1 to the FPGA of MCB1; the FPGA of MCB1 receives and transmits the DOORBELL-type data packet via fiber optic cable; the FPGA of MCB2 receives and transmits the DOORBELL-type data packet; the SRIO module of the MCB2 DSP sends the DOORBELL-type data packet to the DSP of MCB2; the DOORBELL interrupt of the MCB2 DSP is triggered, and the received target data is read. It is evident that the doorbell event in classic SRIO data transmission is transmitted serially, inevitably resulting in long data transmission times and low efficiency.

[0004] However, when using flag bits to complete SRIO data transmission, there are problems such as poor read / write flexibility, the need for specific protocol constraints, and poor timeliness. When using DSP-DSP SRIO for direct data transmission, specific hardware such as a switching board is required, which has strong limitations. Summary of the Invention

[0005] This invention provides a data transmission system, method, device, and medium to solve the problems of long data transmission time, low efficiency, and strong limitations of SRIO.

[0006] According to one aspect of the present invention, a data transmission system is provided, including a first motion control board and a second motion control board, the first motion control board and the second motion control board being communicatively connected; wherein, the first motion control board includes a first programmable logic array and a first digital signal processing module;

[0007] The first programmable logic array is used to receive the target data packet to be written sent by the second motion control board, and to send the first GPIO level signal to the first digital signal processing module when sending the target data packet to be written to the first digital signal processing module.

[0008] The first digital signal processing module is used to enter the interrupt service routine based on the received first GPIO level signal after receiving the first GPIO level signal, and read the received data.

[0009] According to another aspect of the present invention, a data transmission method is provided, applied to a first motion control board, comprising:

[0010] The system receives the target data packet to be written from the second motion control board via the first programmable logic array, and sends a first GPIO level signal to the first digital signal processing module when sending the target data packet to be written to the first digital signal processing module.

[0011] Upon receiving the first GPIO level signal, the first digital signal processing module enters the interrupt service routine based on the received first GPIO level signal to read the received data.

[0012] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0013] At least one processor; and

[0014] A memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method described in any embodiment of the present invention.

[0016] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the data transmission method described in any embodiment of the present invention.

[0017] The technical solution of this invention uses a first motion control board and a second motion control board to form a data transmission system. Based on the first programmable logic array of the first motion control board, it receives the target data packet to be written sent by the second motion control board. When sending the target data packet to be written to the first digital signal processing module, it sends a first GPIO level signal to the first digital signal processing module. After receiving the first GPIO level signal, the first digital signal processing module enters an interrupt service routine based on the received first GPIO level signal to read the received data. Since the motion control board uses an SRIO interface for data transmission and event notification, this solution uses the first GPIO level signal to replace the doorbell event, achieving synchronization of data transmission and notification. That is, the data transmission of the target data packet to be written is synchronized with the notification to the first digital signal processing module for data reading. Furthermore, the GPIO level signal is more efficient for event notification than the doorbell event, effectively improving the data transmission rate. Moreover, this solution has no specific constraints on the protocol or hardware, solving the problems of long data transmission time, low efficiency, and strong limitations of existing SRIO data transmission methods. It reduces SRIO data transmission time, improves data transmission efficiency, and reduces the limitations of application scenarios.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a classic SRIO data transmission process provided in the background art of this invention;

[0021] Figure 2 This is a schematic diagram of a classic SRIO data transmission timing provided in the background technology of this invention;

[0022] Figure 3 This is a schematic diagram of a data transmission system provided in Embodiment 1 of the present invention;

[0023] Figure 4 This is a schematic diagram of throughput test results for different SRIO transaction types provided in Embodiment 1 of the present invention;

[0024] Figure 5This is a schematic diagram of an SRIO data flow provided in Embodiment 1 of the present invention;

[0025] Figure 6 This is a timing diagram of SRIO data transmission provided in Embodiment 1 of the present invention;

[0026] Figure 7 This is a schematic diagram of the data flow for feedback control provided in Embodiment 1 of the present invention;

[0027] Figure 8 This is a timing diagram of SRIO data transmission corresponding to feedback control provided in Embodiment 1 of the present invention;

[0028] Figure 9 A flowchart of a data transmission method provided in Embodiment 2 of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of a semiconductor device board box provided in Embodiment 3 of the present invention;

[0030] Figure 11 This is a schematic diagram of the structure of a motion control board provided in Embodiment 3 of the present invention;

[0031] Figure 12 This is an operational logic diagram of a motion control board provided in Embodiment 3 of the present invention;

[0032] Figure 13 This is a comparison chart of the impact of SRIO communication duration on performance provided in Embodiment 3 of the present invention;

[0033] Figure 14 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Example 1

[0037] Figure 3 This is a schematic diagram of a data transmission system provided in Embodiment 1 of the present invention, as shown below. Figure 3 As shown, the data transmission system includes a first motion control board 110 and a second motion control board 120, which are communicatively connected. The first motion control board 110 includes a first programmable logic array 111 and a first digital signal processing module 112.

[0038] The first programmable logic array 111 can be used to receive the target data packet to be written sent by the second motion control board 120, and send a first GPIO level signal to the first digital signal processing module 112 when sending the target data packet to be written; the first digital signal processing module 112 can be used to enter the interrupt service routine based on the received first GPIO level signal after receiving the first GPIO level signal, and read the received data.

[0039] The first motion control board 110 and the second motion control board 120 can be two motion control boards in a data transmission system. The first programmable logic array 111 can be a programmable logic array in the first motion control board 110. The first digital signal processing module 112 can be a digital signal processor in the first motion control board 110. The target data packet to be written can be a data packet sent from the second motion control board 120 to the first motion control board 110 and stored by the first motion control board 110. The first GPIO level signal can be a GPIO signal sent from the first programmable logic array 111 to the first digital signal processing module 112.

[0040] In this embodiment of the invention, the second motion control board 120 can package the data to be sent to the first operation control board 110 into a target data packet to be written, and then send the target data packet to the first programmable logic array 111 of the first operation control board 110. The first programmable logic array 111 then sends the target data packet to the first digital signal processing module 112 via the SRIO interface. After the first programmable logic array 111 begins transmitting the target data packet to the first digital signal processing module 112 via the SRIO interface, it immediately sends a first GPIO level signal to the first digital signal processing module 112. Since the first GPIO level signal can be used as a trigger signal for an interrupt handler, when the first digital signal processing module 112 receives the GPIO level signal sent by the first programmable logic array 111, it can trigger an interrupt handler based on the first GPIO level signal and enter the interrupt service routine. At this time, the first digital signal processing module 112 can read the received data.

[0041] Optionally, when the memory area of ​​the first digital signal processing module 112 fails to successfully store the target data packet to be written, the data read is the data transmitted to the memory area of ​​the first digital signal processing module 112 in the previous data transmission cycle. When the memory area of ​​the first digital signal processing module 112 successfully writes the target data packet to be written, the data read can be the target data packet to be written.

[0042] By using GPIO level signals to transmit interrupt notifications concurrently, the time consumed by serially sending Doorbell signals is eliminated, significantly improving the transmission speed. This fully utilizes the parallel computing capabilities of FPGAs, enabling the simultaneous reading of received interrupt data while transmitting data.

[0043] This solution improves upon the serial notification method for doorbell events by sending data transmission and transmission completion notifications in parallel with a reasonable timing sequence. Without changing the hardware structure, SRIO protocol, or yield, this simple improvement significantly increases the data transmission throughput of SRIO, a critical communication method for semiconductor devices, achieving higher productivity.

[0044] In an optional embodiment of the present invention, the second motion control board may include a second digital signal processing module and a second programmable logic array. The second digital signal processing module may be used to write the target data packet to be written to the second programmable logic array according to the stream write operation transaction through the second SRIO module; the second programmable logic array may be used to forward the target data packet to be written to the first programmable logic array of the first motion control board.

[0045] The second digital signal processing module can be a digital signal processor in the second motion control board. The second programmable logic array can be a programmable logic array in the second motion control board. The second SRIO module can be an SRIO interface configured on the second motion control board for inter-board or intra-board SRIO communication of the digital signal processor and / or programmable logic array.

[0046] In this embodiment of the invention, the second digital signal processing module of the second motion control board can first configure the transmission parameters of the second SRIO module, and then package the data to be sent to the first motion control board from the local memory into a target data packet to be written. The second SRIO module, having completed the parameter configuration, then writes the target data packet to the second programmable logic array according to the stream write operation transaction. After the target data packet is successfully written to the second programmable logic array, it is forwarded to the first programmable logic array of the first motion control board via optical fiber or a backplane.

[0047] In an optional embodiment of the present invention, the first digital signal processing module may further be used to write the target data packet to be written to the target memory according to the stream write operation transaction through the first SRIO module.

[0048] The first SRIO module can be an SRIO interface configured on the first motion control board 110 for inter-board or intra-board SRIO communication with a digital signal processor and / or programmable logic array. The target memory can be a timing logic circuit for storing data in the first digital signal processing module 112. The stream write operation transaction can be a SWRITE transaction.

[0049] SWRITE transactions are equivalent to using NWRITE transactions to transmit double-words, but with less header overhead.

[0050] In this embodiment of the invention, the first programmable logic array 111 can buffer the target data packet to be written into the first SRIO module, and the first SRIO module writes the target data packet to be written into the target memory of the first digital signal processing module 112 according to the stream write operation transaction. The first SRIO module writes the target data packet to be written into the target memory through the stream write operation transaction, i.e., the SWRITE transaction, which can reduce the header overhead of the data packet and achieve the effect of minimizing the time limit and maximizing the throughput of SRIO single packet data transmission.

[0051] It should be noted that the data reading operation of the first digital signal processing module 112 and the data writing operation in the target memory are two independent operations, without any time sequence restrictions.

[0052] Figure 4The results are the throughput test results for the following four SRIO transaction types (SWRITE transaction, NWRITE transaction, SRIO protocol type 9 transaction, and SRIO protocol type 11 transaction). According to the test results, it can be seen that using SWRITE for data transmission in this solution can achieve the effect of minimizing the time limit for SRIO single packet data transmission and maximizing throughput.

[0053] For example, Figure 5 A data flow diagram of SRIO is provided. Figure 5 The SRIO data transmission time includes: the second digital signal processing module of the second motion control board configuring the transmission parameters of the second SRIO module; the second SRIO module packaging the data in the memory (such as DDR3) of the second digital signal processing module of the second motion control board to obtain the target data packet to be written, and transmitting the target data packet to be written to the second programmable logic array of the second motion control board through the second SRIO module; the second programmable logic array receiving and transmitting the target data packet to be written to the first programmable logic array through optical fiber; the first programmable logic array of the first motion control board receiving and transmitting the target data packet to be written; after the transmission of the first programmable logic array starts, it immediately sends a first GPIO level signal; the first SRIO module of the first digital signal processing module of the first motion control board writing the target data in the target data packet to be written to the target memory of the first digital signal processing module; after the GPIO interrupt of the first digital signal processing module is triggered, it begins to read the data in the received target data packet to be written.

[0054] The timing of SRIO data transmission is as follows: Figure 6 As shown. The meanings of each time period are as follows: t1: The moment when the target data packet to be written is completed in the second digital signal processing module. t2: The moment when the target data packet to be written is completed in the second programmable logic array. The data transmission time on the optical fiber is extremely short and negligible. t3: ​​After the first programmable logic array sends the header packet of the target data packet to be written through the first SRIO module, it performs GPIO output, i.e., sends the first GPIO signal. t4: The moment when the first digital signal processing module receives the first GPIO level signal sent by the first programmable logic array, enters the interrupt service routine (GPIO interrupt), and begins reading the data transmitted from the first SRIO module. t5: The moment when the first digital signal processing module begins receiving the target data packet to be written sent by the first programmable logic array. t6: The moment when the first digital signal processing module finishes receiving the target data packet to be written. It should be noted that if the amount of data in the target data packet to be written is small, t5 can be earlier than t4.

[0055] The following table compares the SRIO transfer times under three different modes:

[0056] Table 1 SRIO Transmission Time Performance Comparison Table

[0057]

[0058]

[0059] As shown in Table 1, the data transmission system using this scheme saves 2Δt = 2*(11.938-6.575)µs (2 SRIO data transmissions) within one control cycle. If the control cycle is compressed from 200µs to (200-2Δt)µs, the yield improvement is close to (2Δt) / 200 = Δt% = 5.363%. If there are more complex multiple data transmissions within a single control cycle, the performance improvement is even more significant.

[0060] In an optional embodiment of the present invention, the first digital signal processing module may further be used to activate a data monitoring thread when a first GPIO level signal is received; refresh the data storage address based on the data monitoring thread to obtain the current data storage address and acquire the historical data storage address; and generate first feedback data or second feedback data based on the current data storage address and the historical data storage address.

[0061] The data monitoring thread can be a pre-set monitoring thread used to monitor the data storage address. The current data storage address can be the address in the target memory where the target data to be written, currently sent by the second motion control board, is stored. The historical data storage address can be the address in the target memory where data was sent in the previous data transmission cycle of the target data to be written cycle. The first feedback data can be used to indicate successful data update. The second feedback data can be used to indicate data update failure.

[0062] In this embodiment of the invention, the first digital signal processing module can activate the data monitoring thread when it receives the first GPIO level signal. The data monitoring thread refreshes the data storage address to obtain the current data storage address and obtains the historical data storage address of the data sent by the second motion control board in the target memory in the previous data transmission cycle. The current data storage address is then compared with the historical data storage address. If the current data storage address is different from the historical data storage address, first feedback data is generated. If the current data storage address is the same as the historical data storage address, second feedback data is generated.

[0063] In an optional embodiment of the present invention, the first digital signal processing module may also be used to send a second GPIO level signal to the first programmable logic array and suspend the data monitoring thread when generating the first feedback data.

[0064] The second GPIO level signal can be a GPIO signal sent by the first digital signal processing module to the first programmable logic array.

[0065] In this embodiment of the invention, if the first digital signal processing module generates first feedback data, it indicates that the data stored in the target memory has been successfully updated, that is, the target data packet to be written in the current data transmission cycle has been successfully written to the target memory. At this time, the first digital signal processing module can send a second GPIO level signal to the first programmable logic array (to notify the first programmable logic array that the first digital signal processing module has completed the writing of the latest target data to be written), which is equivalent to a feedback control. After sending the second GPIO level signal to the first programmable logic array, the data monitoring thread is suspended, thereby releasing the resource occupation of the thread.

[0066] SWRITE transactions do not require responses from the target, so once the transaction is processed by the target, no feedback is sent to the initiator. Providing feedback for data write operations ensures that the start time of data reading by the first digital signal processing module and the completion time of data transmission by the first SRIO module of the first programmable logic array are consistent, and adapts to different application scenarios as much as possible. The first digital signal processing module does not need to measure communication and interrupt response times beforehand, as the interrupt service routine logic is relatively simple and the response time is relatively stable. This solves the cumbersome data verification process on the first programmable logic array side. Adding parallel data verification on the first digital signal processing side effectively controls the stability of data transmission and improves the transmission rate. On the first programmable logic array side, it is not necessary to set different GPIO level signals relative to the data packet header trigger times for different versions, and feedback control greatly reduces the development and maintenance costs of the data transmission system, compensating for the lack of feedback information in SWRITE transactions and the long DoorBell latency. The data flow of feedback control in this scheme is as follows: Figure 7 As shown. The SRIO data transmission timing corresponding to feedback control is as follows. Figure 8 As shown. By comparing the timing of the doorbell event with the corresponding timing of the feedback control, and comparing the duration Δt1 of the doorbell event with the historical duration Δt2 of the feedback control, it can be seen that the feedback control in this scheme has a shorter duration and higher efficiency. Furthermore, before the feedback control ends, the second data signal processing module can complete the new data writing at time t1' and perform a new round of feedback control (ending at t7'), and so on, performing another round of feedback control from time t1" to t7". Since both the first GPIO level signal and the second GPIO level signal are GPIO signals, in Figure 8For ease of representation, the two are not distinguished, but they can be specifically distinguished according to the sender. That is, the GPIO corresponding to t3, t3' and t3” is the first GPIO level signal, and the GPIO corresponding to t7, t7' and t7” is the second GPIO level signal.

[0067] The data transmission system using this scheme allows for parallel feedback control and data verification and reception at the digital signal processing module level, without additional control cycle time. In other words, its time performance is consistent with the third transmission mode in Table 1 (SWRITE transaction performs data writing + first motion control board sends GPIO level signal).

[0068] In an optional embodiment of the present invention, the first digital signal processing module can be used to return to the operation of refreshing the data storage address based on the data monitoring thread after generating the second feedback data, until the first feedback data is not generated even after a preset time threshold is reached, then exit the data monitoring thread and feed back a timeout signal.

[0069] The preset duration threshold can be a pre-set upper limit for duration.

[0070] In this embodiment of the invention, if the first digital signal processing module generates second feedback data, it indicates that the data update in the target memory has failed, that is, the target data packet to be written in the current data transmission cycle has not been successfully written to the target memory. The operation of refreshing the data storage address based on the data monitoring thread can be returned. When the operation of repeatedly refreshing the data storage address reaches a preset time threshold after several retries, and the first feedback data is still not generated, it indicates that the writing of the target data packet to be written has been abnormal. The data monitoring thread can be exited and a timeout signal can be fed back to notify the operation and maintenance personnel to handle it in a timely manner.

[0071] The technical solution of this invention uses a first motion control board and a second motion control board to form a data transmission system. Based on the first programmable logic array of the first motion control board, it receives the target data packet to be written sent by the second motion control board. When sending the target data packet to be written to the first digital signal processing module, it sends a first GPIO level signal to the first digital signal processing module. After receiving the first GPIO level signal, the first digital signal processing module enters an interrupt service routine based on the received first GPIO level signal to read the received data. Since the motion control board uses an SRIO interface for data transmission and event notification, this solution uses the first GPIO level signal to replace the doorbell event, achieving synchronization of data transmission and notification. That is, the data transmission of the target data packet to be written is synchronized with the notification to the first digital signal processing module for data reading. Furthermore, the GPIO level signal is more efficient for event notification than the doorbell event, effectively improving the data transmission rate. It achieves the effect of minimizing the time limit and maximizing the throughput of SRIO single-packet data transmission. Moreover, this solution has no specific constraints on the protocol and hardware, solving the problems of long data transmission time, low efficiency, and strong limitations of existing SRIO systems. It reduces SRIO data transmission time, improves data transmission efficiency, and reduces the limitations of application scenarios.

[0072] Example 2

[0073] Figure 9 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention. This embodiment is applicable to high-efficiency SRIO data transmission. The method can be implemented using a first motion control board, which can be configured in the data transmission system. Figure 9 As shown, the method includes:

[0074] S210: Receive the target data packet to be written sent by the second motion control board through the first programmable logic array, and send a first GPIO level signal to the first digital signal processing module when sending the target data packet to be written to the first digital signal processing module.

[0075] In this embodiment of the invention, the first motion control board can receive the target data packet to be written sent by the second motion control board through the first programmable logic array. After the first programmable logic array starts transmitting the target data packet to the first digital signal processing module, it immediately sends a first GPIO level signal to the first digital signal processing module.

[0076] S220. After receiving the first GPIO level signal, the first digital signal processing module enters the interrupt service routine based on the received first GPIO level signal to read the received data.

[0077] In this embodiment of the invention, after receiving the first GPIO level signal, the first digital signal processing module of the first motion control board can trigger an interrupt handler based on the first GPIO level signal, enter the interrupt service routine, and read the received data by the first digital signal processing module.

[0078] Optionally, the second motion control board may include a second digital signal processing module and a second programmable logic array; the second digital signal processing module can be used to write the target data packet to be written to the second programmable logic array according to the stream write operation transaction through the second SRIO module. The second programmable logic array can be used to forward the target data packet to be written to the first programmable logic array of the first motion control board.

[0079] Optionally, after receiving the first GPIO level signal, the process may further include: activating a data monitoring thread through a first digital signal processing module; refreshing the data storage address based on the data monitoring thread to obtain the current data storage address and acquire the historical data storage address; and generating first feedback data or second feedback data through the first digital signal processing module based on the current data storage address and the historical data storage address.

[0080] Optionally, the first digital signal processing module is also used to write the target data packet to be written to the target memory according to the stream write operation transaction through the first SRIO module.

[0081] Optionally, after generating the first feedback data, the process may further include: sending a second GPIO level signal to the first programmable logic array through the first digital signal processing module, and suspending the data monitoring thread.

[0082] Optionally, after generating the second feedback data, the process may further include: returning to perform the operation of refreshing the data storage address based on the data monitoring thread until the preset time threshold is reached and the first feedback data is not generated, then exiting the data monitoring thread and sending a timeout signal.

[0083] The technical solution of this invention receives a target data packet to be written from a second motion control board via a first programmable logic array. When sending the target data packet to a first digital signal processing module, a first GPIO level signal is sent to the first digital signal processing module. Upon receiving the first GPIO level signal, the first digital signal processing module enters an interrupt service routine based on the received signal to read the received data. In this solution, the first GPIO level signal replaces the doorbell event, achieving synchronization between data transmission and notification. That is, the data transmission of the target data packet to be written is synchronized with the notification to the first digital signal processing module for data reading. Furthermore, the GPIO level signal is more efficient for event notification than the doorbell event, effectively improving the data transmission rate. Moreover, this solution has no specific constraints on the protocol or hardware, solving the problems of long data transmission time, low efficiency, and strong limitations of existing SRIO data transmission methods. It reduces SRIO data transmission time, improves data transmission efficiency, and reduces the limitations of application scenarios.

[0084] Example 3

[0085] Embodiment 3 of the present invention provides an application scenario for a data transmission system. The specific implementation of the system can be found in the following embodiments. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0086] The structure of a typical semiconductor device board box is as follows: Figure 10 As shown, the two core motion control boards transmit data at high speed via fiber optic cable or a backplane.

[0087] The structure of the motion control board is as follows: Figure 11 As shown, the DSP is responsible for running the firmware, the FPGA is responsible for data transmission, and the FMC (FPGA Mezzanine Card) is a general-purpose module. General-purpose I / O ports are GPIO, used for outputting level signals, input capture, and RESET. The high-speed interface is the SRIO module, used for high-speed small data packet communication between cards. EMIF (External Memory Interface) is used for reading and writing to the DSP's external memory devices, and other buses handle high-speed or low-speed data transmission.

[0088] Taking motion control as an example, within the control cycle (firmware cycle, 200µs as an example), the two MCBs respectively complete the following functions to achieve synchronization and overall operation. The specific operating logic is as follows: Figure 12As shown: (1) MCB ① waits for the position data calculated by MCB ②; (2) MCB ② runs the sampling process and sends the calculated position to MCB ①, then MCB ② waits for the force data from MCB ①; (3) After obtaining the position data, MCB ① calculates the force data and sends it to MCB ②; (4) After receiving the force data, MCB ② runs the algorithm; (5) After that, MCB ① and MCB ② run other functions to guide the end of one control cycle.

[0089] Force and position data are transmitted via the SRIO module. The longer the SRIO transmission time, the less time is available for algorithms and other functions; therefore, SRIO transmission time affects overall system performance. Increasing SRIO transmission speed allows for more complex algorithms or shorter control cycles, ensuring higher accuracy or faster response times in motion control, thereby reducing control errors. Figure 13 This demonstrates the impact of SRIO communication duration on performance, showing that this solution can effectively improve productivity and control accuracy by reducing SRIO communication duration.

[0090] Example 4

[0091] Figure 14 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0092] like Figure 14 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0093] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] Processor 11 may be a general-purpose and / or dedicated processing component with processing and computing capabilities configured in a first motion control board of an electronic device. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data transfer methods.

[0095] In some embodiments, the data transfer method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data transfer method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the data transfer method by any other suitable means (e.g., by means of firmware).

[0096] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0098] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0100] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0101] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0102] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data transmission system, characterized in that, It includes a first motion control board and a second motion control board, which are communicatively connected; wherein, the first motion control board includes a first programmable logic array and a first digital signal processing module; The first programmable logic array is used to receive the target data packet to be written sent by the second motion control board, and when sending the target data packet to be written to the first digital signal processing module, send a general output first GPIO level signal to the first digital signal processing module; The first digital signal processing module is configured to, upon receiving the first GPIO level signal, enter an interrupt service routine based on the received first GPIO level signal and read the received data. The first digital signal processing module is further configured to activate the data monitoring thread when it receives the first GPIO level signal; The data monitoring thread refreshes the data storage address to obtain the current data storage address and acquires the historical data storage address; wherein, the current data storage address is the address where the target memory of the first digital signal processing module stores the target data to be written currently sent by the second motion control board; the historical data storage address is the address where the target memory stores the data sent in the previous data transmission cycle of the target data to be written data transmission cycle; Based on the current data storage address and the historical data storage address, generate either first feedback data or second feedback data; wherein, the first feedback data is used to indicate that the data update was successful; and the second feedback data is used to indicate that the data update failed. The first digital signal processing module is further configured to send a second GPIO level signal to the first programmable logic array and suspend the data monitoring thread when generating the first feedback data.

2. The system according to claim 1, characterized in that, The second motion control board includes a second digital signal processing module and a second programmable logic array, wherein, The second digital signal processing module is used to write the target data packet to be written to the second programmable logic array according to the stream write operation transaction through the second SRIO module; The second programmable logic array is used to forward the target data packet to be written to the first programmable logic array of the first motion control board.

3. The system according to claim 1, characterized in that, The first digital signal processing module is further configured to write the target data packet to be written to the target memory according to the stream write operation transaction through the first SRIO module.

4. The system according to claim 1, characterized in that, The first digital signal processing module is further configured to, after generating the second feedback data, return to perform the operation of refreshing the data storage address based on the data monitoring thread, until the first feedback data is not generated even after a preset time threshold is reached, then exit the data monitoring thread and send out a timeout signal.

5. A data transmission method, characterized in that, Applied to the first motion control board, including: The system receives the target data packet to be written from the second motion control board via the first programmable logic array, and sends a general output first GPIO level signal to the first digital signal processing module when sending the target data packet to the first digital signal processing module. Upon receiving the first GPIO level signal, the first digital signal processing module enters the interrupt service routine based on the received first GPIO level signal to read the received data. The step of receiving the first GPIO level signal further includes: The data monitoring thread is activated through the first digital signal processing module; The data monitoring thread refreshes the data storage address to obtain the current data storage address and acquires the historical data storage address; wherein, the current data storage address is the address where the target memory stores the target data to be written currently sent by the second motion control board; the historical data storage address is the address where the target memory stores the data sent in the previous data transmission cycle of the target data to be written data transmission cycle. The first digital signal processing module generates first feedback data or second feedback data based on the current data storage address and the historical data storage address; wherein, the first feedback data is used to indicate that the data update was successful; and the second feedback data is used to indicate that the data update failed. After generating the first feedback data, the process also includes: The first digital signal processing module sends a second GPIO level signal to the first programmable logic array and suspends the data monitoring thread.

6. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method of claim 5.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the data transmission method of claim 5.

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