Data transmission system and transmission method for a hardware emulator

Abstract

The application discloses a data transmission system and method of a hardware emulator. The data transmission system of the hardware emulator comprises a sending end and a receiving end connected through a low-voltage differential signal link and a link establishment signal line. The sending end comprises a sending controller and a sending data processing module. The receiving end comprises a receiving controller and a second data conversion module. After the sending controller and the receiving controller obtain a link establishment success signal through the link establishment signal line, the sending data processing module and the receiving data processing module are controlled to be in transmission synchronization, so that a to-be-transmitted signal of a first simulation chip connected to the sending end can be transmitted in at least one batch through the sending data processing module, and the signal transmitted in each batch is accurately transmitted to a corresponding receiving port of a second simulation chip connected to the receiving end through the receiving data processing module in transmission synchronization through the low-voltage differential signal link. The application can realize synchronous transmission of a large-bit-width LVDS link data.

Description

Technical Field

[0001] This invention belongs to the field of chip verification, and specifically relates to a time-division multiplexing (TDM) data transmission interconnection system and method based on a low-voltage differential signaling link (LVDS link) for hardware simulation accelerators and prototype verification systems. Background Technology

[0002] The IC chip industry is developing rapidly. To verify the functionality of chips, chip simulation verification is usually required in the early stages of chip development. When the design under test (DUT) is too large, the signals of the DUT need to be segmented and mapped to multiple simulation chips. However, many chip verification platforms interconnect simulation chips through a limited number of LVDS (Low-Voltage Differential Signaling) links in physical hardware. The number of LVDS links between FPGAs is determined during the hardware emulator design of the DUT. Currently, most LVDS link interconnection schemes are based on fixed-width data transmission, which cannot support large-scale, variable-width data transmission. Therefore, it is necessary to solve the problem of interconnecting variable-width data signals through LVDS links, especially the transmission of large-width signals through a limited number of LVDS links. For example, two FPGA simulation chips may only have 10 pairs of LVDS, but 10,000 signals need to be transmitted between them. Therefore, the data transmission system needs to be able to support variable widths and a large upper limit on the supported width.

[0003] Furthermore, existing data transmission interconnection systems rely on software configuration when establishing links, making automatic link establishment and hot-swapping impossible, resulting in a lack of convenience in application. Moreover, existing data transmission interconnection systems typically transmit data in packet form, requiring complete reception of the data packets before data can be recovered, leading to significant data transmission delays. Summary of the Invention

[0004] To address the technical problem of synchronizing data transmission between the sending and receiving ends in existing data transmission interconnection systems, this invention proposes a data transmission system and method using a hardware emulator.

[0005] The data transmission system of the hardware emulator proposed in this invention includes: a transmitter and a receiver connected by a low-voltage differential signal link and a link establishment signal line;

[0006] The transmitting end includes: a transmitting controller and a transmitting data processing module;

[0007] The receiving end includes: a receiving controller and a second data conversion module;

[0008] After the transmitting controller and receiving controller obtain the link establishment success signal through the link establishment signal line, they control the transmitting data processing module and the receiving data processing module to transmit synchronously, so that the signal to be transmitted from the first emulation chip connected to the transmitting end can be divided into at least one batch and transmitted through the transmitting data processing module. The signal transmitted in each batch is accurately transmitted to the receiving port corresponding to the second emulation chip connected to the receiving end through the low voltage differential signal link by the receiving data processing module that is synchronized with the transmission.

[0009] Furthermore, the data transmission processing module and / or the data reception processing module include at least one data selector and a timer;

[0010] Each input of the data selector of the transmitting data processing module is driven by a corresponding timer, and the output of the data selector of the receiving data processing module is driven by a corresponding timer.

[0011] After the sending controller and receiving controller obtain the link establishment success signal, they set the timers of the sending data processing module and the receiving data processing module to the same value so that the sending data processing module and the receiving data processing module transmit synchronously.

[0012] Furthermore, the data transmission processing module and / or the data reception processing module automatically select a corresponding number of data selectors to form a corresponding circuit based on the number of signals to be transmitted by the first simulation chip and the number of signals transmitted in each batch.

[0013] Furthermore, when the data selector is an 8:1 data selector, the number of data selectors in the transmitting data processing module or the receiving data processing module is R / 8, where R is the number of signals to be transmitted by the first simulation chip.

[0014] Furthermore, the transmitting end is connected to the LVDS link via a parallel-to-serial conversion module, and the receiving end is connected to the LVDS link via a serial-to-parallel conversion module.

[0015] Furthermore, the output of the transmitting data processing module is connected to the transmitting mode control module controlled by the transmitting controller; the input of the receiving data processing module is connected to the receiving mode processing module controlled by the receiving controller.

[0016] Furthermore, the transmitting controller and / or the receiving controller are implemented using a state machine.

[0017] Furthermore, the transmitting controller has at least one of a training state, a preamble state, and a signal transmission state; the receiving controller has at least one of an idle state, a bit sliding state, a preamble receiving state, and a signal receiving state.

[0018] Furthermore, when the transmitting controller detects that the receiving controller is in an idle state via the link establishment signal line, it enters the training state. Simultaneously, it notifies the transmitting mode control module to send training data to the LVDS link and notifies the receiving controller to control the receiving mode processing module to enter the bit sliding state. The receiving mode processing module performs bit sliding on the data transmitted from the LVDS link until the received data matches the training data. The receiving controller then informs the transmitting controller that the link establishment is successful, and the transmitting controller and the receiving controller each enter the next state.

[0019] Furthermore, the transmission mode control module receives the control signal from the transmission controller through the data selector and selects the input data of the input port corresponding to the data selector according to the control signal.

[0020] Furthermore, the receiving mode control module receives the control signal from the receiving controller through the data selector to perform bit sliding control for receiving data.

[0021] Furthermore, a verification module is provided between the data transmission processing module and the data transmission mode control module, and a deverification module is provided between the data reception mode processing module and the data reception processing module.

[0022] The present invention provides a data transmission method for a hardware emulator data transmission system based on the above-mentioned technical solution, comprising:

[0023] After the sending end establishes a connection with the receiving end, it sends preamble data to the receiving end.

[0024] The transmitting end and the receiving end generate corresponding circuits based on the data bit width of each batch sent by the first simulation chip, and transmit the signal of the first simulation chip to the corresponding receiving port of the second simulation chip.

[0025] Furthermore, when a verification error occurs in the signal sent by the first simulation chip, the sending end disconnects from the receiving end and prepares for the next connection establishment.

[0026] Furthermore, it also includes: when the sending end detects that no connection has been established with the receiving end, it sends training data to the receiving end;

[0027] The receiving end determines the data bit boundary through training data and sends a link establishment completion signal to the sending end.

[0028] Furthermore, the receiving end determines the data bit boundaries using training data, including:

[0029] The receive mode processing module performs cyclic shifting on the received data, and the state of each cyclic shift is controlled by a counter;

[0030] When the receiving mode processing module determines that the received data matches the training data, it keeps the counter unchanged, and the receiving controller outputs a training completion status signal to the transmitting controller, indicating that the transmitting controller and the receiving controller have successfully established a link.

[0031] Furthermore, when the output of the receiver controller via the link establishment signal line changes from low level to high level, it indicates that the receiver controller outputs a training completion status signal.

[0032] This invention enables LVDS link data transmission with arbitrary bit width. In a further embodiment, the invention can also automatically establish a link, enabling hot-plugging. Furthermore, the data transmission latency of this invention is relatively low. Attached Figure Description

[0033] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0034] Figure 1 This is a schematic block diagram of a system according to an embodiment of the present invention;

[0035] Figure 2 This is a flowchart of one embodiment of the present invention;

[0036] Figure 3 This is a circuit schematic diagram of a receiving mode processing module according to an embodiment of the present invention;

[0037] Figure 4 This is a circuit schematic diagram of a data transmission processing module according to an embodiment of the present invention;

[0038] Figure 5 This is a circuit schematic diagram of a data receiving and processing module according to an embodiment of the present invention;

[0039] Figure 6 This is a circuit schematic diagram of a CRC verification module according to an embodiment of the present invention;

[0040] Figure 7 This is a circuit schematic diagram of a CRC decryption and verification module according to an embodiment of the present invention;

[0041] Figure 8 This is a circuit schematic diagram of a transmission mode control module according to an embodiment of the present invention;

[0042] Figure 9 This is a circuit schematic diagram of an automatic link establishment and transmission controller according to an embodiment of the present invention;

[0043] Figure 10 This is a circuit schematic diagram of an automatic link establishment receiver controller according to an embodiment of the present invention;

[0044] Figure 11 This is a circuit schematic diagram of a CRC check error indication signal according to an embodiment of the present invention. Detailed Implementation

[0045] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0046] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0047] The data transmission system proposed in this invention includes a transmitter and a receiver. The transmitter is connected to a first simulation chip, and the receiver is connected to a second simulation chip. The transmitter and receiver are connected via a low-voltage differential signal link (LVDS link) and a link establishment signal line.

[0048] In one embodiment, the transmitting end includes a transmitting controller and a transmitting data processing module. The receiving end includes a receiving controller and a second data conversion module.

[0049] After the transmitting controller and receiving controller obtain the link establishment success signal through the link establishment signal line, they control the transmitting data processing module and the receiving data processing module to transmit synchronously. This allows the signal to be transmitted from the first emulation chip connected to the transmitting end to be divided into at least one batch and transmitted via the transmitting data processing module. Each batch of transmitted signal is accurately transmitted to the corresponding receiving port of the second emulation chip connected to the receiving end by the receiving data processing module through a low-voltage differential signal link.

[0050] The connection between the transmitting and receiving ends can be established through software or hardware circuitry. Since the signals transmitted between the first and second emulation chips are typically numerous and need to be transmitted in multiple batches, the technical solution described above ensures that a specific batch of data can be accurately sent to the corresponding receiving port of the second emulation chip. For example, there are usually tens of thousands of signal lines connecting the first and second emulation chips due to the cutting of the chip under test; that is, the first emulation chip needs to send tens of thousands of signals to the second emulation chip. The accurate transmission of each signal to the corresponding receiving port of the second emulation chip is primarily achieved by controlling the synchronization of the transmitting data processing module and the receiving data processing module.

[0051] In one specific embodiment, the transmitting data processing module and / or receiving data processing module include at least one data selector and a timer. Each input of the data selector in the transmitting data processing module is driven by a corresponding timer, and the output of the data selector in the receiving data processing module is driven by a corresponding timer. When the transmitting controller and the receiving controller receive a successful link establishment signal, they synchronize their transmission by setting the timers of the transmitting and receiving data processing modules to the same value. For example, after the transmitting and receiving controllers successfully establish a link, they can control the timers of the transmitting and receiving data processing modules to be set to 0. From this point onward, each data selector in the circuits of the transmitting and receiving data processing modules selects either the input or output of port 0. This embodiment allows the transmitting and receiving data processing modules to handle numerous signal lines between the first and second emulation chips with a very simple circuit structure.

[0052] In a preferred embodiment, the transmitting data processing module and / or receiving data processing module automatically select a corresponding number of data selectors to form a corresponding circuit based on the number of signals to be transmitted from the first emulation chip and the number of signals transmitted in each batch. This allows the data transmission system of the present invention to transmit signals of arbitrary bit width to meet the signal transmission requirements between two emulation chips.

[0053] In one specific embodiment, if the data selector selected by the transmitting data processing module and the receiving data processing module is an 8:1 data selector, the number of data selectors in the transmitting data processing module and the receiving data processing module is R / 8, where R is the number of signals to be transmitted by the first simulation chip. The transmitting end and the receiving end can automatically generate the circuits corresponding to the transmitting data processing module and the receiving data processing module based on the number of signals transmitted between the first simulation chip and the second simulation chip.

[0054] This invention is not limited to this one type of data selector; other types of data selectors can also be selected.

[0055] In a further embodiment, the transmitting end is connected to the LVDS link via a parallel-to-serial conversion module, and the receiving end is connected to the LVDS link via a serial-to-parallel conversion module. The parallel-to-serial and serial-to-parallel conversion modules can increase the transmission bandwidth between the transmitting and receiving ends.

[0056] Based on any of the above embodiments, the output of the transmitting data processing module is connected to the transmitting mode control module controlled by the transmitting controller; the input of the receiving data processing module is connected to the receiving mode processing module controlled by the receiving controller. The transmitting mode control module and the receiving mode processing module enable the transmitting end and the receiving end to transmit different data types.

[0057] In one embodiment, the transmitting controller and / or receiving controller are implemented using a state machine.

[0058] In one specific embodiment, the transmitting controller has at least one of a training state, a preamble state, and a signal transmission state; the receiving controller has at least one of an idle state, a bit sliding state, a preamble receiving state, and a signal receiving state.

[0059] When the transmitting controller is in training state and the receiving controller is in idle state and bit sliding state, the transmitting controller enters training state when it learns that the receiving controller is in idle state through the link establishment signal line. At the same time, it notifies the transmitting mode control module to send training data to the LVDS link and notifies the receiving controller to control the receiving mode processing module to enter bit sliding state. The receiving mode processing module performs bit sliding on the data transmitted from the LVDS link until the received data matches the training data. The receiving controller informs the transmitting controller that the link establishment is successful, and the transmitting controller and the receiving controller enter the next state respectively.

[0060] In one specific embodiment, the transmission mode control module receives the control signal from the transmission controller through the data selector and selects the input data of the input port corresponding to the data selector according to the control signal.

[0061] In one specific embodiment, the receive mode control module receives control signals from the receive controller via a data selector to perform bit sliding control for receiving data.

[0062] Based on the above embodiments, a verification module can be further provided between the data transmission processing module and the transmission mode control module, and a deverification module can be provided between the receiving mode processing module and the receiving data processing module. The verification module can verify the input data of the first simulation chip and generate a check bit, while the deverification module performs error checks on the data and check bit received by the receiving end. Through the verification module and the deverification module, the receiving end can know when the transmitting end is abnormal, thereby realizing a closed loop of automatic link establishment control, that is, when the transmitting end is abnormal, the link with the transmitting end is disconnected in a timely manner (the actual physical link is not disconnected, only the link state is disconnected).

[0063] Figure 1 A preferred embodiment of the data transmission system of the present invention is shown. In this embodiment, the data transmission system is specifically a TDM data transmission interconnection system based on an LVDS link, including a transmitting end and a receiving end. The transmitting end includes an automatic link establishment transmitting controller S105 (transmitting controller), a transmitting data TDM processing module S101 (transmitting data processing module), a CRC verification module S102 (verification module), a transmitting mode control module S103, and a parallel-to-serial conversion module S104. The receiving end includes an automatic link establishment receiving controller S110 (receiving controller), a receiving data TDM processing module S109 (receiving data processing module), a CRC de-verification module S108 (de-verification module), a receiving mode processing module S107, and a serial-to-parallel conversion module S106.

[0064] The automatic link establishment and transmission controller S105 is connected to the transmission mode control module S103 and the transmission data TDM processing module S101 respectively; the automatic link establishment and reception controller S110 is connected to the reception mode processing module S107, the CRC de-verification module S108, and the reception data TDM processing module S109 respectively; the parallel-to-serial conversion module is connected to the serial-to-parallel conversion module through the LVDS link.

[0065] The automatic link establishment transmitting controller S105 is connected to the automatic link establishment receiving controller S110, and the connection adopts single-ended logic level such as CMOS, TTL, etc.

[0066] A data transmission processing module is used to receive data signals from the first module. In one embodiment, the data transmission processing module may be a time-division multiplexing (TDM) processing module, which receives different data signals from the first module using time-division multiplexing technology.

[0067] The transmission mode control module is used to control the types of data transmitted by the parallel-to-serial conversion module. The types of data controlled by the transmission mode control module include: the data signal transmitted by the first module, the preamble, and the training data.

[0068] The parallel-to-serial conversion module is used to receive the data selected by the transmission mode control module in parallel and then send it to the serial-to-parallel conversion module at the receiving end through the LVDS link.

[0069] The serial-to-parallel conversion module is used to send data received from the LVDS link in parallel to the receive mode processing module.

[0070] The receive mode processing module receives control signals sent by the receive controller and determines the type of data received by the serial-to-parallel conversion module. For example, during the link establishment process between the receive controller and the transmit controller, the receive mode processing module continuously slides and shifts to align the data bits. After the link establishment is successful, it can also determine the preamble data and the signal transmitted by the first simulation chip.

[0071] The receiving data processing module is synchronized with the transmitting data processing module. When the transmitting data processing module uses time-division multiplexing (TDM) technology to transmit signals from the first simulation chip, the receiving data processing module mainly implements the reverse process of TDM. In one embodiment, the receiving data processing module can be a receiving data TDM processing module, which uses TDM technology to divide multiple data signals into at least one batch and transmit them to the receiving end of the second simulation chip.

[0072] The automatic link establishment transmit controller monitors the link establishment level of the automatic link establishment receive controller via the link establishment signal line. For example, when the automatic link establishment transmit controller detects a low level on the link establishment signal line, it initiates automatic link establishment. The automatic link establishment transmit controller notifies the transmit mode control module, which then controls the parallel-to-serial conversion module to send training data to the receiving end. The serial-to-parallel conversion module at the receiving end determines the data bit boundaries using the training data. After determining the data bit boundaries, the automatic link establishment receive controller sends a link establishment completion signal to the transmitting end, i.e., the link establishment signal line goes high. The transmit controller is the control center of the transmitting end, primarily controlling whether the transmit mode control module should send training data or other user data based on the signal on the link establishment signal line. It also needs to control the control terminal of the mux circuit (data selector circuit) in the transmit data processing module.

[0073] The automatic link establishment receiver controller controls the corresponding modules at the receiving end according to the control of the automatic link establishment transmitter controller. For example, the automatic link establishment receiver controller needs to control the receive mode processing module, receive the CRC check result, and control the MUX end of the receive data processing module, which is the control center of the receiving end.

[0074] In one embodiment, a CRC verification module is provided between the data transmission processing module and the transmission mode control module, and a CRC de-verification module is provided between the receiving mode processing module and the CRC de-verification module.

[0075] CRC check mode is used to verify the transmitted data and generate check bits.

[0076] The CRC verification module is used to verify the received data and check bits to obtain the corresponding verification result.

[0077] The present invention provides a data transmission method for a hardware emulator data transmission system based on the above-mentioned technical solution, comprising:

[0078] After the sending end and the receiving end establish a link, the sending end and the receiving end generate corresponding circuits according to the data bit width of each batch sent by the first simulation chip, and transmit the signal of the first simulation chip to the corresponding receiving port of the second simulation chip.

[0079] In a preferred embodiment, when a verification error occurs in the signal sent by the first simulation chip, the sending end disconnects from the receiving end and prepares for the next connection establishment.

[0080] The data transmission method of the present invention also includes a chain establishment process, the steps of which are as follows.

[0081] When the sending end detects that a connection has not been established with the receiving end, it sends training data to the receiving end;

[0082] The receiving end determines the data bit boundaries using the training data and sends a link establishment completion signal to the sending end.

[0083] In one embodiment, the receiver determines the data bit boundaries using training data, including:

[0084] The receive mode processing module performs cyclic shifting on the received data, and the state of each cyclic shift is controlled by a counter;

[0085] When the receiving mode processing module determines that the received data matches the training data, it keeps the counter unchanged, and the receiving controller outputs a training completion status signal to the transmitting controller, thus successfully establishing a link between the transmitting controller and the receiving controller.

[0086] In one specific embodiment, when the output of the receiver controller through the link establishment signal line changes from low level to high level, it indicates that the receiver controller outputs a training completion status signal.

[0087] The following is combined with Figure 2 It describes the detailed data processing process at the sending and receiving ends, specifically including the following steps.

[0088] S201. The sending end sends training data to the receiving end;

[0089] S202, The receiving end determines the data bit boundaries using training data.

[0090] S203. The receiving end sends a link establishment completion signal to the sending end;

[0091] S204. The transmitting end sends preamble data to the receiving end; the purpose of the preamble data is to synchronize the clock of the destination receiving end with the clock of the transmitting end, and the preamble is used to indicate the start of a frame. Therefore, a preamble is needed to distinguish each frame.

[0092] S205. The sending and receiving ends perform TDM processing on the data and transmit it until an error occurs in the CRC check. After that, the above steps are repeated.

[0093] In one embodiment, the process of the sending end sending training data to the receiving end includes the following steps.

[0094] S206. The automatic link establishment sending controller determines that the link establishment completion signal is low level;

[0095] S207. The automatic link establishment and transmission controller controls the transmission mode control module to send training data. In one embodiment, the conversion factor of the parallel-to-serial conversion module and the serial-to-parallel conversion module is 10, that is, the parallel-to-serial conversion module processes 10 bits of data to the LVDS link each time, and the serial-to-parallel conversion module recovers 10 bits of data from the LVDS link each time. The training data can be selected as the binary number 0101011010. The training data is not limited to any specific value listed in this invention, but it must be guaranteed to be asymmetric, and the data with a balanced number of 1s and 0s should be selected as much as possible, which is beneficial for the receiving end to determine the appropriate sampling point.

[0096] The above-mentioned receiving end determines the data bit boundaries through training data, including the following steps.

[0097] S208. The receive mode processing module cyclically shifts the received data, and the state of each cyclic shift is controlled by a counter. In one embodiment, the specific RTL circuit of the receive mode processing module can be as follows: Figure 3 As shown, S301 is a serial-to-parallel conversion module, S302 is a register, and S303 is a MUX circuit (data selector). The data d output by the serial-to-parallel conversion module S301 is assumed to have 10 bits, where d[9:0] represents bits 0 to 9 of data d. Delaying data d by one register value yields d_ff[9:0]. slip_cnt represents the counter, which counts cyclically according to the bit width of data d. When the counter is 0, the output data is d_slip[9:0]; when the counter is 1 to 9, n = 1 to 9, meaning the output data d_slip[9:0] is the concatenation of d_ff[n-1:0] and d[9:0], represented as {d_ff[n-1:0], d[9:n]}.

[0098] S209. When the receiving mode processing module determines that the received data matches the training data, it keeps the counter unchanged and outputs a training completion status signal to the automatic connection establishment receiving controller. At this time, the training completion status signal changes from low level to high level. Specifically, it determines... Figure 3 The data d_slip[9:0] shown is incremented. When the data d_slip[9:0] matches the training data, the slip_cnt remains unchanged, and the training completion status signal is changed to a high level.

[0099] The process of the receiving end sending a link establishment completion signal to the sending end includes the following steps.

[0100] S210, The automatic link establishment receiver controller determines the training completion status signal as high level;

[0101] S211. The automatic link establishment receiver controller sends a link establishment completion signal to the automatic link establishment sender controller. At this time, the link establishment completion signal changes from low level to high level.

[0102] The process of sending preamble data from the sending end to the receiving end includes the following steps.

[0103] S212, The automatic link establishment and transmission controller controls the transmission mode controller module to send the preamble data. The preamble data can be set to any data that is not equal to the training data, for example, it can be set to 1010100101, which is not equal to the training data.

[0104] S213. The preamble data, after passing through the parallel-to-serial conversion module, the LVDS link, and the serial-to-parallel conversion module, is received by the receive mode processing module. The specific parallel-to-serial and serial-to-parallel conversion modules can be implemented by the PHY layer IP of each manufacturer's chip; it only needs to ensure the mutual conversion between serial and parallel data. The LVDS link uses the standard LVDS level for end-to-end communication.

[0105] S214. The receiving mode processing module determines whether the received data matches the preamble data and outputs the preamble matching signal to the automatic connection receiving controller. At this time, the preamble matching signal changes from low level to high level.

[0106] S215, The automatic link establishment receiver controller determines that the preamble matching signal is high.

[0107] The aforementioned sending and receiving ends transmit data using TDM processing until a CRC check error occurs, at which point the process is restarted. This includes the following steps.

[0108] S216. Calculate the TDM data processing counter bit width at the transmitting and receiving ends based on the required data signal bit width. Assuming the required data signal bit width is W, and the conversion factor of the parallel-to-serial conversion module and the serial-to-parallel conversion module is P, then the TDM data processing counter bit width C at the transmitting and receiving ends can be calculated during the pre-compilation phase of the synthesis process without consuming logic circuit resources.

[0109] S217. The automatic link establishment and transmission controller resets the TDM data processing counter of the transmission data TDM processing module and de-resets it after transmitting the preamble data.

[0110] S218. The transmitted data sequentially passes through the TDM processing module, CRC check module, transmission mode controller module, and parallel-to-serial conversion module before finally being sent to the LVDS link.

[0111] S219. The data from the LVDS link undergoes TDM inverse processing through the serial-to-parallel conversion module, the receive mode processing module, the CRC de-verification module, and the receive data TDM processing module, and is finally output as the received data.

[0112] The polynomial used in the CRC check module and decheck module described above is determined by the number of bits used for the check, offering considerable flexibility. For example, in this embodiment, the number of bits used for the check is 2, and the selected polynomial is x. 2 +x 1 +1.

[0113] S220: The automatic connection establishment receiver controller resets the TDM data processing counter of the received data TDM processing module and de-resets it upon receiving preamble data to ensure synchronization of the TDM data processing counters at the transmitting and receiving ends.

[0114] S221. If the CRC de-verification module finds an error during data verification, it will output a CRC error status signal to the automatic connection receiver controller.

[0115] S222. After receiving the CRC error status signal, the automatic link establishment receiver controller resets the receiver mode processing module, causing the preamble matching signal and the training completion status signal to go low, and at the same time, the link establishment completion signal to go low.

[0116] S223. After receiving the low link establishment completion signal, the automatic link establishment and transmission controller resets the transmission mode control module to send training data, that is, it returns to the step S201 of sending training data from the transmitting end to the receiving end, and repeats the above steps in sequence.

[0117] In one embodiment, the data transmission TDM processing module is implemented using a MUX circuit. For example... Figure 4As shown, assuming the signal width of the transmitted data is R (R is greater than the data signal width W to be transmitted and is divisible by 8), and each output is an 8-bit data signal, then R / 8 MUX circuits S401 are required. The control terminals of multiple MUX circuits are all the values ​​of the TDM data processing counter mux_cnt. Each value of the counter mux_cnt represents a state. The R / 8 states of the counter correspond to the R / 8 groups of 8-bit data transmitted. In step S205, the data TDM processing is in the de-reset state, and mux_cnt changes from 0 to (R / 8-1).

[0118] The TDM inverse processing of the received data TDM processing module is implemented using a DMUX circuit. For example... Figure 5 As shown, in one embodiment, the circuit principle is... Figure 4 The reverse process is as follows: assuming the signal width of the received data is 8 bits, and the signal width of the data to be recovered is R bits, then R / 8 DMUX circuits S501 are needed. The control terminals of multiple DMUX circuits are all the values ​​of the TDM data processing counter mux_cnt. Each value of the counter mux_cnt represents a state. The R / 8 states of the counter correspond to the R / 8 groups of 8 bits of data transmitted. In step S205, the data TDM processing is in the de-reset state, and mux_cnt changes from 0 to (R / 8-1).

[0119] like Figure 6 As shown, in one embodiment, the CRC verification module of the present invention adopts a CRC parallel structure circuit composed of multiple XOR gates. In this embodiment, the input data bit width of the CRC verification module is 8, and the output verification data bit width is 2. In the figure, D0 to D7 are the input 8-bit data, CRC_TX_D8[0] and CRC_TX_D8[1] are the output verification data, and the bit width of CRC_TX_D8 is 2.

[0120] like Figure 7 As shown, in one embodiment, the CRC verification module of the present invention uses a CRC parallel structure circuit composed of multiple XOR gates. In this embodiment, the input is 8 bits of data and 2 bits of check data, and the output is a 2-bit check result. If both bits of the check result are 0, it indicates that the data verification is correct; otherwise, the data verification is incorrect. Figure 7 In the S102, D0 to D7 represent the 8-bit input data, and CRC_IN0 and CRC_IN1 represent the 2-bit check data, which are CRC_TX_D8[0] and CRC_TX_D8[1] in S102.

[0121] The verification results are CRC_RX_D8[0] and CRC_RX_D8[1]. If both verification results are 0, it means that the data verification is correct; otherwise, the data verification is incorrect.

[0122] like Figure 8 As shown, in one embodiment, the transmission mode control module of the present invention consists of two registers and a multiplexer. The three input ports of the multiplexer receive the data, preamble data, and training data transmitted to the transmitter by the first module, respectively. The port slip_en[1:0] is the control terminal with a bit width of 2, controlled by the automatic link establishment transmission controller S105. The input data DATA_IN[9:0] is 10 bits, and the output data is DATA_OUT[9:0]. When slip_en[1:0] is 0, the output data DATA_OUT[9:0] is the training data, for example... Figure 8 The example shown is 10'h15a; when slip_en[1:0] is 1, the output data DATA_OUT[9:0] is the preamble data, for example... Figure 8 As shown in 10'h2a5; when slip_en[1:0] is 2, the output data DATA_OUT[9:0] is the data transmitted from the first module to the sending end, for example, the input data is DATA_IN[9:0].

[0123] like Figure 9 As shown, in one embodiment, the automatic link establishment and transmission controller S105 of the present invention is implemented using a state machine, where train_done refers to the training completion state signal. The states are described below:

[0124] TRAIN: Indicates the training state. When train_done is 1, it transitions to the next state, at which point slip_en[1:0] is controlled to be 0 to send the training code. If train_done is 0, it remains in the training state. train_done indicates the training completion signal. In one embodiment, the training completion signal is indicated by the automatic connection receiver controller sending a high level.

[0125] SEND_PRE: Indicates the preamble state. This state lasts for one clock cycle and then jumps unconditionally. At this time, control slip_en[1:0] to be 1 to send a preamble for one clock cycle.

[0126] SEND_DATA: Indicates the data transmission status. If train_done is 0, it jumps to the TRAIN state; otherwise, it remains in the data transmission state. At this time, the automatic link establishment and transmission controller S105 controls slip_en[1:0] to be 2 to transmit data.

[0127] like Figure 10As shown, in one embodiment, the automatic link establishment receiver controller S110 is also implemented using a state machine.

[0128] IDLE indicates an idle state, in which the training completion status signal is set to 0.

[0129] SLIP indicates the bit sliding state. In this state, the slip_cnt of the MUX circuit S303 of the receive mode processing module S107 is controlled to slide bit until the received data matches the training data, and then it enters the next state.

[0130] RCV_PRE indicates the preamble reception state. If the received data is the preamble 10'h2a5, the system jumps to the next state. If the preamble duration exceeds 1 second in this state, the system exits and returns to the IDLE state. This timeout handling ensures that the system will not crash under certain circumstances. time_out represents the timeout signal, implemented by a counter circuit. In this state, the training completion status signal is set to 1.

[0131] RCV_DATA indicates the data reception status. In this state, useful data is normally received and output to S108. If a CRC check error occurs, the system jumps back to the IDLE state. crc_err is the CRC check error indicator signal, and its specific implementation is as follows... Figure 11 As shown.

[0132] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A data transmission system for a hardware emulator, characterized in that, include: The transmitting and receiving ends are connected via a low-voltage differential signal link and a link establishment signal line; The transmitting end includes: a transmitting controller and a transmitting data processing module; The receiving end includes: a receiving controller and a receiving data processing module; The transmitting data processing module includes multiple MUX circuits and a TDM data processing counter for the transmitting data processing module; the receiving data processing module includes multiple DMUX circuits and a TDM data processing counter for the receiving data processing module. Each input of the data selector of the transmitting data processing module is driven by the corresponding TDM data processing counter, and the output of the data selector of the receiving data processing module is driven by the corresponding TDM data processing counter. The data transmission processing module and the data reception processing module automatically select the corresponding number of MUX circuits and DMUX circuits to form the corresponding circuit based on the number of signals to be transmitted by the first simulation chip and the number of signals transmitted in each batch. The control terminals of multiple MUX circuits are all the value of the TDM data processing counter of the transmitting data processing module, mux_cnt. The control terminals of multiple DMUX circuits are all the value of the TDM data processing counter of the receiving data processing module, mux_cnt. Each value of the TDM data processing counter, mux_cnt, represents a state. The multiple states of the value of the TDM data processing counter, mux_cnt, correspond to the multiple sets of data after the signal to be transmitted is divided. After the transmitting controller and receiving controller obtain the link establishment success signal through the link establishment signal line, they control the transmitting data processing module and the receiving data processing module to transmit synchronously by setting the TDM data processing counters of the transmitting data processing module and the receiving data processing module to the same value. This allows the signal to be transmitted from the first emulation chip connected to the transmitting end to be divided into at least one batch and transmitted via the transmitting data processing module. Each batch of transmitted signal is accurately transmitted to the receiving port corresponding to the second emulation chip connected to the receiving end by the receiving data processing module through the low voltage differential signal link.

2. The data transmission system of the hardware emulator as described in claim 1, characterized in that, When the data selector is an 8:1 data selector, the number of data selectors in the transmitting data processing module or the receiving data processing module is R / 8, where R is the number of signals to be transmitted by the first simulation chip.

3. The data transmission system of the hardware emulator as described in claim 1 or 2, characterized in that, The transmitting end is connected to the LVDS link through a parallel-to-serial conversion module, and the receiving end is connected to the LVDS link through a serial-to-parallel conversion module.

4. The data transmission system of the hardware emulator as described in claim 1 or 2, characterized in that, The output of the transmitting data processing module is connected to the transmitting mode control module controlled by the transmitting controller; the input of the receiving data processing module is connected to the receiving mode processing module controlled by the receiving controller.

5. The data transmission system of the hardware emulator as described in claim 4, characterized in that, The transmitting controller and / or the receiving controller are implemented using a state machine.

6. The data transmission system of the hardware emulator as described in claim 5, characterized in that, The transmitting controller has at least one of the following states: training state, preamble state, and signal transmission state; the receiving controller has at least one of the following states: idle state, bit sliding state, preamble receiving state, and signal receiving state.

7. The data transmission system of the hardware emulator as described in claim 6, characterized in that, When the transmitting controller detects that the receiving controller is in an idle state via the link establishment signal line, it enters the training state. Simultaneously, it notifies the transmitting mode control module to send training data to the LVDS link and notifies the receiving controller to control the receiving mode processing module to enter the bit sliding state. The receiving mode processing module performs bit sliding on the data transmitted from the LVDS link until the received data matches the training data. The receiving controller then informs the transmitting controller that the link establishment is successful, and the transmitting controller and the receiving controller each enter the next state.

8. The data transmission system of the hardware emulator as described in claim 6, characterized in that, The transmission mode control module receives the control signal from the transmission controller through the data selector and selects the input data of the input port corresponding to the data selector according to the control signal.

9. The data transmission system of the hardware emulator as described in claim 6, characterized in that, The receiving mode processing module receives the control signal from the receiving controller through the data selector to perform bit sliding control for receiving data.

10. The data transmission system of the hardware emulator as described in claim 4, characterized in that, A verification module is provided between the data transmission processing module and the data transmission mode control module, and a deverification module is provided between the data reception mode processing module and the data reception processing module.

11. A data transmission method for a data transmission system of a hardware emulator as described in any one of claims 1 to 10, characterized in that, include: After the sending end establishes a connection with the receiving end, it sends preamble data to the receiving end. The transmitting end and the receiving end generate corresponding circuits based on the data bit width of each batch sent by the first simulation chip, and transmit the signal of the first simulation chip to the corresponding receiving port of the second simulation chip.

12. The data transmission method as described in claim 11, characterized in that, When a verification error occurs in the signal sent by the first simulation chip, the sending end disconnects from the receiving end and prepares for the next connection establishment.

13. The data transmission method as described in claim 11, characterized in that, Also includes: When the sending end detects that a connection has not been established with the receiving end, it sends training data to the receiving end; The receiving end determines the data bit boundary through training data and sends a link establishment completion signal to the sending end.

14. The data transmission method as described in claim 13, characterized in that, The receiving end determines the data bit boundaries using training data, including: The receive mode processing module performs cyclic shifting on the received data, and the state of each cyclic shift is controlled by a counter; When the receiving mode processing module determines that the received data matches the training data, it keeps the counter unchanged, and the receiving controller outputs a training completion status signal to the transmitting controller, indicating that the transmitting controller and the receiving controller have successfully established a link.

15. The data transmission method as described in claim 14, characterized in that, When the output of the receiver controller via the link establishment signal line changes from low level to high level, it indicates that the receiver controller outputs a training completion status signal.

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