Method for designing read-write mechanism for continuous multi-bit error correction code memory

Abstract

The application relates to a read-write mechanism design method for a continuous multi-bit error correction code memory. The method comprises the following steps: when the multi-bit error correction code memory is read, the read data is decoded by a decoder to determine whether an error occurs, the data is directly output if no error occurs, and the data in the multi-bit error correction code memory is re-read to perform error positioning and error correction if an error occurs; in the process of writing, an encoder is designed in a data interleaving arrangement calculation mode to perform encoding operation on the data to be written, the data is written into the multi-bit error correction code memory for storage, and a vertical check code is updated at the same time; the read data before the writing operation and the writing are converted into one operation, the read operation of the data is completed at the rising edge of a clock, and the data is written into a storage unit of the multi-bit error correction code memory at the falling edge of the clock after calculation. The method can improve the read-write accuracy of the multi-bit error correction code memory.

Description

Technical Field

[0001] This application relates to the field of static random access memory technology, and in particular to a design method for a read / write mechanism for a continuous multi-bit error-correcting code memory, a computer device, and a computer medium. Background Technology

[0002] Static Random-Access Memory (SRAM) is widely used as a high-speed cache due to its high read / write speed and low power consumption, and occupies an important position in multi-core microprocessors. With 40nm or deeper process technologies, on-chip SRAM capacity can reach tens of megabits. However, large-capacity SRAM is a vulnerable area susceptible to radiation. When high-energy particles bombard the memory circuit, the charge deposited on its trajectory is collected by sensitive nodes, causing the circuit's logic state to flip. Therefore, hardening the memory is the first problem that must be solved to ensure the chip's soft error rate.

[0003] However, existing error-correcting code memories are mainly designed for correcting single-bit errors, and their read / write mechanisms require one clock cycle for each operation. For correcting multiple-bit errors, BCH codes are typically used, which incurs significant timing and area overhead. Therefore, a method to improve memory read / write efficiency is needed. Summary of the Invention

[0004] Therefore, it is necessary to provide a design method for a read / write mechanism of a continuous multi-bit error-correcting code memory, a computer device, and a computer medium that can improve the read / write efficiency of the memory and address the above-mentioned technical problems.

[0005] A method for designing a read / write mechanism for a continuous multi-bit error-correcting code memory, the method comprising:

[0006] Construct a multi-bit error correction code memory; the multi-bit error correction code memory includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder;

[0007] When reading from the multi-bit error correction code memory, the read data is decoded by the decoder to determine whether there is an error. If there is no error, the data is output directly. If an error occurs, the data in the multi-bit error correction code memory is reread to locate and correct the error.

[0008] During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in an interleaved arrangement and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical check code.

[0009] The read and write operations are combined into a single clock cycle. The read operation is completed on the rising edge of the clock, and after calculation, the data is written to the storage unit of the multi-bit error correction code memory on the falling edge of the clock.

[0010] In one embodiment, during a read operation on the multi-bit error correction code memory, the read data is decoded by a decoder to determine if there is an error. If there is no error, the data is directly output; if an error occurs, the data in the multi-bit error correction code memory is reread for error location and correction, including:

[0011] The address signal, after being decoded, sends a read request to the multi-bit error correction code memory at the same time it arrives at the multi-bit error correction code memory.

[0012] The data at the address corresponding to the address signal is read using a multi-bit error correction code memory, and the horizontal parity check code is read out. Based on the calculation unit of the horizontal parity check code and the error correction code, the data stored in the multi-bit error correction code memory is subjected to error detection operation.

[0013] In one embodiment, the parity check result is used to determine whether the read data has an error. If no error has occurred, the data is output directly; if an error has occurred, error correction is initiated.

[0014] After an error is detected, all data in the storage array and the vertical parity check code are read from the multi-bit error correction code memory.

[0015] The stored data is calculated one by one with the vertical parity check code to obtain the error bits;

[0016] Calculate the distance to where the error occurred based on the error bits, and then perform a read operation on the multi-bit error correction code memory based on the calculation result.

[0017] In one embodiment, the distance to where the error occurred is calculated based on the error bits, and a read operation of the multi-bit error correction code memory is performed based on the calculation result, including:

[0018] The distance to the error is calculated based on the error bits. If the distance to the error is greater than the interleaving number of the multi-bit error correction code memory during a write operation, it exceeds the error correction capability and the stored data is retransmitted.

[0019] If the distance to the error is less than the interleaving number of the multi-bit error-correcting code memory during a write operation, the error is located and the erroneous data is flipped to obtain the correct data, which is then output to complete the read operation of the multi-bit error-correcting code memory.

[0020] In one embodiment, during the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in a data interleaving and calculation manner before writing it into the multi-bit error correction code memory for storage, and simultaneously updates the vertical check code, including:

[0021] During the write operation of the multi-bit error correction code memory, the encoder arranges the data, encodes it using an interleaving method, and then writes it into the multi-bit error correction code memory for storage. Where n bits of errors are corrected, the number of interleaving is n.

[0022] In one embodiment, the address signal is decoded and a write request is sent to the multi-bit error correction code memory at the same time it arrives at the multi-bit error correction code memory.

[0023] The original data corresponding to the address signal is read using a multi-bit error correction code memory, and the vertical parity check code is read out.

[0024] The vertical parity check code is compared and calculated with the data to be written. If the data to be written is consistent with the original data, the vertical parity check code is not returned. If the data to be written is inconsistent with the original data, the vertical parity check code is modified. At the same time, the data to be written is encoded with the horizontal error correction code.

[0025] The vertical parity check code is updated and written back, and the encoded data is written into the storage array of the multi-bit error correction code memory, thus completing a write operation of the multi-bit error correction code memory.

[0026] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program performing the following steps:

[0027] Construct a multi-bit error correction code memory; the multi-bit error correction code memory includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder;

[0028] When reading from the multi-bit error correction code memory, the read data is decoded by the decoder to determine whether there is an error. If there is no error, the data is output directly. If an error occurs, the data in the multi-bit error correction code memory is reread to locate and correct the error.

[0029] During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in a data interleaving and calculation manner and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical check code.

[0030] The read and write operations are combined into a single clock cycle. The read operation is completed on the rising edge of the clock, and after calculation, the data is written to the storage unit of the multi-bit error correction code memory on the falling edge of the clock.

[0031] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0032] Construct a multi-bit error correction code memory; the multi-bit error correction code memory includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder;

[0033] When reading from the multi-bit error correction code memory, the read data is decoded by the decoder to determine whether there is an error. If there is no error, the data is output directly. If an error occurs, the data in the multi-bit error correction code memory is reread to locate and correct the error.

[0034] During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in an interleaved arrangement and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical check code.

[0035] The read and write operations are combined into a single clock cycle. The read operation is completed on the rising edge of the clock, and after calculation, the data is written to the storage unit of the multi-bit error correction code memory on the falling edge of the clock.

[0036] The aforementioned design method, computer device, and storage medium for the read / write mechanism of a continuous multi-bit error-correcting code memory first constructs a multi-bit error-correcting code memory. This memory includes a storage array, a horizontal error-correcting code array, a vertical error-correcting code array, an encoder, and a decoder. During a read operation on the multi-bit error-correcting code memory, the read data is decoded by the decoder to determine if there is an error. If no error is found, the data is directly output. If an error occurs, the data in the multi-bit error-correcting code memory is reread for error location and correction. The two-dimensional error-correcting code's multi-bit error correction avoids the time spent on read operations when no error occurs, significantly reducing time and area overhead during read operations and improving read efficiency. During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in an interleaved arrangement calculation method and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical parity code. This application first adds a vertical parity code and then changes the write operation to "read first, write later". The vertical parity update logic can be pipelined and decoupled from the critical path of SRAM access, so it has no direct impact on performance. Since the data addresses of the write operation and the read operation are the same, there is no need to extract the address information again. The data reading operation can be completed on the rising edge of the clock. After calculation, the data is written into the storage cell of SRAM on the falling edge of the clock, so that the entire write process is completed within one clock cycle, which can significantly improve the read and write efficiency. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating a design method for a read / write mechanism of a continuous multi-bit error-correcting code memory in one embodiment.

[0038] Figure 2 This is a schematic diagram illustrating the use of a two-dimensional error-correcting code algorithm to encode data in one embodiment;

[0039] Figure 3 This is a schematic diagram of the architecture of a multi-bit error correction code memory in one embodiment;

[0040] Figure 4 This is a flowchart illustrating a read operation of a multi-bit error-correcting code memory in one embodiment.

[0041] Figure 5 This is a flowchart illustrating a write operation to a multi-bit error-correcting code memory in one embodiment.

[0042] Figure 6 This is a timing waveform diagram of an SRAM write operation process in one embodiment;

[0043] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] In one embodiment, such as Figure 1 As shown, a method for designing a read / write mechanism for a continuous multi-bit error-correcting code memory is provided, including the following steps:

[0046] Step 102: Construct a multi-bit error correction code memory; the multi-bit error correction code memory includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder.

[0047] like Figure 3 The diagram shows the overall structure of a Multi-bit Error-Correcting RAM (SRAM). The primary function of SRAM is data storage. Its main components include a storage array, a horizontal error-correcting code array, a vertical error-correcting code array, an encoder, and a decoder. The main workflow is as follows: the address signal is input to the address decoder for decoding, followed by read and write operations on the data at the corresponding address. The storage array is the most crucial component of the SRAM, and the horizontal error-correcting code array is incorporated to detect errors in the data within the storage array, thus providing protection. Data is transmitted to the outside world via Column I / O.

[0048] Step 104: When performing a read operation in the multi-bit error correction code memory, the read data is decoded by the decoder to determine whether there is an error. If there is no error, the data is output directly. If an error occurs, the data in the multi-bit error correction code memory is reread for error location and correction.

[0049] Traditional BCH codes require numerous clock cycles to decode during read operations, resulting in significant time consumption. This application employs a two-dimensional error-correcting code algorithm. While parity-check coding is the simplest and least hardware-intensive coding scheme, it can only detect errors, not correct them. Therefore, the data bits are reorganized, and multiple parity checks are performed. Each check identifies a different, overlapping error location. When the overlapping area shrinks to a single error bit, the error is located. The two-dimensional error-correcting code's ability to correct multiple errors avoids the time spent on read operations when no errors are found. The decoder for the two-dimensional error-correcting code is also much simpler than that of BCH codes, thus greatly reducing time and area overhead during read operations and improving efficiency. This application uses two-dimensional parity-check coding, with the data bits in the SRAM forming a two-dimensional matrix. Parity checks are performed in both the vertical and horizontal directions, and errors are located through cross-intersection. Because only parity-check coding is used, the hardware overhead is low for the same error correction capability, resulting in a high cost-effectiveness ratio for SRAM.

[0050] Step 106: During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in a data interleaving and calculation manner and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical check code.

[0051] like Figure 2As shown, an n-way alternating scheme is adopted in the horizontal and vertical directions. The encoder is designed to encode the data to be written in an interleaved data arrangement to achieve the purpose of correcting n-bit errors. Since the parity check code has low overhead, the timing, area, and power consumption overhead of ECC are reduced while ensuring multi-bit error correction capability. Compared with the traditional write operation, firstly, a vertical parity code is added, and then the write operation is changed to "read first, write later". The vertical parity update logic can be pipelined and decoupled from the critical path of SRAM access, so it has no direct impact on performance. Since the data address of the write operation and the read operation are consistent, there is no need to extract the address information again. As long as the vertical parity update rate matches the data access rate of SRAM, the vertical parity update will not affect the access time or cycle time of SRAM subarray. Updating the vertical parity row, which is similar to a register, is faster than accessing the main array, so the rate can be easily matched in practice. This application can complete the data read operation on the rising edge of the clock and write the data into the SRAM storage cell on the falling edge of the clock after calculation, so that the entire write process is completed within one clock cycle, which can significantly improve the read and write efficiency.

[0052] Step 108: Convert the read data and write data before the write operation into a single clock cycle. The data read operation is completed on the rising edge of the clock, and after calculation, the data is written to the storage unit of the multi-bit error correction code memory on the falling edge of the clock.

[0053] When performing a write operation on SRAM, a read operation must be performed first. Conventional read and write operations each require one clock cycle. If a read operation is performed before a write operation, it takes two clock cycles, resulting in low SRAM write efficiency. This application, in its SRAM architecture, converts the read and write operations before the write operation into a single clock cycle. Since the data addresses for write and read operations are the same, there is no need to retrieve address information again. The data read operation is completed on the rising edge of the clock, and after calculation, the data is written to the SRAM storage cell on the falling edge of the clock. This allows the entire write process to be completed within one clock cycle, significantly improving the efficiency of memory data writing.

[0054] The above-described read / write mechanism design method for a continuous multi-bit error-correcting code memory first constructs a multi-bit error-correcting code memory. This memory includes a storage array, a horizontal error-correcting code array, a vertical error-correcting code array, an encoder, and a decoder. During a read operation, the read data is decoded by the decoder to determine if there is an error. If no error is found, the data is directly output. If an error occurs, the data in the multi-bit error-correcting code memory is reread for error location and correction. The two-dimensional error-correcting code's multi-bit error correction avoids the time spent on read operations when no error occurs, significantly reducing time and area overhead during read operations and improving read efficiency. During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in an interleaved arrangement calculation method and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical parity code. This application first adds a vertical parity code and then changes the write operation to "read first, write later". The vertical parity update logic can be pipelined and decoupled from the critical path of SRAM access, so it has no direct impact on performance. Since the data addresses of the write operation and the read operation are the same, there is no need to extract the address information again. The data reading operation can be completed on the rising edge of the clock. After calculation, the data is written into the storage cell of SRAM on the falling edge of the clock, so that the entire write process is completed within one clock cycle, which can significantly improve the read and write efficiency.

[0055] In one embodiment, during a read operation on the multi-bit error correction code memory, the read data is decoded by a decoder to determine if there is an error. If there is no error, the data is directly output; if an error occurs, the data in the multi-bit error correction code memory is reread for error location and correction, including:

[0056] The address signal, after being decoded, sends a read request to the multi-bit error correction code memory at the same time it arrives at the multi-bit error correction code memory.

[0057] The data at the address corresponding to the address signal is read using a multi-bit error correction code memory, and the horizontal parity check code is read out. Based on the calculation unit of the horizontal parity check code and the error correction code, the data stored in the multi-bit error correction code memory is subjected to error detection operation.

[0058] In one embodiment, the parity check result is used to determine whether the read data has an error. If no error has occurred, the data is output directly; if an error has occurred, error correction is initiated.

[0059] After an error is detected, all data in the storage array and the vertical parity check code are read from the multi-bit error correction code memory.

[0060] The stored data is calculated one by one with the vertical parity check code to obtain the error bits;

[0061] Calculate the distance to where the error occurred based on the error bits, and then perform a read operation on the multi-bit error correction code memory based on the calculation result.

[0062] In a specific embodiment, such as Figure 4 As shown, ① the address signal, after decoding, sends a read request to the SRAM simultaneously with its arrival; ② the SRAM reads the data at that address and retrieves the horizontal parity check code. The error correction code calculation unit then performs error detection on the data stored in the SRAM; ③ the parity check result determines whether the read data contains an error; ④ if no error occurs, the data is directly output; if an error occurs, error correction is initiated; ⑤ after detecting an error, all data in the storage array and the vertical parity check code are read from the SRAM; ⑥ the stored data is calculated one by one with the vertical parity check code to locate the error position, and the error bits are flipped to obtain the correct data; ⑦ after error correction, the correct data is output, and the SRAM completes one read operation. After the read operation is completed, the SRAM is refreshed in the background to eliminate the effects of accumulated errors.

[0063] In one embodiment, the distance to where the error occurred is calculated based on the error bits, and a read operation of the multi-bit error correction code memory is performed based on the calculation result, including:

[0064] The distance to the error is calculated based on the error bits. If the distance to the error is greater than the interleaving number of the multi-bit error correction code memory during a write operation, it exceeds the error correction capability and the stored data is retransmitted.

[0065] If the distance to the error is less than the interleaving number of the multi-bit error-correcting code memory during a write operation, the error is located and the erroneous data is flipped to obtain the correct data, which is then output to complete the read operation of the multi-bit error-correcting code memory.

[0066] In a specific embodiment, during a read operation, data decoding is required. This includes determining if erroneous data exists. If an error occurs, the entire SRAM storage data needs to be read. After calculation, the distance to the error is first determined. For example, in a four-bit error correction device, if the distance is greater than four, it exceeds the error correction capability, and the entire system will be reset. If the distance is less than four, the error is located and the erroneous data is flipped. After the read / write process is complete, the correct data will be updated and reset in the background.

[0067] In one embodiment, during the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in a data interleaving and calculation manner before writing it into the multi-bit error correction code memory for storage, and simultaneously updates the vertical check code, including:

[0068] During the write operation of the multi-bit error correction code memory, the encoder arranges the data, encodes it using an interleaving method, and then writes it into the multi-bit error correction code memory for storage. Where n bits of errors are corrected, the number of interleaving is n.

[0069] In a specific embodiment, such as Figure 6 The diagram shows the timing waveforms of an SRAM write operation. During the write operation, the encoder is designed to encode the data to be written using an interleaved data calculation method. For example, the encoding method of a two-dimensional error-correcting code that corrects one bit error is to perform an XOR operation on all the data in each row, such as h1 = W. 00 ^W 01 ^W 02 ^W 03 ^W 04 ^W 05 ^W 06 ^W 07 And so on. Encoders that correct multiple errors arrange the data using an interleaving method. For example, to correct two errors, the interleaving number is 2, and the error correction code is h1 = W. 00 ^W 02 ^W 04 ^W 06 h2 = W 01 ^W 03 ^W 05 ^W 07 If four errors are corrected, the interleaving number is 4, and the error correction codes are h1 = W. 00 ^W 04 h2 = W 01 ^W 05 h3 = W 02 ^W 06 h4 = W 03 ^W 07 And so on. The encoder writes the encoded data to SRAM for storage. The written data and the read stored data are then used to update the vertical error correction code array.

[0070] In one embodiment, the address signal is decoded and a write request is sent to the multi-bit error correction code memory at the same time it arrives at the multi-bit error correction code memory.

[0071] The original data corresponding to the address signal is read using a multi-bit error correction code memory, and the vertical parity check code is read out.

[0072] The vertical parity check code is compared and calculated with the data to be written. If the data to be written is consistent with the original data, the vertical parity check code is not returned. If the data to be written is inconsistent with the original data, the vertical parity check code is modified. At the same time, the data to be written is encoded with the horizontal error correction code.

[0073] The vertical parity check code is updated and written back, and the encoded data is written into the storage array of the multi-bit error correction code memory, thus completing a write operation of the multi-bit error correction code memory.

[0074] In a specific embodiment, the write process in the SRAM architecture of this application differs from the traditional SRAM write process in that a mechanism for updating the vertical checksum is added. The specific process is as follows: Figure 5 As shown, ① the address signal, after decoding, sends a write request to the SRAM upon arrival; ② at this time, the SRAM reads the original data at that address and retrieves the vertical parity check code, which is compared with the incoming data to be written. If the data to be written matches the original data, the vertical parity check code is not returned; if the data to be written does not match the original data, the vertical parity check code is modified. Simultaneously, the data to be written undergoes horizontal error correction code encoding; ③ the vertical parity check code is updated and written back, and the encoded data is written into the SRAM's storage array, completing one SRAM write operation.

[0075] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0076] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a read / write mechanism design method for a continuous multi-bit error-correcting code memory. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0077] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0078] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0079] In one embodiment, a computer storage medium is provided that stores a computer program, which, when executed by a processor, implements the steps of the method described above.

[0080] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for designing a read / write mechanism for a continuous multi-bit error-correcting code memory, characterized in that, The method includes: A multi-bit error correction code memory is constructed; the multi-bit error correction code memory includes a storage array, a horizontal error correction code array, a vertical error correction code array, an encoder, and a decoder; When reading from the multi-bit error correction code memory, the read data is decoded by the decoder to determine whether there is an error. If there is no error, the data is output directly. If an error occurs, the data in the multi-bit error correction code memory is reread to locate and correct the error. During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written in a data interleaving and calculation manner and then write it into the multi-bit error correction code memory for storage, while simultaneously updating the vertical check code; wherein, the update logic of the vertical check code is configured to be pipelined and deviate from the access critical path of the multi-bit error correction code memory. Taking advantage of the fact that the data addresses of write and read operations are the same and there is no need to extract the address information again, the data reading and writing before the write operation are converted into a single clock cycle. The data reading operation is completed on the rising edge of the clock, and after calculation, the data is written to the storage cell of the multi-bit error correction code memory on the falling edge of the clock.

2. The method according to claim 1, characterized in that, During a read operation from the multi-bit error correction code memory, the read data is decoded by the decoder to determine if there are any errors. If no errors are found, the data is output directly. If errors occur, the data in the multi-bit error correction code memory is reread for error location and correction, including: The address signal, after being decoded, sends a read request to the multi-bit error correction code memory at the same time it arrives at the multi-bit error correction code memory. The data at the address corresponding to the address signal is read using a multi-bit error correction code memory, and the horizontal parity check code is read out. Based on the calculation unit of the horizontal parity check code and the error correction code, the data stored in the multi-bit error correction code memory is subjected to error detection operation.

3. The method according to claim 2, characterized in that, The method further includes: The system checks the parity of the data to determine if any errors have occurred. If no errors have occurred, the data is output directly. If errors have occurred, error correction is initiated. After an error is detected, all data in the storage array and the vertical parity check code are read from the multi-bit error correction code memory. The stored data is calculated one by one with the vertical parity check code to obtain the error bits; The distance to the error is calculated based on the error bit, and a read operation is performed on the multi-bit error correction code memory based on the calculation result.

4. The method according to claim 3, characterized in that, Calculate the distance to the error based on the error bit, and perform a read operation on the multi-bit error correction code memory based on the calculation result, including: The distance to the error is calculated based on the error bit. If the distance to the error is greater than the interleaving number of the multi-bit error correction code memory during the write operation, it exceeds the error correction capability and the stored data is retransmitted. If the distance to the error is less than the interleaving number of the multi-bit error-correcting code memory during a write operation, the error is located and the erroneous data is flipped to obtain the correct data, which is then output to complete the read operation of the multi-bit error-correcting code memory.

5. The method according to claim 4, characterized in that, During the write operation of the multi-bit error correction code memory, the encoder is designed to encode the data to be written using a data interleaving and calculation method, and then write it to the multi-bit error correction code memory for storage. Simultaneously, the vertical check code is updated, including: During the write operation of the multi-bit error correction code memory, the encoder arranges the data, encodes it using an interleaving method, and then writes it into the multi-bit error correction code memory for storage. Where n bits of errors are corrected, the number of interleaving is n.

6. The method according to claim 5, characterized in that, The method further includes: The address signal is decoded and simultaneously sends a write request to the multi-bit error correction code memory upon arrival at the multi-bit error correction code memory. The original data corresponding to the address signal is read using a multi-bit error correction code memory, and the vertical parity check code is read out. The vertical parity check code is compared and calculated with the data to be written. If the data to be written is consistent with the original data, the vertical parity check code is not returned. If the data to be written is inconsistent with the original data, the vertical parity check code is modified. At the same time, the data to be written is encoded with a horizontal error correction code. The vertical parity check code is updated and written back, and the encoded data is written into the storage array of the multi-bit error correction code memory, thus completing a write operation of the multi-bit error correction code memory.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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