Method of forming a semiconductor device

Abstract

Photoresist and methods for its formation and use are disclosed. In an embodiment, one method includes spin-coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, depositing the photoresist layer using one or more organometallic precursors; heating the photoresist layer to induce crosslinking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to induce decrosslinking in the photoresist layer, forming decrosslinked portions of the photoresist layer; and removing the decrosslinked portions of the photoresist layer. Embodiments of the invention also relate to methods for forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on the material layers.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, which allows more components to be integrated in a given area. Summary of the Invention

[0004] Embodiments of the present invention provide a method for forming a semiconductor device, comprising: spin-coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, wherein one or more organometallic precursors are used to deposit the photoresist layer; heating the photoresist layer to induce cross-linking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to induce decross-linking in the photoresist layer, forming a decross-linked portion of the photoresist layer; and removing the decross-linked portion of the photoresist layer.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: reacting a first precursor with a first reactant to form a first compound, the first precursor comprising M(CH2COOX)4 or M(CH2COOR)4, wherein M represents a metal, X represents a halogen, and R represents an alkyl group; reacting a second precursor with the first reactant to form a second compound, the second precursor comprising M(CH=CH2)4 or M(CH(CH3)X)4; and crosslinking the first compound with the second compound to form a crosslinked compound.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a first hard mask layer over a target layer; and forming a crosslinked photoresist over the first hard mask layer, wherein forming the crosslinked photoresist comprises crosslinking a first organometallic compound with a second organometallic compound, wherein the first organometallic compound comprises M(CH2COOH)4 or M(N=C=O)4, and wherein the second organometallic compound comprises M(CH(CH3)OH)4 or M(CH(CH3)NH2)4, wherein M represents a metal and X represents a halogen. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 9 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments is shown. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the discussed embodiments and / or configurations.

[0010] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] Various embodiments provide improved photoresists, methods for forming such photoresists, and methods for patterning target layers using photoresists. The photoresist is a metal-organic photoresist, which can be a positive material. Improved photoresists can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. CVD or ALD deposition allows for photoresist deposition without the use of toxic organic solvents, making it a more environmentally friendly process. CVD and ALD are material-saving processes that reduce waste and cost. CVD or ALD deposition results in photoresist deposition with more uniform density and controllable film thickness, which improves lithography performance and pattern transfer, reduces device defects, and improves device performance. Metal-organic photoresists have good energy (such as light) absorption. This reduces the dosage required for patterning the photoresist, lowers costs, and increases yield. Compared to other semiconductor materials, metal-organic photoresists have good etch resistance. This improves the patterning of underlying layers, reduces device defects, and improves device performance.

[0012] Figures 1 to 9 A cross-sectional view is shown of an intermediate stage in forming components in a target layer 102 of a semiconductor device 101 according to some embodiments. The target layer 102 is the layer to be patterned. In some embodiments, the semiconductor device 101 may be treated as part of a larger wafer. In such embodiments, after forming the various components of the semiconductor device 101 (e.g., active devices, interconnect structures, etc.), a dicing process may be applied to the scribe area of ​​the wafer to separate the individual semiconductor dies from the wafer (also referred to as dicing).

[0013] Figure 1 A multilayer film stack 120 formed over a semiconductor substrate 100 is shown. The multilayer film stack 120 may include a target layer 102, a first dielectric layer 104, a first hard mask layer 106, and a second dielectric layer 108. The first dielectric layer 104, the first hard mask layer 106, and the second dielectric layer 108 may be optional layers and may be omitted in some embodiments. According to some embodiments, the first dielectric layer 104, the first hard mask layer 106, and the second dielectric layer 108 may be stacked in any desired order, may be replicated, or may be otherwise repeated.

[0014] Semiconductor substrate 100 may be formed from an active layer of a semiconductor material such as doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 100 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; combinations thereof, etc. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the active surface of semiconductor substrate 100. In some embodiments, target layer 102 may be a semiconductor substrate. For example, in some embodiments, target layer 102 may be a semiconductor substrate for forming fin field-effect transistors (FinFETs), nanostructure field-effect transistors (nanoFETs), etc. In such embodiments, semiconductor substrate 100 may be omitted.

[0015] The target layer 102 may be a layer to be patterned. In some embodiments, the target layer 102 may be a conductive layer, a dielectric layer, a semiconductor layer, etc. In embodiments where the target layer 102 is a conductive layer, the target layer 102 may be a metal layer, a polysilicon layer, etc. The target layer 102 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) (e.g., blanket deposition, etc.). The conductive layer may be patterned according to the processes described below to form metal gates (e.g., in a metal gate dicing process), wires, conductive vias, dummy gates (e.g., replacement gates for FinFETs, nanoFETs, etc.).

[0016] In embodiments where the target layer 102 is a dielectric layer, the target layer 102 may be an intermetallic dielectric layer, an interlayer dielectric layer, a passivation layer, etc. The target layer 102 may be a material with a low dielectric constant (e.g., a low-k material). For example, the target layer 102 may have a dielectric constant below 3.8, below 3.0, or below 2.5. The target layer 102 may also be a material with a high dielectric constant, such as a dielectric constant above 3.8. The target layer 102 may be deposited by CVD, atomic layer deposition (ALD), etc. One or more openings (such as opening 114, described below) may be patterned in the target layer 102 according to the process described below. Figure 6 (Discussion), and can form wires, conductive vias, etc. in the openings of the target layer 102.

[0017] In embodiments where the target layer 102 is a semiconductor material, the target layer 102 may be formed of silicon, silicon germanium, or the like. In some embodiments, the target layer 102 may be formed of a crystalline semiconductor material such as crystalline silicon, crystalline silicon carbide, crystalline silicon germanium, crystalline III-V compound, or the like. In some embodiments, openings (such as opening 114, as described below) may be patterned in the target layer 102 according to the process described below. Figure 6 (As discussed), shallow trench isolation (STI) regions can be formed in the openings in the target layer 102. Semiconductor fins can protrude from between adjacent STI regions, and source / drain regions can be formed in the semiconductor fins. The semiconductor fins can include the material remaining in the target layer 102 after the openings are formed in the target layer 102. A gate dielectric layer and a gate electrode can be formed over the channel regions in the semiconductor fins to form semiconductor devices such as FinFETs, nanoFETs, etc.

[0018] Although Figure 1 The target layer 102 is shown as being in physical contact with the semiconductor substrate 100, but any number of intermediate layers may be disposed between the target layer 102 and the semiconductor substrate 100. Such intermediate layers may include interlayer dielectric (ILD) layers, which may include low-k dielectrics and may include contact plugs formed therein; other intermetallic dielectric (IMD) layers having wires and / or vias formed therein; one or more intermediate layers (e.g., etch stop layers, adhesive layers, etc.); combinations thereof, etc. In some embodiments, the etch stop layer may be disposed directly below the target layer 102. The etch stop layer may be used as a subsequent etching process performed on the target layer 102 (e.g., hereinafter referred to as...). Figure 6 The etch stop layer is a stop element in the described etching process. The materials and processes used to form the etch stop layer may depend on the material of the target layer 102. In some embodiments, the etch stop layer may be made of silicon nitride, SiON, SiCON, SiC, SiOC, SiC x N y SiO x Other dielectrics, combinations thereof, etc., are formed. Etch stop layers can be deposited using CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), PVD, etc.

[0019] A first dielectric layer 104 is formed over the target layer 102. The first dielectric layer 104 may be an anti-reflective coating (ARC) that facilitates the exposure and focusing of the overlying photoresist layer (discussed below) during patterning. In some embodiments, the first dielectric layer 104 may be formed of SiON, silicon carbide, oxygen (O)-doped and / or nitrogen (N)-doped materials, etc. In some embodiments, the first dielectric layer 104 is substantially nitrogen-free and may be formed of oxides. In such embodiments, the first dielectric layer 104 may also be referred to as a nitrogen-free ARC (NFARC). In some embodiments, the material composition of the first dielectric layer 104 may be selected to prevent reflection. The first dielectric layer 104 may be deposited by PECVD, high-density plasma (HDP) deposition, etc.

[0020] A first hard mask layer 106 is formed over the first dielectric layer 104. The first hard mask layer 106 may be formed of materials including: metallic materials (e.g., titanium nitride, titanium, tantalum nitride, tantalum, metal-doped carbides (e.g., tungsten carbide), etc.); quasi-metallic materials (e.g., silicon nitride, boron nitride, silicon carbide, etc.); oxides (e.g., silicon dioxide (SiO2), oxides formed from tetraethyl orthosilicate (TEOS), etc.); silicon, etc. In some embodiments, the material composition of the first hard mask layer 106 may be determined to provide high etch selectivity with underlying layers, such as relative to the first dielectric layer 104 and / or the target layer 102. The first hard mask layer 106 may be deposited by CVD, PVD, ALD, etc. In subsequent processing steps, a pattern is formed on the first hard mask layer 106 using an embodiment patterning process. The first hard mask layer 106 is then used as an etch mask to etch the target layer 102, wherein the pattern of the first hard mask layer 106 is transferred to the target layer 102.

[0021] A second dielectric layer 108 is formed over the first hard mask layer 106. The second dielectric layer 108 can be formed of a silicon oxide material. For example, the second dielectric layer 108 can be an oxide formed of tetraethyl borophosphosilicate (BPTEOS), undoped TEOS, etc. The second dielectric layer 108 can be deposited by CVD, ALD, PEALD, spin coating, etc. Other processes and materials can be used. In some embodiments, the second dielectric layer 108 also serves as an anti-reflective coating. The first hard mask layer 106 and the second dielectric layer 108 can have different material compositions, allowing for selective etching of the first hard mask layer 106 and the second dielectric layer 108. Although Figure 1 The second dielectric layer 108 is shown as disposed above the first hard mask layer 106, but in some embodiments, the second dielectric layer 108 may be disposed below the first hard mask layer 106.

[0022] exist Figure 2In this configuration, a second hard mask layer 110 is formed over the multilayer film stack 120. The second hard mask layer 110 can be deposited by spin coating or the like, and subsequently baked. In some embodiments, the second hard mask layer 110 may include a spin-coated carbon (SOC) material, a bottom anti-reflective coating (BARC) material, etc. The second hard mask layer 110 may include an organic polymer with a high carbon content (e.g., the second hard mask layer 110 may have a carbon content from about 20 wt% to about 90 wt%). The second hard mask layer 110 can be used to augment multilayer photoresist structures (such as multilayer photoresist structure 122, hereinafter referred to as...). Figure 3 (Discussion) Selectivity with respect to the layers of the underlying multilayer stack 120. Including an organic polymer with a high carbon content in the second hard mask layer 110 can increase the etch selectivity of the second hard mask layer 110 relative to the layers of the underlying multilayer stack 120. The second hard mask layer 110 may also include a photosensitive compound (PAC), such as a photoacid generator (PAG), a photoalkali generator (PBG), etc. In some embodiments, the PAG may include iodide salts (such as tert-butylphenyl iodide perfluorooctane sulfonate (TBI-PFOS), etc.), sulfonium salts (such as triphenylsulfonium perfluorobutane sulfonate (TPS-PFBS), triphenylsulfonium trifluorosulfonate (TPS-TF), etc.), combinations thereof, etc. The photosensitive compound may be included in the second hard mask layer 110 to assist the subsequent deposition of photoresist layers (such as photoresist layer 112, discussed below) during the exposure of the photoresist layer to a patterned energy source. Figure 3 (Discussion) Decrosslinking. In some embodiments, the solvent used for depositing the second hard mask layer 110 may include an organic solvent, such as propylene glycol methyl ether acetate (PGMEA).

[0023] exist Figure 3In this configuration, a photoresist layer 112 is formed over a second hard mask layer 110. The combination of the photoresist layer 112 and the second hard mask layer 110 can be referred to as a multilayer photoresist structure 122. In some embodiments, the photoresist layer 112 may be formed of an organometallic compound. The photoresist layer 112 can be deposited by CVD, ALD, spin coating, etc. In embodiments where the photoresist layer 112 is deposited by CVD or ALD, deposition can be performed at a temperature of about 100°C to about 500°C and a pressure of about 5 mTorr to about 10 Torr at a plasma power of less than about 1000 W. The second photoresist layer 112 may be deposited from an organometallic precursor, which may be supplied in the gas phase. The organometallic precursor may be supplied at a flow rate of about 100 sccm to about 2000 sccm. In some embodiments, the organometallic precursor has the following general formula: M(CH2COOX)4, M(CH2COOR)4, M(CH=CH2)4, M(CH(CH3)X)4, or M(N=C=O)4. M represents a metal, which may include tin (Sn), bismuth (Bi), antimony (Sb), indium (In), tellurium (Te), etc. X represents a halogen, such as chlorine (Cl), bromine (Br), iodine (I), etc. R represents an alkyl group, which may be straight-chain or branched and may include 1 to 5 carbon atoms. Therefore, the organometallic precursor may include the following structures:

[0024]

[0025] In each of the above structures, only one functional group is fully shown. Each structure may include four of the functional groups shown, with three additional functional groups represented by the symbol -. The other functional groups represented by the symbol - are the same as those shown in each of the above structures and throughout this application. In a further embodiment, the organometallic precursor may have the general formula MxAaBb, where M represents one of the above-described metals, A and B represent any two of the above-described ligands (e.g., CH2COOX, CH2COOR, CH=CH2, CH(CH3)X, or N=C=O), x is in the range of 1 to 2, a and b are both greater than or equal to 1, and the sum of a and b is less than or equal to 6.

[0026] The organometallic precursor can be reacted with the co-reactant prior to polymerization to form the photoresist layer 112. In some embodiments, the co-reactant may include water vapor (H2O), ammonia (NH3), etc. For example, the organometallic precursor can react with the co-reactant according to the following reaction:

[0027]

[0028] In each of the above structures, only one functional group is shown to react with each co-reactant. However, any number of functional groups can react with the co-reactants.

[0029] An organometallic precursor is deposited on a second hard mask layer 110 and then subjected to post-deposition baking to induce cross-linking between the organometallic precursors and form a photoresist layer 112. Post-deposition baking can be performed at a temperature of about 70°C to about 150°C, at a pressure of about 100 Torr to about 1 atm (760 Torr), and for about 20 seconds to about 10 minutes. The organometallic precursor can include at least two of the above-described structures. For example, the organometallic precursor can include M(CH2COOH)4 and M(CH(CH3)OH)4; M(CH2COOH)4 and M(CH(CH3)NH2)4; M(N=C=O)4 and M(CH(CH3)OH)4; or M(N=C=O)4 and M(CH(CH3)NH2)4. Organometallic precursors can be crosslinked to form M(CH₂COOH)₃(CH₂COOCHCH₃)M(CH(CH₃)OH)₃, M(CH₂COOH)₃(CH₂C=ONHCHCH₃)M(CH(CH₃)NH₂)₃, or M(N=C=O)₃(NHCOOCHCH₃)M(CH(CH₃)OH)₃. Organometallic precursors can be crosslinked according to the following reactions:

[0030]

[0031] In each of the above structures, only one functional group of each organometallic precursor is shown to react with one functional group of another organometallic precursor to form a crosslinked photoresist molecule. However, any number of functional groups from organometallic precursors can be crosslinked to form crosslinked photoresist molecules.

[0032] The use of CVD, ALD, or similar methods to deposit the photoresist layer 112 results in a controllable film thickness for the photoresist layer 112. For example, the photoresist layer 112 can be deposited to a thickness ranging from about 4 nm to about 400 nm. The photoresist layer 112 can be deposited to have high film uniformity (including uniform film density) over a large area. The photoresist layer 112 forming the described metal-organic material allows the photoresist layer 112 to be used to pattern smaller parts, such as parts with a critical size of less than about 5 nm. As a result, the photoresist layer 112 can be used to form smaller devices with improved performance and reduced device defects. CVD and ALD are more efficient and environmentally friendly than other processes used for depositing photoresist, reducing costs, waste, and the use of harmful solvents.

[0033] In some embodiments, the photoresist layer 112 can be deposited at a gradient film density. The photoresist layer 112 can have a density ranging from about 2.0 g / cm³. 3 Approximately 3.5 g / cm³ 3The average film density is within a certain range. The ratio of the density of the photoresist layer 112 at the interface between the second hard mask layer 110 and the photoresist layer 112 to the density of the photoresist layer 112 on the top surface of the photoresist layer 112 opposite to the second hard mask layer 110 can be in the range of about 0.5 to about 2.0. Forming a photoresist layer 112 with a gradient film density can help reduce defect problems such as dross and bridging, and improve etching performance, such as reducing linewidth roughness (LWR) and line edge roughness (LER).

[0034] exist Figure 4 In this process, a photoresist layer 112 and an underlying second hard mask layer 110 are exposed to patterned energy 130, and a post-exposure bake (PEB) is performed to induce decrosslinking in the photoresist layer 112, forming a decrosslinked portion 112d. The photoresist layer 112 and the underlying second hard mask layer 110 are exposed to patterned energy 130 through an intermediate mask 132. In some embodiments, the patterned energy 130 may include patterned light, such as ultraviolet (UV) light, extreme ultraviolet (EUV) light, etc. Exposing photosensitive compounds (e.g., photoacid generators and photoalkali generators) present in the second hard mask layer 110 to the patterned energy 130 causes the generation of acid and base 134 in the second hard mask layer 110. The acid / base 134 is then transferred to the photoresist layer 112. The acid / base 134 can be used as a catalyst to induce decrosslinking in the portion of the photoresist layer 112 exposed to the patterned energy 130. In some embodiments, the acid / base 134 may include H... + and OH - ion.

[0035] Then, post-exposure baking is performed on the second hard mask layer 110 and the photoresist layer 112, which causes decrosslinking in the portions of the photoresist layer 112 exposed to the patterned energy 130 and forms decrosslinked portions 112d. An acid / base 134 transferred to the photoresist layer 112 catalyzes the decrosslinking in the exposed portions of the photoresist layer 112. The decrosslinking in the photoresist layer 112 can proceed according to the following reaction:

[0036]

[0037] In the above structure, only one crosslinking of the crosslinked photoresist molecule is shown to react with acid / base 134 and be decrosslinked. However, any number of crosslinking groups from the crosslinked photoresist molecules can be decrosslinked. Post-exposure baking can be performed under ambient conditions at temperatures greater than about 350°C.

[0038] exist Figure 5In this embodiment, the decrosslinked portion 112d of the photoresist layer 112 is removed, forming an opening 114 in the photoresist layer 112. In the illustrated embodiment, the photoresist layer 112 is a positive photoresist, allowing the decrosslinked portion 112d exposed to the patterning energy 130 to be removed. The decrosslinked portion 112d can be removed by exposing it to a developer. The aforementioned material used for the photoresist layer 112 exhibits good absorption of the patterning energy 130, such as EUV light, and good etch selectivity between the unexposed portion and the decrosslinked portion 112d of the photoresist layer 112. This improves the exposure and development of the photoresist layer 112, resulting in the formation of patterns with smaller critical dimensions, improved device performance, and reduced device defects. Furthermore, the photoresist layer 112 is a positive metal-organic photoresist formed through an efficient deposition process, which has the potential for use in many high-performance patterning processes.

[0039] exist Figure 6 In this process, an opening 114 extends through the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, the first dielectric layer 104, and the target layer 102. In one or more etching processes, the photoresist layer 112 can be used as a mask to pattern the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, the first dielectric layer 104, and the target layer 102. The etching process can be anisotropic, such that the opening 114 extending through the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, the first dielectric layer 104, and the target layer 102 has substantially the same size and shape as the opening 114 extending through the photoresist layer 112. The etching process can include wet etching, dry etching, combinations thereof, etc. The etching process can include processes such as reactive ion etching (RIE), neutral beam etching (NBE), etc. In some embodiments, other etching techniques can be used.

[0040] After the opening 114 extends through the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, the first dielectric layer 104, and the target layer 102, each of the photoresist layer 112, the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, and the first dielectric layer 104 is shown as existing above the target layer 102. However, as the opening 114 extends through the underlying layers, one or more of the photoresist layer 112, the second hard mask layer 110, the second dielectric layer 108, the first hard mask layer 106, and the first dielectric layer 104 can be consumed and / or removed.

[0041] exist Figure 7In the process, photoresist layer 112, second hard mask layer 110, second dielectric layer 108, first hard mask layer 106, and first dielectric layer 104 are removed. After the opening 114 extends through the target layer 102, photoresist layer 112, second hard mask layer 110, second dielectric layer 108, first hard mask layer 106, and first dielectric layer 104 can be removed. Photoresist layer 112, second hard mask layer 110, second dielectric layer 108, first hard mask layer 106, and first dielectric layer 104 can be removed by dry etching process, wet etching process, plasma ashing, chemical mechanical planarization (CMP) process, combination of them, or multiplexing.

[0042] Forming the photoresist layer 112 using the methods and materials described above offers several advantages. For example, forming the photoresist layer 112 via CVD, ALD, etc., allows for controllable film thickness, high film uniformity (including uniform film density), and large-area deposition. The photoresist layer 112 can be deposited without the use of toxic solvents, resulting in a more environmentally friendly process and higher material efficiency. The photoresist layer 112 can be an organometallic material, exhibiting good patterned energy absorption and good etch resistance. This allows the photoresist layer 112 to be used for reduced critical size etching. The methods and materials described above can be used to improve device performance, reduce device size, and decrease device defects.

[0043] Figure 8 An embodiment is shown in which a third hard mask layer 116 is formed over the photoresist layer 112 before the photoresist layer 112 is exposed to patterned energy 130. The third hard mask layer 116 can be deposited over the photoresist layer 112 after the photoresist layer 112 has undergone post-deposition baking. The third hard mask layer 116 can be formed from the same or similar materials and methods as the second hard mask layer 110. For example, the third hard mask layer 116 can be deposited by spin coating or the like and subsequently baked. In some embodiments, the third hard mask layer 116 may include a spin-coated carbon (SOC) material, a bottom anti-reflective coating (BARC) material, etc. The third hard mask layer 116 may include an organic polymer with a high carbon content (e.g., the third hard mask layer 116 may have a carbon content from about 20 wt% to about 80 wt%). The third hard mask layer 116 can be used to provide additional photosensitive compounds to aid in the decrosslinking of the photoresist layer 112. Therefore, the third hard mask layer 116 may include photosensitive compounds, such as photoacid generators, photoalkali generators, etc.

[0044] Furthermore, in Figure 8In this process, the third hard mask layer 116, the photoresist layer 112, and the second hard mask layer 110 are exposed to patterned energy 130, and post-exposure baking (PEB) is performed to induce decrosslinking in the photoresist layer 112, forming a decrosslinked portion 112d. Besides the formation of acid / base 134a in the second hard mask layer 110 and acid / base 134b in the third hard mask layer 116, the exposure to patterned energy 130 and post-exposure baking can be related to the above... Figure 4 Those described are similar or identical. Both acid / base 134a and acid / base 134b can be transferred to photoresist layer 112 and can be applied as described above. Figure 4 The post-exposure baking process promotes decrosslinking in the photoresist layer 112. The inclusion of photosensitive compounds in both the second hard mask layer 110 and the third hard mask layer 116 disposed on opposite sides of the photoresist layer 112 helps ensure sufficient decrosslinking in the photoresist layer 112, which improves the etch selectivity between the decrosslinked portion 112d and the remaining portion of the photoresist layer 112 not exposed to the patterned energy 130. This improves etching performance, reduces defects such as dross and bridging, reduces linewidth roughness and line edge roughness, and allows for smaller critical dimensions with the photoresist layer 112.

[0045] exist Figure 9 In the process, the third hard mask layer 116 is removed. The third hard mask layer 116 can be removed by dry etching, wet etching, CMP, or a combination thereof. After removing the third hard mask layer 116, the decrosslinked portion 112d of the photoresist layer 112 can be removed, and this can be performed as described above. Figure 6 and Figure 7 The steps.

[0046] The embodiments can achieve various advantages. For example, by forming the photoresist layer 112 through CVD, ALD, etc., the photoresist layer 112 can have controllable film thickness, high film uniformity (including uniform film density), and large-area deposition. The photoresist layer 112 can be deposited without the use of toxic solvents, resulting in a more environmentally friendly process and higher material efficiency. The photoresist layer 112 can be an organometallic material, which has good patterned energy absorption and good etch resistance. This allows the photoresist layer 112 to be used for reduced critical size etching. The above methods and materials can be used to improve device performance, reduce device size, and reduce device defects. Forming a third hard mask layer 116 above the photoresist layer 112 can further improve the etching performance of the photoresist layer 112, thereby reducing device defects, lowering the achievable critical size, and improving device performance.

[0047] According to an embodiment, a method includes: spin-coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, and depositing the photoresist layer using one or more organometallic precursors; heating the photoresist layer to induce crosslinking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to induce decrosslinking in the photoresist layer, forming a decrosslinked portion of the photoresist layer; and removing the decrosslinked portion of the photoresist layer. In an embodiment, the first hard mask layer includes a photosensitive compound. In an embodiment, exposing the photoresist layer to patterned energy also exposes the first hard mask layer to patterned energy, generating an acid or base in the first hard mask layer, the acid or base transferring to the photoresist layer, and reacting with the photoresist layer during decrosslinking. In an embodiment, the method further includes spin-coating a second hard mask layer over the photoresist layer, the second hard mask layer including an additional photosensitive compound. In one embodiment, one or more organometallic precursors include a first precursor and a second precursor. The first precursor includes M(CH₂COOX)₄ or M(CH₂COOR)₄, and the second precursor includes M(CH=CH₂)₄ or M(CH(CH₃)X)₄, where M represents a metal, X represents a halogen, and R represents an alkyl group. In another embodiment, one or more organometallic precursors include a first precursor and a second precursor. The first precursor includes M(N=C=O)₄, and the second precursor includes M(CH=CH₂)₄ or M(CH(CH₃)X)₄, where M represents a metal and X represents a halogen. In yet another embodiment, the photoresist layer is heated to induce decrosslinking and release carbon dioxide.

[0048] According to another embodiment, a method includes reacting a first precursor with a first reactant to form a first compound, the first precursor comprising M(CH2COOX)4 or M(CH2COOR)4, where M represents a metal, X represents a halogen, and R represents an alkyl group; reacting a second precursor with the first reactant to form a second compound, the second precursor comprising M(CH=CH2)4 or M(CH(CH3)X)4; and crosslinking the first compound with the second compound to form a crosslinked compound. In an embodiment, the first reactant comprises water. In an embodiment, the first reactant comprises ammonia. In an embodiment, the first compound with the second compound is crosslinked to form a positive photoresist. In an embodiment, the method further includes depositing the first and second precursors over a target layer by chemical vapor deposition or atomic layer deposition; and performing post-deposition baking on the first and second compounds to induce crosslinking of the first and second compounds. In an embodiment, the method further includes exposing the crosslinked compound to patterned energy; and performing post-exposure baking on the crosslinked compound to induce decrosslinking of the crosslinked compound. In an embodiment, the first and second precursors are supplied at a flow rate from 100 sccm to 2000 sccm, and the first and second precursors are deposited at a temperature of 100°C to 500°C, a pressure in the range of 5 mTorr to 10 Torr, and an applied plasma power of less than 1000 W.

[0049] According to yet another embodiment, a method includes forming a first hard mask layer over a target layer; and forming a crosslinked photoresist over the first hard mask layer, the crosslinking of the photoresist including crosslinking a first organometallic compound with a second organometallic compound, the first organometallic compound including M(CH₂COOH)₄ or M(N=C=O)₄, and the second organometallic compound including M(CH(CH₃)OH)₄ or M(CH(CH₃)NH₂)₄, where M represents a metal and X represents a halogen. In an embodiment, the method further includes forming a second hard mask layer over the crosslinked photoresist. In an embodiment, the first hard mask layer and the second hard mask layer include a photoacid generator and a photoalkali generator. In an embodiment, the method further includes exposing the crosslinked photoresist to patterned energy and performing post-exposure baking to form decrosslinked portions from the crosslinked photoresist. In an embodiment, the method further includes exposing the crosslinked photoresist and the decrosslinked portions to a developer to remove the decrosslinked portions. In an embodiment, the metal includes tin, bismuth, antimony, indium, or tellurium.

[0050] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: Spin-coat a first hard mask layer over the target layer; A photoresist layer is deposited over the first hard mask layer using chemical vapor deposition or atomic layer deposition, wherein one or more organometallic precursors are used to deposit the photoresist layer, wherein the one or more organometallic precursors include a first precursor and a second precursor, the first precursor including M(CH2COOX)4 or M(CH2COOR)4, and the second precursor including M(CH=CH2)4 or M(CH(CH3)X)4, wherein M represents a metal, X represents a halogen, and R represents an alkyl group; Heating the photoresist layer to induce cross-linking between the one or more organometallic precursors; Expose the photoresist layer to patterned energy; Heating the photoresist layer to induce decrosslinking in the photoresist layer, forming decrosslinked portions of the photoresist layer; and Remove the decrosslinked portion of the photoresist layer.

2. The method according to claim 1, wherein, The first hard mask layer includes a photosensitive compound.

3. The method according to claim 2, wherein, Exposing the photoresist layer to the patterned energy also exposes the first hard mask layer to the patterned energy, wherein exposing the first hard mask layer to the patterned energy generates an acid or base in the first hard mask layer, wherein the acid or base is transferred to the photoresist layer, and wherein the acid or base reacts with the photoresist layer during decrosslinking of the photoresist layer.

4. The method according to claim 2, further comprising: A second hard mask layer is spin-coated over the photoresist layer, the second hard mask layer including an additional photosensitive compound.

5. The method according to claim 1, wherein, The halogens include chlorine.

6. The method according to claim 1, wherein, The metal includes tin, bismuth, antimony, indium, or tellurium.

7. The method according to claim 1, wherein, Heating the photoresist layer causes decrosslinking in the photoresist layer, releasing carbon dioxide.

8. A method of forming a semiconductor device, comprising: A first precursor is reacted with a first reactant to form a first compound, the first precursor comprising M(CH2COOX)4 or M(CH2COOR)4, wherein M represents a metal, X represents a halogen, and R represents an alkyl group; The second precursor reacts with the first reactant to form a second compound, the second precursor comprising M(CH=CH2)4 or M(CH(CH3)X)4; and The first compound is crosslinked with the second compound to form a crosslinked compound.

9. The method according to claim 8, wherein, The first reactant includes water.

10. The method according to claim 8, wherein, The first reactant includes ammonia.

11. The method according to claim 8, wherein, The first compound and the second compound are crosslinked to form a positive photoresist.

12. The method according to claim 8, further comprising: The first precursor and the second precursor are deposited over the target layer by chemical vapor deposition or atomic layer deposition; as well as Post-deposition baking is performed on the first compound and the second compound to induce crosslinking between the first compound and the second compound.

13. The method of claim 12, further comprising: The cross-linked compound is exposed to patterned energy; as well as The cross-linked compound is subjected to post-exposure baking to induce decrosslinking of the cross-linked compound.

14. The method according to claim 12, wherein, The first precursor and the second precursor are supplied at a flow rate from 100 sccm to 2000 sccm, and wherein the first precursor and the second precursor are deposited at a temperature of 100°C to 500°C, a pressure in the range of 5 mTorr to 10 Torr, and an applied plasma power of less than 1000 W.

15. A method of forming a semiconductor device, comprising: A first hard mask layer is formed above the target layer; as well as A cross-linked photoresist is formed over the first hard mask layer, wherein forming the cross-linked photoresist includes cross-linking a first organometallic compound with a second organometallic compound, wherein the first organometallic compound includes M(CH2COOH)4 or M(N=C=O)4, and wherein the second organometallic compound includes M(CH(CH3)OH)4 or M(CH(CH3)NH2)4, wherein M represents a metal.

16. The method of claim 15, further comprising forming a second hard mask layer over the crosslinked photoresist.

17. The method according to claim 16, wherein, The first hard mask layer and the second hard mask layer include a photoacid generator and a photoalkali generator.

18. The method of claim 15, further comprising exposing the crosslinked photoresist to patterned energy and performing post-exposure baking to form decrosslinked portions from the crosslinked photoresist.

19. The method of claim 18, further comprising exposing the crosslinked photoresist and the decrosslinked portion to a developer to remove the decrosslinked portion.

20. The method of claim 15, wherein, The metal includes tin, bismuth, antimony, indium, or tellurium.

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