Chip position adjustment method and device, terminal and storage medium
By automatically detecting and adjusting the placement of small chips in EDA tools, the problem of relying on manual methods for accurate chip placement on the canvas is solved, achieving efficient chip position adjustment and improving design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN CHIPULLER CHIP TECH CO LTD
- Filing Date
- 2022-11-09
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, the accurate placement of small chips in the EDA tool canvas relies on manual operation, resulting in low design efficiency.
By automatically detecting the initial placement position of the chip in the EDA tool and determining the target placement position based on the initial position, the chip can be automatically adjusted using methods such as search area and overlap area calculation.
It improves the accuracy of chip placement on the canvas and design efficiency, reducing the manual operation time for designers.
Smart Images
Figure CN115763342B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of EDA technology, and more specifically, to a method, apparatus, terminal, and storage medium for adjusting the position of a chip. Background Technology
[0002] Chiplet technology refers to breaking down a System on Chip (SoC) into multiple smaller chips, which may have different functions and processes. These modular chips are then packaged together using novel packaging technologies to achieve interconnection and form a heterogeneous integrated chip.
[0003] To facilitate the widespread application of chipplet technology, it has been incorporated into EDA (Electronic Design Automation). In chipplet-based EDA, a chip placement process typically involves placing the chips onto a pre-defined canvas. The position of the chip on the canvas in EDA corresponds to its position on the active silicon substrate within the actual SoC (System-on-a-Chip). The active silicon substrate usually contains a programmable routing network for interconnecting the chips. In practice, the side of the active silicon substrate in contact with the chip typically has metal bumps. These bumps connect to the programmable routing network in the active silicon substrate, allowing for interconnection between any two bumps by controlling the network. The bottom of the chip also has metal bumps, which, through contact with the bumps on the active silicon substrate, enable interconnection via the programmable routing network. At this point, in order to ensure the signal transmission effect between the chiplet and the active silicon substrate, the metal bumps of the chiplet and the metal bumps of the active silicon substrate often need to be accurately aligned, or have a contact area as large as possible, or have as many contact points as possible. To ensure accurate alignment between the metal bumps of the chiplet and the metal bumps of the active silicon substrate, or to have a contact area as large as possible, or to have as many contact points as possible, there are relatively high requirements for the placement of the chiplet on the canvas in the EDA tools during the chip design stage.
[0004] Currently, the accurate placement of small chips on the canvas relies solely on manual labor. Summary of the Invention
[0005] The main objective of this application is to provide a method, apparatus, terminal, and storage medium for adjusting the position of a chip, so as to solve the problem in the related art of relying solely on manual labor to achieve the accuracy of placing a small chip in the canvas.
[0006] To achieve the above objectives, in a first aspect, this application provides a method for adjusting the position of a chip, comprising:
[0007] In response to the target chip being placed in the canvas, the initial placement position of the target chip in the canvas is detected. The canvas includes multiple grid cells arranged in an array. Each grid cell in the multiple grid cells is provided with a contact point, which is used to characterize the contact point of the active silicon substrate.
[0008] Based on the initial placement position, determine the target placement position corresponding to the target chip, and adjust the target chip to the target placement position.
[0009] In one possible implementation, the target placement position of the target chip is determined based on the initial placement position, including:
[0010] Check whether the initial placement position is aligned with the preset reference position;
[0011] If the initial placement position is aligned with the preset reference position, the initial placement position will be used as the target placement position for the target chip.
[0012] In one possible implementation, the method also includes:
[0013] If the initial placement position is not aligned with the preset reference position, search for the existence of a reference position within the search area formed by the initial placement position as the center and the first offset as the radius;
[0014] If a reference position exists within the search area, the target placement position is determined based on the number of reference positions and the initial placement position.
[0015] In one possible implementation, the target placement position is determined based on the number of reference positions and the initial placement position, including:
[0016] If there is only one reference position, the reference position will be used as the target placement position.
[0017] In one possible implementation, the target placement position is determined based on the number of reference positions and the initial placement position, including:
[0018] If there are multiple reference positions, select the position that is closest to the initial placement position from among the multiple reference positions as the target reference position;
[0019] Use the target reference position as the target placement position.
[0020] In one possible implementation, the method also includes:
[0021] If no reference position is found within the search area, the first offset is expanded until a reference position is found within the search area centered on the initial placement position and with the expanded first offset as the radius. Then, the step of determining the target placement position based on the number of reference positions and the initial placement position is executed.
[0022] In one possible implementation, the target placement position of the target chip is determined based on the initial placement position, including:
[0023] Based on the initial placement position, multiple candidate placement positions are determined. These multiple candidate placement positions are obtained by moving the target chip from the initial placement position with a second offset.
[0024] The target placement position is determined based on the initial placement position and multiple candidate placement positions.
[0025] In one possible implementation, the target placement position is determined based on the initial placement position and multiple candidate placement positions, including:
[0026] Calculate the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position to obtain the first overlap area;
[0027] Calculate the overlap area of all chip contacts in the target chip with all contacts corresponding to each of the multiple candidate placement positions to obtain multiple candidate overlap areas, wherein the multiple candidate placement positions correspond one-to-one with the multiple candidate overlap areas.
[0028] The first overlapping area is compared with multiple candidate overlapping areas to determine the target placement position.
[0029] In one possible implementation, the first overlap area is compared with multiple candidate overlap areas to determine the target placement position, including:
[0030] If the first overlapping area is greater than each of the multiple candidate overlapping areas, the initial placement position is taken as the target placement position.
[0031] In one possible implementation, the first overlap area is compared with multiple candidate overlap areas to determine the target placement position, including:
[0032] Sort the first overlapping area and multiple candidate overlapping areas in a forward order to obtain all overlapping areas after sorting.
[0033] Select the last overlapping area among all sorted overlapping areas as the target overlapping area, and use the placement position corresponding to the target overlapping area as the target placement position.
[0034] In one possible implementation, the first overlap area is obtained by calculating the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position, including:
[0035] For each chip contact in the target chip, obtain multiple contacts corresponding to the chip contact, and determine the overlap area between the chip contact and each of the multiple contacts based on the distance between the center of the chip contact and the center of each of the multiple contacts.
[0036] The overlapping area of the chip contact with each of the multiple contacts is summarized and calculated to obtain the overlapping area corresponding to the chip contact.
[0037] The first overlapping area is obtained by summing the overlapping areas of all chip contacts.
[0038] In one possible implementation, the overlap area between the chip contact and each of the multiple contacts is determined based on the distance between the center of the chip contact and the center of each of the multiple contacts, including:
[0039] For each of the multiple contacts, determine the distance interval to which the distance between the centers of the chip contacts belongs;
[0040] Obtain the area corresponding to the distance interval and use the area as the overlapping area between chip contacts.
[0041] Secondly, embodiments of the present invention provide a chip position adjustment device, comprising:
[0042] The detection module is used to detect the initial placement position of the target chip in the canvas in response to the target chip being set in the canvas. The canvas includes multiple grid cells arranged in an array. Each grid cell in the multiple grid cells is provided with a contact point, which is used to characterize the contact point of the active silicon substrate.
[0043] The adjustment module is used to determine the target placement position of the target chip based on the initial placement position, and adjust the target chip to the target placement position.
[0044] Thirdly, embodiments of the present invention provide a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the chip position adjustment methods described above.
[0045] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the chip position adjustment methods described above.
[0046] This invention provides a method, apparatus, terminal, and storage medium for adjusting the position of a chip. The method includes: first, responding to a target chip being placed on a canvas, detecting the initial placement position of the target chip on the canvas; then, based on the initial placement position, determining the target placement position corresponding to the target chip; and finally, adjusting the target chip to the target placement position. After the target chip is placed on the canvas of an EDA tool, the EDA tool automatically detects the placement position of the target chip on the canvas, i.e., the initial placement position, and determines whether the initial placement position is the target placement position. When the initial placement position is not the target placement position, the target placement position can be determined based on the initial placement position, and the target chip can be automatically adjusted to the target placement position, thereby achieving automatic adjustment of the target chip position, avoiding manual operation by designers, and improving work efficiency. Attached Figure Description
[0047] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of the accompanying drawings are used to explain the application and do not constitute an undue limitation of the application. In the drawings:
[0048] Figure 1 This is a schematic diagram of the design page of existing EDA software provided in an embodiment of the present invention;
[0049] Figure 2 This is a flowchart illustrating the implementation of a chip position adjustment method provided in an embodiment of the present invention;
[0050] Figure 3 This is a schematic diagram of the small chip U9 provided in an embodiment of the present invention;
[0051] Figure 4 This is a schematic diagram of the small chip U2 provided in an embodiment of the present invention;
[0052] Figure 5 This is a schematic diagram of the small chip U23 provided in an embodiment of the present invention;
[0053] Figure 6 This is a schematic diagram of the small chip U1 provided in an embodiment of the present invention;
[0054] Figure 7 This is a schematic diagram showing the positional relationship between the small chip U9 and the canvas provided in an embodiment of the present invention;
[0055] Figure 8 This is a schematic diagram showing that the small chip U9 provided in this embodiment of the invention is not aligned with the reference position;
[0056] Figure 9 This is a schematic diagram showing the alignment of the small chip U9 with a reference position according to an embodiment of the present invention.
[0057] Figure 10 This is a schematic diagram showing the positional relationship between the small chip U9 and multiple reference positions provided in an embodiment of the present invention;
[0058] Figure 11 This is a schematic diagram of the small chip U2 provided in an embodiment of the present invention being disposed at the initial placement position E;
[0059] Figure 12 This is a schematic diagram of the small chip U2 provided in an embodiment of the present invention disposed at the first candidate placement position F;
[0060] Figure 13 This is a schematic diagram of the small chip U2 provided in an embodiment of the present invention being disposed at the second candidate placement position G;
[0061] Figure 14 This is a schematic diagram of the structure of a chip position adjustment device provided in an embodiment of the present invention;
[0062] Figure 15 This is a schematic diagram of the terminal provided in an embodiment of the present invention. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0064] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.
[0065] It should be understood that in the various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0066] It should be understood that in this invention, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.
[0067] It should be understood that in this invention, "multiple" refers to two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, "and / or B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Contains A, B, and C", "Contains A, B, and C" means that all three A, B, and C are contained; "Contains A, B, or C" means that one of A, B, and C is contained; "Contains A, B, and / or C" means that any one, two, or three of A, B, and C are contained.
[0068] It should be understood that in this invention, "B corresponding to A", "B corresponding to A", "A and B correspond", or "B and A correspond" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. Matching A and B is defined as a similarity between A and B that is greater than or equal to a preset threshold.
[0069] Depending on the context, "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection."
[0070] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0071] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.
[0072] Existing EDA software, such as Figure 1 As shown, the EDA software page contains very few controls, among which the essential ones are the electrical toolbar and the drawing toolbar. The electrical toolbar contains various types of components. Users can click on the components they want to place on the canvas and then drag and drop them to proceed with subsequent hardware design. These components include, but are not limited to, small chips.
[0073] However, existing EDA software lacks automatic detection and adjustment capabilities for chip placement. Designers typically need to rely on their experience to place the chips accurately. For inexperienced designers, after placing the chips on the EDA software canvas, they must observe their placement. If inaccurate, manual adjustment is required.
[0074] Therefore, designers need to spend a lot of time placing the small chips, which reduces work efficiency.
[0075] To address the aforementioned issues, this application proposes a chip placement adjustment method that can automatically detect and adjust the chip's position, thereby improving the work efficiency of designers.
[0076] In one embodiment, such as Figure 2 As shown, a method for adjusting the position of a chip is provided, including the following steps:
[0077] Step S201: In response to the target chip being set in the canvas, detect the initial placement position of the target chip in the canvas.
[0078] The target chip refers to a small chip or chip with arbitrary functions, which includes an outer frame and multiple chip contacts. The type and name of the small chip are displayed around the outer frame, such as... Figure 3 The small chip shown is of type U9 and named TMP108AIYFFT.
[0079] Different types of chiplets have different chip contact parameters, which can be set in the chip library of EDA tools. These parameters include at least the chip contact arrangement, the number of chip contacts, and the radius of each chip contact.
[0080] Combination Figures 3-6 , Figure 3 The chip contacts in the small chip U9 are arranged in a regular pattern (i.e., 2*3 arrangement), and the number of chip contacts is 6. Figure 4 The chip contacts in the small chip U2 are arranged irregularly, and the number of chip contacts is 12. Figure 5 The chip contacts in the small chip U23 are arranged in a regular pattern (i.e., 4*5 arrangement), and the number of chip contacts is 20. Figure 6 The chip contacts in the small chip U1 are arranged in a regular pattern (i.e., a 2x2 arrangement). Furthermore... Figures 3-6 The radii of the chip contacts in the small chips shown are different. Figure 6 The chip with the largest radius is the chip contact point in the small chip shown. Figure 3 The chip junctions in the small chip shown have the smallest radius.
[0081] The canvas comprises multiple grid cells arranged in an array, each of which has a contact point, which is used to characterize the contact point of the active silicon substrate.
[0082] like Figure 7 As shown, the multiple contacts arranged in an array on the EDA tool canvas are the metal bumps (i.e., contact points) on the active silicon substrate. The active silicon substrate has a programmable routing network, and by programming the programmable routing, the connections between the metal bumps on the active silicon substrate can be freely configured.
[0083] Taking the target chip U9 as an example, after the designer selects the U9 chip in the chip library, they can manually drag and drop the U9 chip onto the canvas using the mouse. At this point, the system will respond upon detecting that the U9 chip is set on the canvas, that is, it will automatically detect the initial placement position of the U9 chip on the canvas. The initial placement position can be the coordinates of a point on the chip within the canvas.
[0084] This application uses the coordinates of a point on the microchip within the canvas as the initial placement position for the following reasons: Given a specific microchip type, knowing the coordinates of a point on the canvas allows for the determination of the coordinates of all other points on the microchip within the canvas. For example, using only the coordinates of the lower left corner of the microchip as the initial placement position, once the coordinates of the lower left corner are determined, the coordinates of all other points on the microchip, and even the center coordinates of the chip's contact points, can be calculated based on the microchip type. Using the coordinates of a single point to represent the microchip's position and performing subsequent calculations helps reduce the amount of data processed and improves processing speed.
[0085] Furthermore, when the chip U9 is placed on the canvas, the chip contacts in the chip U9 will contact the metal bumps on the active silicon substrate (achieving a connection), so that signals can be transmitted between the chip and the active silicon substrate.
[0086] It should be noted that due to the different types of chiplets, the radii of the chip contacts in the chiplet are different. Therefore, when a chiplet is placed in the canvas, the overlap area between the chip contacts in the chiplet and the contacts in the canvas is different.
[0087] Step S202: Based on the initial placement position, determine the target placement position corresponding to the target chip, and adjust the target chip to the target placement position.
[0088] When using EDA tools to design the placement of small chips, designers may encounter issues when dragging the target chip with a mouse, resulting in misalignment of the chip contacts and the metal bumps on the active silicon substrate, or the possibility of a better placement position. Therefore, it is necessary to determine the target placement position based on the initial placement position. This allows for the automatic adjustment function of the chip placement position in the EDA tool, which is more conducive to improving design efficiency and effect, and reducing design difficulty.
[0089] This application determines the target placement location of the target chip using two methods, as follows:
[0090] The first method is to detect whether the initial placement position is aligned with the preset reference position. If the initial placement position is aligned with the preset reference position, the initial placement position is used as the target placement position corresponding to the target chip. If the initial placement position is not aligned with the preset reference position, the target placement position is determined by defining a search area based on the initial placement position.
[0091] For example, combined Figure 8 Let the target chip be a small chip U9. Take vertex A, the bottom left corner of the outer edge of the small chip U9, as its initial placement position. Take grid point B, the closest point to the initial placement position on the canvas, as the preset reference position. Then, through... Figure 8 It is known that vertex A at the bottom left corner of the outer frame of the small chip U9 is not aligned with its nearest grid point B. Therefore, the target placement position can be determined by defining a search area based on the initial placement position. That is, the search area formed by the initial placement position as the center and the first offset as the radius is searched to see if a reference position exists. If a reference position exists in the search area, the target placement position is determined based on the number of reference positions and the initial placement position. The first offset can be set according to specific circumstances and is not limited here.
[0092] Furthermore, in combination Figures 8-9 If the number of reference positions is one, that is, as Figure 8 As shown in the grid point B, the reference position is used as the target placement position. Then, the vertex A of the lower left corner of the outer frame of the small chip U9 is adjusted to grid point B, as shown. Figure 9 As shown, the lower left corner vertex of the outer frame of the small chip U9 is aligned with grid point B.
[0093] If there are multiple reference positions, such as Figure 10The three reference points shown are grid points B, C, and D. From these three reference positions, the point closest to vertex A of the lower left corner of the outer frame of the small chip U9 is selected as the target reference point, i.e., grid point B, and grid point B is used as the target placement position. Then, vertex A of the lower left corner of the outer frame of the small chip U9 is adjusted to grid point B, as shown... Figure 9 As shown, the lower left corner vertex of the outer frame of the small chip U9 is aligned with grid point B.
[0094] Furthermore, if no reference position is found within the search area, the first offset is expanded until a reference position is found within the search area centered on the initial placement position and with the expanded first offset as the radius. Then, the step of determining the target placement position based on the number of reference positions and the initial placement position is executed.
[0095] For example, let the first offset be 'a'. When searching with the first offset 'a' as the radius, if no reference position is found, the first offset 'a' can be expanded by a preset multiple, such as 2 or 3, without specific limitation here. When the preset multiple is 2, the expanded first offset is 2a. The search is still performed within the search area formed by the initial placement position as the center and a radius of 2a. If a reference position is found, the target placement position is determined based on the number of reference positions and the initial placement position. If one reference position is found, it is used as the target placement position. If multiple reference positions are found, the reference position closest to the initial placement position is selected as the target placement position. Optionally, when multiple reference positions are found, a suitable reference position can be selected as the target placement position according to various preset rules, such as being as far away as possible from existing chips or the edge of the active silicon substrate.
[0096] Furthermore, if no reference position is found within the search area centered on the initial placement position and with a radius of 2a, the offset is further increased. That is, the reference position is searched within the search area centered on the initial placement position and with a radius of 4a. If no reference position is found, the offset is further increased until the reference position is found.
[0097] In this embodiment, the present application not only automatically detects the initial placement position of the target chip, but also automatically finds the reference position through the initial placement position, thereby determining the target placement position of the target chip, realizing the automation of target chip placement, eliminating the need for manual operation by designers, saving designers' time, and thus improving the efficiency of chip position adjustment and placement work.
[0098] The second method involves determining multiple candidate placement positions based on the initial placement position. These candidate positions are obtained by moving the target chip from the initial placement position using a second offset. The target placement position is then determined based on both the initial placement position and the multiple candidate placement positions. The second offset can be set according to specific circumstances and is not limited here.
[0099] For example, combined Figures 11-13 Let the target chip be chip U2, and its initial position be point E on the canvas. Starting from point E, move chip U2 using the second offset to obtain two candidate positions. The first candidate position is... Figure 12 Point F shown, and the second candidate placement position, i.e. Figure 13 Point G is shown. Then, the target placement position can be determined using the initial placement position E, the first candidate placement position F, and the second candidate placement position G.
[0100] Once the initial placement position and multiple candidate placement positions are determined, the target placement position needs to be determined by calculating the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position and the multiple candidate placement positions. Specifically, first, the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position is calculated to obtain the first overlap area. Then, the overlap area between all chip contacts in the target chip and all contacts corresponding to each of the multiple candidate placement positions is calculated to obtain multiple candidate overlap areas. Each candidate placement position corresponds one-to-one with a candidate overlap area. Finally, the first overlap area and the multiple candidate overlap areas are compared to determine the target placement position.
[0101] The process involves comparing the first overlapping area with multiple candidate overlapping areas to determine the target placement position. This includes two cases: if the first overlapping area is greater than each of the multiple candidate overlapping areas, the initial placement position is taken as the target placement position; or the first overlapping area and multiple candidate overlapping areas are sorted in a forward order to obtain all sorted overlapping areas, and the last overlapping area among all sorted overlapping areas is selected as the target overlapping area, with the placement position corresponding to the target overlapping area taken as the target placement position.
[0102] For example, combined Figures 11-13Calculate the overlap areas of the 12 chip contacts in chip U2 with all contacts corresponding to the initial placement position E, the first candidate placement position F, and the second candidate placement position G, respectively, to obtain the first overlap area S1, the first candidate overlap area S2, and the second candidate overlap area S3. If the first overlap area S1 is greater than the first candidate overlap area S2 and the second candidate overlap area S3, then the initial placement position E corresponding to the first overlap area S1 is taken as the target placement position; if the first overlap area S1 < the first candidate overlap area S2 < the second candidate overlap area S3, then the second candidate placement position G corresponding to the maximum area, i.e., the second candidate overlap area S3, is taken as the target placement position.
[0103] Furthermore, to calculate the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position, and to obtain the first overlap area, it is necessary to obtain multiple contacts corresponding to each chip contact in the target chip, and determine the overlap area between the chip contact and each of the multiple contacts based on the distance between the center of the chip contact and the center of each of the multiple contacts. Then, the overlap areas between the chip contact and each of the multiple contacts are summarized and calculated to obtain the overlap area corresponding to the chip contact. Finally, the overlap areas corresponding to all chip contacts are summed and calculated to obtain the first overlap area.
[0104] Specifically, determining the overlap area between the chip contact's center and the centers of each of the multiple contacts involves identifying the distance interval between the chip contact's center and the centers of other contacts for each of the multiple contacts. The area corresponding to this distance interval is then calculated and used as the overlap area between the chip contacts. This method of calculating the overlap area ensures both accuracy and speed, while also reducing computational load, thus improving the speed of determining the target placement position.
[0105] For example, combined Figure 11 Taking the first chip contact in the upper left corner of the small chip U2 as an example, through Figure 11 It can be seen that the first chip contact in the upper left corner covers multiple contacts in the canvas. Since the first chip contact in the upper left corner only partially covers some contacts in the canvas, the overlapping area is difficult to calculate accurately. Therefore, this application determines the overlapping area by the distance interval between the center of the first chip contact in the upper left corner and the center of the contacts in the canvas.
[0106] Specifically, let the first distance interval be [0-1.5cm], with a corresponding area of L1; the second distance interval be [1.6-2cm], with a corresponding area of L2; the third distance interval be [2.1-2.5cm], with a corresponding area of L3; and the fourth distance interval be [2.6-3cm], with a corresponding area of L4, where L1>L2>L3>L4. Figure 11 It can be seen that the first chip contact in the upper left corner overlaps with 7 contacts in the canvas. Three of these contacts are completely covered, while the other four are partially covered. Specifically, the distance between the three completely covered contacts and the center of the first chip contact in the upper left corner falls within the first distance interval [0-1.5cm], so the corresponding area is 3L1. The distance between the three other contacts and the center of the first chip contact in the upper left corner falls within the third distance interval [2.1-2.5cm], so the corresponding area is 3L3. The distance between the remaining contact and the center of the first chip contact in the upper left corner falls within the fourth distance interval [2.6-3cm], so the corresponding area is L4. Summing all the areas, we can obtain the overlapping area Y1 = 3L1 + 3L3 + L4 of the first chip contact in the upper left corner and the multiple contacts in the covered canvas.
[0107] Using the above method, the overlapping area between other chip contacts in the small chip U2 and the contacts in the covered canvas can be calculated. Then, the overlapping areas of all chip contacts in the small chip U2 and the contacts in the covered canvas are summed to obtain the first overlapping area S1.
[0108] It should be noted that the method of calculating the overlapping area of all chip contacts in the target chip and all contacts corresponding to each of the multiple candidate placement positions in this application to determine the overlapping area of multiple candidates is similar to the method of calculating the first overlapping area, and will not be repeated here.
[0109] Optionally, determining the target placement position of the target chip can also be achieved by combining the first and second methods described above. Specifically, when multiple reference positions are determined using the method of defining the search area based on the initial placement position mentioned in the first method, the overlapping area of all chip contacts in the target chip and all contacts corresponding to the multiple reference positions can be calculated using the overlapping area calculation method mentioned in the second method. Finally, based on the overlapping area corresponding to each reference position, one reference position is selected from the multiple reference positions as the target placement position. The process of determining the reference position, calculating the overlapping area, and selecting the target placement position are all similar to the first and second methods described above, and will not be elaborated further to avoid repetition.
[0110] This invention provides a method for adjusting the position of a chip, comprising: first, in response to a target chip being set in a canvas, detecting the initial placement position of the target chip in the canvas; then, based on the initial placement position, determining the target placement position corresponding to the target chip; and adjusting the target chip to the target placement position. After the target chip is set in the canvas of an EDA tool, the EDA tool automatically detects the placement position of the target chip in the canvas, i.e., the initial placement position, and determines whether the initial placement position is the target placement position. When the initial placement position is not the target placement position, the target placement position can be determined based on the initial placement position, and the target chip can be automatically adjusted to the target placement position, thereby achieving automatic adjustment of the target chip position, avoiding manual operation by designers, and improving work efficiency.
[0111] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0112] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.
[0113] Figure 14 The diagram illustrates a chip position adjustment device according to an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment are shown. The chip position adjustment device includes a detection module 1401 and an adjustment module 1402, as detailed below:
[0114] The detection module 1401 is used to detect the initial placement position of the target chip in the canvas in response to the target chip being set in the canvas. The canvas includes multiple grid cells arranged in an array. Each grid cell in the multiple grid cells is provided with a contact point, which is used to characterize the contact point of the active silicon substrate.
[0115] The adjustment module 1402 is used to determine the target placement position of the target chip based on the initial placement position, and adjust the target chip to the target placement position.
[0116] In one possible implementation, the adjustment module 1402 is further configured to detect whether the initial placement position is aligned with a preset reference position; if the initial placement position is aligned with the preset reference position, the initial placement position is used as the target placement position corresponding to the target chip.
[0117] In one possible implementation, the device further includes a first search unit, which is used to search for the existence of a reference position within a search area formed by the initial placement position as the center and a first offset as the radius if the initial placement position is not aligned with a preset reference position; if a reference position exists within the search area, the target placement position is determined based on the number of reference positions and the initial placement position.
[0118] In one possible implementation, the first search unit is further configured to use the reference position as the target placement position if the number of reference positions is one.
[0119] In one possible implementation, the first search unit is further configured to select, if there are multiple reference positions, the position closest to the initial placement position from the multiple reference positions as the target reference position; and use the target reference position as the target placement position.
[0120] In one possible implementation, the device further includes a second search unit, which is used to expand the first offset if no reference position is found in the search area until a reference position is found in the search area formed by the initial placement position as the center and the expanded first offset as the radius, and to perform the step of determining the target placement position based on the number of reference positions and the initial placement position.
[0121] In one possible implementation, the adjustment module 1402 is further configured to determine multiple candidate placement positions based on the initial placement position, wherein the multiple candidate placement positions are obtained by moving the target chip with the initial placement position as the starting point and by a second offset; and to determine the target placement position based on the initial placement position and the multiple candidate placement positions.
[0122] In one possible implementation, the adjustment module 1402 is further configured to calculate the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position to obtain a first overlap area; calculate the overlap area between all chip contacts in the target chip and all contacts corresponding to each of the multiple candidate placement positions to obtain multiple candidate overlap areas, wherein the multiple candidate placement positions correspond one-to-one with the multiple candidate overlap areas; and compare the first overlap area with the multiple candidate overlap areas to determine the target placement position.
[0123] In one possible implementation, the adjustment module 1402 is further configured to use the initial placement position as the target placement position if the first overlapping area is greater than each of the multiple candidate overlapping areas.
[0124] In one possible implementation, the adjustment module 1402 is further configured to sort the first overlapping area and multiple candidate overlapping areas in a forward sorting manner to obtain all overlapping areas after sorting; select the last overlapping area among all overlapping areas after sorting as the target overlapping area, and take the placement position corresponding to the target overlapping area as the target placement position.
[0125] In one possible implementation, the adjustment module 1402 is further configured to, for each chip contact in the target chip, obtain multiple contacts corresponding to the chip contact, and determine the overlap area between the chip contact and each of the multiple contacts based on the distance between the center of the chip contact and the center of each of the multiple contacts; summarize and calculate the overlap area between the chip contact and each of the multiple contacts to obtain the overlap area corresponding to the chip contact; and sum and calculate the overlap areas corresponding to all chip contacts to obtain the first overlap area.
[0126] In one possible implementation, the adjustment module 1402 is further configured to, for each of the multiple contacts, determine the distance interval to which the distance between the center of the chip contact and the center of the contact belongs; obtain the area corresponding to the distance interval, and use the area as the overlapping area between the chip contact and the contact.
[0127] Figure 15 This is a schematic diagram of a terminal provided in an embodiment of the present invention. Figure 15 As shown, the terminal 15 in this embodiment includes: a processor 1501, a memory 1502, and a computer program 1503 stored in the memory 1502 and executable on the processor 1501. When the processor 1501 executes the computer program 1503, it implements the steps in the above-described embodiments of the chip position adjustment methods, for example... Figure 2 Steps 201 to 202 are shown. Alternatively, when processor 1501 executes computer program 1503, it implements the functions of each module / unit in the above-described embodiments of the chip position adjustment device, for example... Figure 14 The functions of modules / units 1401 to 1402 shown.
[0128] The present invention also provides a readable storage medium storing a computer program, which, when executed by a processor, is used to implement the chip position adjustment method provided in the various embodiments described above.
[0129] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of computer programs from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application-Specific Integrated Circuit (ASIC). Alternatively, the ASIC can be located in a user device. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0130] The present invention also provides a program product including executable instructions stored in a readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the execution of the executable instructions by the at least one processor causes the device to implement the chip position adjustment methods provided in the various embodiments described above.
[0131] In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.
[0132] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A method of adjusting a chip position, characterized by, include: In response to the target chip being placed in a canvas, the initial placement position of the target chip in the canvas is detected, wherein the canvas includes a plurality of grid cells arranged in an array, each of the plurality of grid cells is provided with a contact point, the contact point being used to characterize the contact point of the active silicon substrate; Based on the initial placement position, determine the target placement position corresponding to the target chip, and adjust the target chip to the target placement position; Determining the target placement position corresponding to the target chip based on the initial placement position includes: Detect whether the initial placement position is aligned with the preset reference position; If the initial placement position is aligned with the preset reference position, the initial placement position is taken as the target placement position corresponding to the target chip; The method further includes: If the initial placement position is not aligned with the preset reference position, search for the existence of a reference position within a search area formed by the initial placement position as the center and the first offset as the radius; If the reference position exists within the search area, the target placement position is determined based on the number of reference positions and the initial placement position. Determining the target placement position based on the number of reference positions and the initial placement position includes: If there is only one reference position, then the reference position shall be used as the target placement position. Determining the target placement position based on the number of reference positions and the initial placement position includes: If there are multiple reference positions, the position closest to the initial placement position is selected from the multiple reference positions as the target reference position; The target reference position is used as the target placement position; The method further includes: If the reference position is not found within the search area, the first offset is expanded until the reference position is found within the search area centered on the initial placement position and with the expanded first offset as the radius, and the step of determining the target placement position based on the number of reference positions and the initial placement position is executed.
2. A method of adjusting the position of a chip, characterized by include: In response to the target chip being placed in a canvas, the initial placement position of the target chip in the canvas is detected, wherein the canvas includes a plurality of grid cells arranged in an array, each of the plurality of grid cells is provided with a contact point, the contact point being used to characterize the contact point of the active silicon substrate; Based on the initial placement position, determine the target placement position corresponding to the target chip, and adjust the target chip to the target placement position; Determining the target placement position corresponding to the target chip based on the initial placement position includes: Based on the initial placement position, multiple candidate placement positions are determined, wherein the multiple candidate placement positions are obtained by moving the target chip with the initial placement position as the starting point and by a second offset. Based on the initial placement position and the multiple candidate placement positions, the target placement position is determined; Determining the target placement position based on the initial placement position and the multiple candidate placement positions includes: Calculate the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position to obtain the first overlap area; Calculate the overlap area of all chip contacts in the target chip with all contacts corresponding to each of the multiple candidate placement positions to obtain multiple candidate overlap areas, wherein the multiple candidate placement positions correspond one-to-one with the multiple candidate overlap areas; The first overlapping area is compared with multiple candidate overlapping areas to determine the target placement position.
3. The chip position adjustment method as described in claim 2, characterized in that, The step of comparing the first overlapping area with multiple candidate overlapping areas to determine the target placement position includes: If the first overlapping area is greater than each of the plurality of candidate overlapping areas, the initial placement position is taken as the target placement position.
4. The method of claim 2, wherein the step of adjusting the position of the chip is performed by a user. The step of comparing the first overlapping area with multiple candidate overlapping areas to determine the target placement position includes: Sort the first overlapping area and multiple candidate overlapping areas in a forward sorting order to obtain all overlapping areas after sorting. Select the last overlapping area among all the sorted overlapping areas as the target overlapping area, and take the placement position corresponding to the target overlapping area as the target placement position.
5. The chip position adjustment method as described in claim 2, characterized in that, The calculation of the overlap area between all chip contacts in the target chip and all contacts corresponding to the initial placement position to obtain the first overlap area includes: For each chip contact in the target chip, obtain multiple contacts corresponding to the chip contact, and determine the overlap area between the chip contact and each of the multiple contacts based on the distance between the center of the chip contact and the center of each of the multiple contacts. The overlapping area of the chip contact with each of the plurality of contacts is summed and calculated to obtain the overlapping area corresponding to the chip contact. The first overlapping area is obtained by summing the overlapping areas corresponding to all chip contacts.
6. The chip position adjustment method of claim 5, wherein, Determining the overlap area between the chip contact and each of the plurality of contacts based on the distance between the center of the chip contact and the center of each of the plurality of contacts includes: For each of the plurality of contacts, determine the distance interval to which the distance between the center of the chip contact and the center of the contact belongs; Obtain the area corresponding to the distance interval, and use the area as the overlapping area between the chip contact and the contact.
7. A chip position adjustment device, characterized by include: A detection module is used to detect the initial placement position of the target chip in the canvas in response to the target chip being placed in the canvas, wherein the canvas includes a plurality of grid cells arranged in an array, each of the plurality of grid cells is provided with a contact point, the contact point being used to characterize the contact point of the active silicon substrate. An adjustment module is used to determine the target placement position corresponding to the target chip based on the initial placement position, and to adjust the target chip to the target placement position; The adjustment module is specifically used to: detect whether the initial placement position is aligned with a preset reference position; if the initial placement position is aligned with the preset reference position, use the initial placement position as the target placement position corresponding to the target chip; The adjustment module is also used to: if the initial placement position is not aligned with the preset reference position, search for the existence of a reference position within a search area formed by the initial placement position as the center and the first offset as the radius; If the reference position exists within the search area, the target placement position is determined based on the number of reference positions and the initial placement position. The adjustment module is also used to: if the number of reference positions is one, use the reference position as the target placement position; The adjustment module is specifically used for: if there are multiple reference positions, selecting the position closest to the initial placement position from the multiple reference positions as the target reference position; and using the target reference position as the target placement position. The adjustment module is further configured to: if the reference position does not exist in the search area, expand the first offset until the reference position is found in the search area formed by the initial placement position as the center and the expanded first offset as the radius, and perform the step of determining the target placement position based on the number of reference positions and the initial placement position.
8. A terminal, characterized by comprising: Includes a memory, and one or more processors communicatively connected to the memory; The memory stores instructions that can be executed by the one or more processors to cause the one or more processors to implement the chip position adjustment method as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, Includes a program or instructions that, when run on a computer, implement the chip position adjustment method according to any one of claims 1 to 6.