Embedded SiGe Deposition Method

Abstract

This invention provides an embedded SiGe deposition method. Based on the proportion of I / O areas in the product layout design, different redundant patterns are selected to fill the product layout design. While ensuring that the active area and gate patterns meet design rules, this effectively improves the germanium-silicon deposition density, saves germanium-silicon process growth cycle time, increases production capacity, and significantly improves the manufacturer's economic benefits. Furthermore, the embedded SiGe deposition method provided by this invention solves the problem of excessive differences in germanium-silicon deposition density caused by different product designs under the same process platform, ensuring the stability of process deviations. It effectively solves the problem of low germanium-silicon deposition density affecting the germanium-silicon deposition rate in some products, increasing the wafer fabrication speed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing, and specifically relates to an embedded SiGe deposition method. Background Technology

[0002] As MOSFETs shrink, embedded silicon-germanium (SiGe) technology has been introduced for PMOS devices to improve performance. This technology applies stress to enhance hole mobility, thereby improving PMOS device performance. Embedded SiGe is widely used in stress engineering in 90nm and below technologies. It utilizes the compressive stress generated by the difference in lattice constants between germanium and silicon, embedding it in the source and drain regions to improve hole mobility and saturation current. In layout design, due to electrical performance requirements, I / O regions often have larger linewidths and higher hole mobility and saturation current; these regions do not require SiGe enhancement. The proportion of the I / O region is a key factor affecting the overall SiGe deposition density of the layout.

[0003] In manufacturing processes, the influencing factors of germanium-silicon deposition rate are temperature, pressure, and flow rate. Within the same process platform, the flow rate of the deposition process is adjusted according to the deposition density of the layout to achieve the same deposition effect. Once the germanium-silicon deposition density of the product layout is determined, the process flow rate is fixed, and the germanium-silicon deposition rate is also fixed, making it impossible to differentiate between different products through process modifications. If the germanium-silicon deposition density of a product is too low, it will severely affect the germanium-silicon deposition rate of that product, thereby affecting the throughput of in-line wafers. If the germanium-silicon deposition density can be effectively balanced among different products on the same platform at the design stage, and the germanium-silicon growth density can be effectively improved while ensuring that the active area pattern and gate pattern meet design rules, it can save germanium-silicon layer growth cycles and increase production capacity, which is very useful for manufacturers. Summary of the Invention

[0004] The purpose of this invention is to provide an embedded SiGe deposition method to improve SiGe deposition density, save the growth cycle of germanium-silicon processes, and increase production capacity.

[0005] To achieve the above objectives, the present invention provides an embedded SiGe deposition method, comprising:

[0006] Obtain the product layout design, which includes at least an active region, a gate region, a germanium-silicon region, and an I / O region;

[0007] The proportion of I / O area in the layout design is calculated. Based on the difference G between the proportion of I / O area and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design.

[0008] Based on the filled layout, a photomask is designed and published, and an embedded germanium-silicon deposition process is performed.

[0009] Optionally, based on the difference G between the proportion of the I / O region and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design, including:

[0010] When G≤0, the germanium-silicon deposition density is not corrected by using redundant pattern filling layout design;

[0011] When G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant graphics.

[0012] Optionally, when G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant patterns, including: selecting redundant patterns with different germanium-silicon deposition densities to fill the layout design based on the relationship between G and the second threshold d2, wherein...

[0013] When 0 < G ≤ d2, the expandable repeating units in the redundant graphics are copied according to the size of the fillable area of ​​the redundant graphics in the layout design, so as to increase the number of silicon cavities in the germanium-silicon deposition process and improve the overall germanium-silicon deposition density of the layout design.

[0014] When G > d2, the expandable repeating units in the redundant pattern are copied according to the size of the fillable area of ​​the redundant pattern in the layout design. This increases the number of silicon cavities in the germanium-silicon deposition process. At the same time, the active area patterns in the redundant pattern with fewer expandable area units than the set value are merged to increase the area of ​​the silicon cavities and improve the overall germanium-silicon deposition density of the layout design.

[0015] Optionally, when G≤0, instead of correcting the germanium-silicon deposition density by filling the layout design with redundant graphics, the method further includes selecting standard redundant graphics of the product platform for filling within the fillable area of ​​the layout design.

[0016] Optionally, the proportion of the I / O area is the ratio of the area of ​​the I / O design mark hierarchy to the total area of ​​the layout design.

[0017] Optionally, the first threshold d1 includes the average percentage of I / O areas in products produced in stable batches on the product platform.

[0018] Optionally, the value of the first threshold d1 is between 10% and 12%.

[0019] Optionally, the value of the second threshold d2 is between 3% and 8%.

[0020] Optionally, the value of the second threshold d2 is 5%.

[0021] Optionally, the set value is less than or equal to 10.

[0022] In summary, the embedded SiGe deposition method provided by this invention selects different redundant patterns to fill the product layout design based on the proportion of I / O areas in the product layout design. Under the premise of ensuring that the active area pattern and gate pattern meet the design rules, it effectively improves the germanium silicon deposition density, saves the germanium silicon process growth cycle, increases production capacity, and greatly improves the economic benefits of manufacturers.

[0023] Furthermore, the embedded SiGe deposition method provided by this invention solves the problem of excessive differences in germanium-silicon deposition density caused by different product designs under the same process platform, ensuring the stability of process deviations. It effectively solves the problem of insufficient germanium-silicon deposition density affecting the germanium-silicon deposition rate in some products, thereby increasing the wafer fabrication speed. Attached Figure Description

[0024] Figure 1 A flowchart of an embedded SiGe deposition method provided in an embodiment of the present invention;

[0025] Figures 2A to 2C This is a schematic diagram of a redundant graphic addition unit in a redundant graphic fillable area provided in an embodiment of the present invention;

[0026] Figures 3A to 3C This invention provides a method for adding redundant patterns in a germanium-silicon deposition process, according to an embodiment of the present invention.

[0027] The attached figures are labeled as follows:

[0028] 100 - Active region pattern, 101 - Gate pattern, 102 - Germanium-silicon pattern, 110 - Expandable repeating unit 110. Detailed Implementation

[0029] Researchers discovered through layout analysis that the SiGe deposition rate in embedded germanium-silicon processes is strongly correlated with SiGe deposition density. Low throughput in the product manufacturing process is attributed to the low SiGe deposition density in the product's layout design. No SiGe main pattern is generated under the I / O region (oxide layer, MOX). Furthermore, the design characteristics of the I / O region limit the addition of SiGe dummy deposits. Therefore, the SiGe deposition density in embedded germanium-silicon processes is limited by the proportion of the I / O region in the layout. In other words, the SiGe deposition rate is heavily dependent on the active and gate patterns, i.e., the number and area of ​​silicon holes on the wafer. Selective SiGe processes need to address the differences in layouts, which is extremely challenging. Here, the SiGe deposition density (Dens) is equal to the ratio of the sum of the silicon-germanium pattern area and the active region pattern area, minus the gate pattern area, to the layout area, i.e., Dens = AREA((silicon-germanium pattern and active region pattern) not gate pattern) / AREA (layout area).

[0030] The germanium-silicon deposition density varies depending on the layout design, affecting the germanium-silicon deposition rate. The proportion of the I / O area is crucial in influencing the overall germanium-silicon deposition density of the layout. When the proportion of the I / O design area for a product on the same process platform is greater than the platform average, it is difficult to resolve the issue of low deposition rate due to layout design affecting throughput through process modifications. Selective SiGe processes need to address the differences between different layouts, which is extremely challenging. If the SiGe deposition density of different products can be balanced in advance during the design phase, it will accelerate the epitaxial growth rate of SiGe, increase SiGe layer throughput, and improve the manufacturer's economic benefits.

[0031] Furthermore, researchers have discovered that redundant pattern filling is an effective way to achieve uniform pattern density in embedded germanium-silicon processes, and the germanium-silicon deposition density of redundant patterns is determined by the active region pattern and the gate pattern. In view of this, this invention proposes an embedded germanium-silicon deposition method. Based on the proportion of I / O areas in the product layout, different redundant pattern unit designs are selected to fill the product with redundant patterns. Under the premise of ensuring that the active region pattern and the gate pattern meet the design rules, the germanium-silicon deposition density is effectively improved, the germanium-silicon process growth cycle is saved, the production capacity is increased, and the economic benefits of manufacturers are greatly improved.

[0032] Figure 1 This is a flowchart illustrating an embedded SiGe deposition method according to an embodiment of the present invention. (See reference...) Figure 1 As shown, the embedded SiGe deposition method provided in this embodiment includes:

[0033] S01: Obtain the layout design of the product, wherein the layout design includes at least an active region, a gate region, a germanium-silicon region, and an I / O region;

[0034] S02: Calculate the proportion of I / O areas in the layout design; based on the difference G between the proportion of I / O areas and the first threshold d1, select redundant patterns with different germanium-silicon deposition densities to fill the layout design; and...

[0035] S03: Design and publish the photomask based on the filled layout, and perform embedded germanium-silicon deposition process.

[0036] The following combination Figure 1 This embodiment provides a detailed description of the embedded SiGe deposition method.

[0037] First, step S01 is executed to obtain the product layout design, which includes at least an active region, a gate region, a germanium-silicon region, and an I / O region.

[0038] Next, step S02 is executed to calculate the proportion of I / O areas in the layout design. Based on the difference G between the proportion of I / O areas and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design.

[0039] Specifically, based on the difference G between the proportion of the I / O region and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design, including:

[0040] When G≤0, the germanium-silicon deposition density is not corrected by filling the layout design with redundant graphics. Instead, the standard redundant graphics of the product platform are selected to fill the fillable area of ​​the layout design.

[0041] When G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant graphics.

[0042] Furthermore, when G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant patterns, including: selecting redundant patterns with different germanium-silicon deposition densities to fill the layout design based on the relationship between G and the second threshold d2, wherein...

[0043] When 0 < G ≤ d2, the expandable repeating units in the redundant graphics are copied according to the size of the fillable area of ​​the redundant graphics in the layout design, so as to increase the number of silicon cavities in the germanium-silicon deposition process and improve the overall germanium-silicon deposition density of the layout design.

[0044] When G > d2, the expandable repeating units in the redundant pattern are copied according to the size of the fillable area of ​​the redundant pattern in the layout design. This increases the number of silicon cavities in the germanium-silicon deposition process. At the same time, the active area patterns in the redundant pattern with a number of expandable repeating units less than the set value are merged to increase the area of ​​the silicon cavities and improve the overall germanium-silicon deposition density of the layout design.

[0045] Redundant pattern filling is an effective way to achieve uniform pattern density, and the germanium-silicon deposition density of redundant patterns is determined by the active region pattern and the gate pattern. Figures 2A to 2C This is a schematic diagram illustrating the addition of dummy cells to redundant graphics in a fillable region of a redundant graphic in this embodiment. Figure 2A This is a redundant patterning unit used in a germanium-silicon deposition process, comprising an active region pattern 100, a gate pattern 101, and a germanium-silicon pattern 102. Figure 2B and Figure 2C In order to be in Figure 2A An improved variable redundancy graphical addition unit based on the existing structure, wherein, Figure 2B exist Figure 2A Based on this, an expandable repeatable unit 110 is added to increase the proportion of silicon holes. Figure 2C exist Figure 2ABased on this, some active region patterns 100 are merged to increase the silicon cavity area.

[0046] Figures 3A to 3C This embodiment provides a method for adding redundant patterns in a germanium-silicon deposition process.

[0047] Specifically, when G≤0, meaning the proportion of the I / O region is less than or equal to the first threshold d1, the proportion of the region capable of generating germanium-silicon patterns is high, and it is not necessary to correct the germanium-silicon deposition density through redundant pattern filling layout design. The specific method is as follows: Logical operations are performed on the relevant layers of the redundant patterns to determine their fillable areas. Within the fillable areas of the layout design, standard redundant pattern units from the platform board are selected for filling, resulting in the following effect: Figure 3A As shown.

[0048] When 0 < G ≤ d2, meaning the I / O region proportion is greater than the first threshold d1 but less than the second threshold d2, the area capable of generating germanium-silicon patterns is too low, requiring an increase in the germanium-silicon deposition density of redundant pattern units. The specific method is as follows: Logically calculate the relevant layers of the redundant pattern to determine its fillable region. Then, cut the fillable region into as few quadrilaterals as possible, calculate the area of ​​each fillable quadrilateral, and determine the number of expandable repeating units in the redundant pattern unit. Fill the corresponding filling regions with redundant pattern units that have different numbers of expandable repeating units, thereby increasing the number of silicon cavities in the germanium-silicon deposition process and thus improving the overall germanium-silicon deposition density of the layout. The effect is as follows: Figure 3B As shown;

[0049] When G > d2, meaning the proportion of the I / O region is greater than the second threshold d2, the area capable of generating germanium-silicon patterns is very low, necessitating further increases in the germanium-silicon deposition density of redundant pattern units. The specific method is as follows: Logical operations are performed on the relevant layers of the redundant pattern to determine its fillable area. This fillable area is then divided into as few quadrilaterals as possible. The area of ​​each fillable quadrilateral is calculated to determine the number of expandable repeating units in the redundant pattern unit. Redundant pattern units with different numbers of expandable repeating units are then filled into their corresponding filling areas, resulting in a greater number of silicon cavities in the germanium-silicon deposition process. Simultaneously, active region patterns in redundant pattern units with fewer than a set number of expandable repeating units are merged, increasing the area of ​​silicon cavities in the germanium-silicon deposition process and further improving the overall germanium-silicon deposition density of the layout. The effect is as follows: Figure 3C As shown.

[0050] In this embodiment, the proportion of the I / O area is the ratio of the area of ​​the I / O design markup layer to the total area of ​​the layout design. The first threshold d1 includes the average proportion of the I / O area in the products produced in stable batches on the product platform. The value of the first threshold d1 is between 10% and 12%, for example, the first threshold d1 is 11% or 12%. The value of the second threshold d2 is between 3% and 8%, for example, the second threshold is 5%, 6%, or 7%. The set value is less than or equal to 10, for example, the set value is 7, 8, or 9.

[0051] It should be noted that in this embodiment, the first threshold d1 is the average proportion of the I / O area in products that have been stably produced in large quantities in the past. In other embodiments of the present invention, the first threshold d1 can also be selected according to the actual process requirements. For example, it can be selected by referring to the median proportion of the I / O area in products that have been stably produced in large quantities in the past. Correspondingly, the second threshold d2 or the set value can also be adjusted according to the selection of the first threshold d1.

[0052] In addition, the filling process of the redundant pattern also includes: adjusting the number and area of ​​active regions in the redundant pattern according to the differences in the surrounding environment in the layout design, so as to balance the germanium-silicon deposition density.

[0053] Next, step S03 is executed, where a photomask is designed and published based on the filled layout, and an embedded germanium-silicon deposition process is performed. The layout design and redundant patterns are merged, and a photomask is published and manufactured based on the merged layout design. Subsequent SiGe deposition is then performed based on this photomask. In this embodiment, SiGe deposition can be performed using one of the following methods: selective chemical vapor deposition (CVD), non-selective chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), forming low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD), or selective epitaxial growth (SEG).

[0054] In the SiGe deposition process, the redundant pattern filling process can adjust the number and area of ​​active regions in the redundant pattern according to the proportion of I / O areas in the layout and the differences in the surrounding environment of the layout design, thereby balancing the germanium-silicon deposition density of different products and effectively improving the problem of low germanium-silicon deposition rate caused by design issues.

[0055] In summary, the embedded SiGe deposition method provided in this embodiment selects different redundant patterns to fill the product layout design based on the proportion of I / O areas. This effectively improves the germanium-silicon deposition density while ensuring that the active area and gate patterns meet design rules, saving germanium-silicon process growth cycle time, increasing production capacity, and significantly improving the manufacturer's economic benefits. Furthermore, the embedded SiGe deposition method provided in this embodiment solves the problem of excessive differences in germanium-silicon deposition density caused by different product designs under the same process platform, ensuring the stability of process deviations. It effectively solves the problem of low germanium-silicon deposition density affecting the germanium-silicon deposition rate in some products, increasing the wafer fabrication speed.

[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An embedded SiGe deposition method, characterized in that, include: Obtain the product layout design, which includes at least an active region, a gate region, a germanium-silicon region, and an I / O region; The proportion of I / O area in the layout design is calculated. Based on the difference G between the proportion of I / O area and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design. The proportion of I / O area is the ratio of the area of ​​I / O design mark layer to the total area of ​​the layout design. Based on the filled layout design, a photomask is printed, and an embedded germanium-silicon deposition process is performed; wherein, based on the difference G between the proportion of the I / O area and the first threshold d1, redundant patterns with different germanium-silicon deposition densities are selected to fill the layout design, including: When G ≤ 0, the germanium-silicon deposition density is not corrected by using redundant pattern filling layout design; When G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant patterns; wherein... When G > 0, the germanium-silicon deposition density is corrected by filling the layout design with redundant patterns. This includes: selecting redundant patterns with different germanium-silicon deposition densities to fill the layout design based on the relationship between G and the second threshold d2. When 0 < G ≤ d2, the expandable repeating units in the redundant graphics are copied according to the size of the fillable area of ​​the redundant graphics in the layout design, so as to increase the number of silicon cavities in the germanium-silicon deposition process and improve the overall germanium-silicon deposition density of the layout design. When G > d2, the expandable repeating units in the redundant pattern are copied according to the size of the fillable area of ​​the redundant pattern in the layout design. This increases the number of silicon cavities in the germanium-silicon deposition process. At the same time, the active area patterns in the redundant pattern with fewer expandable area units than the set value are merged to increase the area of ​​the silicon cavities and improve the overall germanium-silicon deposition density of the layout design.

2. The embedded SiGe deposition method according to claim 1, characterized in that, When G ≤ 0, the germanium-silicon deposition density is not corrected by filling the layout design with redundant graphics, and the method also includes selecting standard redundant graphics of the product platform to fill the fillable area of ​​the layout design.

3. The embedded SiGe deposition method according to claim 1, characterized in that, The first threshold d1 includes the average percentage of the I / O area in the products produced in stable batches on the product platform.

4. The embedded SiGe deposition method according to claim 3, characterized in that, The value of the first threshold d1 is between 10% and 12%.

5. The embedded SiGe deposition method according to claim 1, characterized in that, The value of the second threshold d2 is between 3% and 8%.

6. The embedded SiGe deposition method according to claim 5, characterized in that, The value of the second threshold d2 is 5%.

7. The embedded SiGe deposition method according to claim 1, characterized in that, The set value is less than or equal to 10.

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