Semiconductor devices and their fabrication methods
By forming a three-layer back-sealing structure on the back side and edge side of the substrate, the substrate is isolated and protected, which solves the problem of dopant leakage in the epitaxial process and improves the production yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2022-12-02
- Publication Date
- 2026-07-31
AI Technical Summary
In silicon wafer epitaxy, dopants diffuse from the edges of the substrate to the front side at high temperatures, causing edge self-doping, which affects the yield of semiconductor device production.
A three-layer back-sealing structure is adopted, including a first silicon dioxide layer, a polysilicon layer, and a second silicon dioxide layer on the back side and edge side of the substrate, forming a super back-sealing structure to isolate the substrate and protect it from dopants.
It effectively prevents substrate self-doping, thereby improving the production yield and product quality of semiconductor devices.
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Figure CN115763386B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In the epitaxial growth process of silicon wafers, a back sealing layer needs to be applied to the back of the substrate. Typically, an indium silicate (ITO) layer is applied as the back sealing layer. However, since the ITO layer is only a few hundred to a few thousand angstroms long and relatively soft, it is prone to peeling off. Therefore, a polycrystalline silicon (POLY) layer needs to be grown on top of the ITO layer to encapsulate the ITO. This process is known in the industry as the Super Sealing process.
[0003] However, during epitaxial growth, at high temperatures, dopants in the substrate can diffuse from the edges to the front side of the substrate, resulting in edge self-doping. In particular, heavily doped substrate silicon wafers are prone to inversion, which leads to low yield in semiconductor device production. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the problem of edge self-doping of substrates during epitaxial growth in existing technologies.
[0005] To achieve the above objectives, in one respect, the present invention provides a semiconductor device comprising:
[0006] Substrate;
[0007] A first silicon dioxide layer is disposed on the lower surface layer of the back side of the substrate;
[0008] A polycrystalline silicon layer is disposed on the lower surface layer of the first silicon dioxide layer;
[0009] A second silicon dioxide layer is disposed on the lower surface of the polycrystalline silicon layer and on the back chamfer and edge sides of the substrate.
[0010] The semiconductor device provided in the above embodiments includes a substrate, a first silicon dioxide layer, a polysilicon layer, and a second silicon dioxide layer. Because silicon dioxide has a high resistivity, the first silicon dioxide layer is disposed on the lower surface of the back side of the substrate, effectively isolating and protecting the substrate. Because polysilicon has high hardness, the polysilicon layer is disposed on the lower surface of the first silicon dioxide layer, effectively preventing the first silicon dioxide layer from detaching. The first silicon dioxide layer and the polysilicon layer form a super back-sealing structure, providing isolation and protection for the substrate and effectively preventing self-doping. Furthermore, since the first silicon dioxide layer and the polysilicon layer at the back chamfer and edge sides are removed after the substrate undergoes chemical mechanical polishing, this application disposes of a second silicon dioxide layer on the lower surface of the polysilicon layer and on the back chamfer and edge sides of the substrate. This adds another layer of silicon dioxide to the super back-sealing structure, achieving complete coverage of the lower surface, back chamfer, and edge sides of the substrate. Based on the three-layer back-sealing structure of the first silicon dioxide layer, the polysilicon layer, and the second silicon dioxide layer, the substrate can be effectively isolated during the epitaxial process, thereby preventing dopants from seeping out of the substrate, reducing the possibility of edge self-doping, and improving product yield.
[0011] In one embodiment, the thickness of the second silicon dioxide layer is 3,000 to 5,000 angstroms.
[0012] In one embodiment, the semiconductor device further includes an epitaxial layer disposed on the upper surface of the front side of the substrate.
[0013] In one embodiment, the conductivity of the substrate is less than that of the epitaxial layer.
[0014] On the other hand, the present invention also provides a method for fabricating a semiconductor device, the method comprising:
[0015] Provide substrate;
[0016] A first silicon dioxide layer is formed on the lower surface layer of the back side of the substrate;
[0017] A polycrystalline silicon layer is formed on the lower surface of the first silicon dioxide layer;
[0018] A second silicon dioxide layer is formed on the lower surface of the polycrystalline silicon layer and on the back chamfer and edge sides of the substrate.
[0019] The semiconductor device fabrication method provided in the above embodiments utilizes silicon dioxide, which has a high resistivity. Therefore, the first silicon dioxide layer is disposed on the lower surface of the substrate's back side, effectively isolating and protecting the substrate. Polycrystalline silicon, with its high hardness, is formed on the lower surface of the first silicon dioxide layer, effectively preventing its detachment. The first silicon dioxide layer and the polycrystalline silicon layer form a super back-sealing structure, providing isolation and protection for the substrate and effectively preventing self-doping. Furthermore, since the first silicon dioxide layer and polycrystalline silicon layer at the back chamfer and edge sides are removed after the substrate undergoes chemical mechanical polishing, this application forms a second silicon dioxide layer on the lower surface of the polycrystalline silicon layer and at the back chamfer and edge sides of the substrate. This adds another layer of silicon dioxide to the super back-sealing structure, achieving complete encapsulation of the lower surface, back chamfer, and edge sides of the substrate's back side. Based on the three-layer back-sealing structure of the first silicon dioxide layer, the polysilicon layer, and the second silicon dioxide layer, the substrate can be effectively isolated during the epitaxial process, thereby preventing dopants from seeping out of the substrate, reducing the possibility of edge self-doping, and improving product yield.
[0020] In one embodiment, the method further includes forming an epitaxial layer on the upper surface of the front side of the substrate.
[0021] In one embodiment, forming an epitaxial layer on the upper surface of the substrate includes:
[0022] An epitaxial layer with a second doping degree is formed on the upper surface of the front side of the substrate having a first doping degree, wherein the first doping degree is different from the second doping degree.
[0023] In one embodiment, after forming an epitaxial layer on the upper surface of the substrate, the method further includes removing the second silicon dioxide layer.
[0024] In one embodiment, removing the second silicon dioxide layer includes:
[0025] The second silicon dioxide layer is removed using a cleaning solution, wherein the cleaning solution includes hydrofluoric acid, SC1 cleaning solution and SC2 cleaning solution.
[0026] In one embodiment, the concentration of the hydrofluoric acid is 49%. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic cross-sectional view of the structure of a semiconductor device obtained after CMP process in one embodiment.
[0029] Figure 2 Provided in one embodiment Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device obtained after epitaxial processing.
[0030] Figure 3 This is a schematic cross-sectional view of a semiconductor device provided in one embodiment;
[0031] Figure 4 Provided in one embodiment Figure 3 A schematic diagram of the cross-sectional structure of the semiconductor device obtained after epitaxial processing.
[0032] Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor device provided in one embodiment;
[0033] Figure 6 Provided in one embodiment Figure 4 A schematic diagram of the cross-sectional structure of the semiconductor device after polishing.
[0034] Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor device provided in another embodiment;
[0035] Figure 8 Provided in one embodiment Figure 1 The resistivity data of the semiconductor device shown;
[0036] Figure 9 Provided in one embodiment Figure 3 The resistivity data of the semiconductor device shown are as follows. Detailed Implementation
[0037] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of the present invention, "a number" means at least one, such as one, two, etc., unless otherwise explicitly specified.
[0039] The terms "preferred," "more preferably," etc., used in this invention refer to embodiments of the invention that provide certain beneficial effects under certain circumstances. However, other embodiments may also be preferred under the same or other circumstances. Furthermore, the description of one or more preferred embodiments does not imply that other embodiments are unavailable, nor is it intended to exclude other embodiments from the scope of this invention.
[0040] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.
[0041] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.
[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0045] When using “including,” “having,” and “contains” as described herein, the intention is to cover non-exclusive inclusion, unless an explicit qualifying term such as “only,” “consisting of,” etc., is used, in which case another component may be added.
[0046] Unless otherwise stated, a singular term may include a plural term and should not be understood as having a quantity of one.
[0047] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the elements are shown in the drawings only as examples to facilitate understanding of the invention, but are not necessarily drawn to actual scale. The scale in the drawings does not constitute a limitation on the invention. It should be noted that when a component is referred to as "on another component," "connected to another component," "coupled to another component," or "in contact with another component," it can be directly on, connected to, coupled to, or in contact with that other component, or there may be an inserting component. In contrast, when a component is referred to as "directly on another component," "directly connected to," "directly coupled to," or "directly in contact with" another component, there is no inserting component. Similarly, when the first component is referred to as "electrically contacting" or "electrically coupling" to the second component, there is an electrical path between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between the conductive components.
[0048] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implanted regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implanted to non-implanted regions. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0049] Please see Figure 1 , Figure 1This can be understood as a cross-sectional schematic diagram of a semiconductor device structure, and the specific structure can be obtained according to the actual situation of the semiconductor device. As mentioned in the background art, a layer of silicon dioxide (ITO) 20 is first grown on the back surface 13 and the edge side 12 of the silicon substrate 10. The back surface 13 of the substrate 10 includes the lower surface layer 13a and the back chamfer 13b. Since the ITO layer is only a few hundred to a few thousand angstroms, it is relatively soft and easy to fall off. Therefore, a layer of polycrystalline silicon (POLY) 30 needs to be grown on the lower surface layer and the edge side 12 of the silicon dioxide layer 20 to wrap the ITO, forming a super back-sealed substrate. However, the inventors discovered during their work that the super back-sealed substrate, when used in epitaxial processes, exhibits edge self-doping. This is primarily because the substrate manufacturing process requires Chemical Mechanical Polishing (CMP) to remove the damaged layer on the front side of the substrate. CMP is the final step in substrate manufacturing, removing the silicon dioxide layer 20 and polysilicon layer 30 from the back chamfer 13b and edge sides 12 of substrate 10, leaving these exposed and unprotected. If, in this state, the substrate 10 continues the epitaxial process (growing the epitaxial layer 40 on the front side 11), the dopants 14 in the substrate 10 will seep out from the back chamfer 13b and / or edge sides 12 and diffuse to the front side 11 under the high-temperature environment of epitaxy. Figure 2 As shown, this alters the resistivity of the substrate 10, and the heavily doped silicon substrate 10 may even exhibit inversion. Based on this, this application provides a semiconductor device and a method for fabricating the semiconductor device.
[0050] In one embodiment, see Figure 3A semiconductor device is provided. The semiconductor device includes a substrate 110, a first silicon dioxide layer 120, a polysilicon layer 130, and a second silicon dioxide layer 150. The substrate 110 can be a heavily doped silicon wafer or a lightly doped silicon wafer. The substrate 110 can be P-type or N-type. The substrate 110 can be designed in different types according to different production requirements, and no limitation is made here. The first silicon dioxide layer (ITO) 120 is disposed on the lower surface layer 113a of the back side of the substrate 110, wherein the back side 113a of the substrate 110 includes the lower surface layer 113a and a back chamfer 113b. The polysilicon layer (POLY) 130 is disposed on the lower surface layer of the first silicon dioxide layer 120. The second silicon dioxide layer (ITO) 150 is disposed on the lower surface layer of the polysilicon layer 130, as well as the back chamfer 113b and the edge side 112 of the substrate 110. Based on this, a three-layer back-sealing structure is formed, consisting of a first silicon dioxide layer 120, a polysilicon layer 130, and a second silicon dioxide layer 150, namely ITO, POLY, and ITO. The second silicon dioxide layer 150 encapsulates both the first silicon dioxide layer 120 and the polysilicon layer 130, as well as the exposed back chamfer 113b and edge side 112 of the substrate 110, but does not encapsulate the front side 111 of the substrate 110. The front side 111 of the substrate 110 includes the upper surface layer 111a and the front chamfer 111b.
[0051] The semiconductor device provided in the above embodiments utilizes silicon dioxide, which has high resistivity and dielectric constant. Elements of Group III and V, such as boron, phosphorus, arsenic, and antimony, have very low diffusion coefficients in silicon dioxide, only 10–15 μm at 1200°C. Therefore, the first silicon dioxide layer, acting as an insulating material, is disposed on the lower surface of the substrate's back side, effectively isolating and protecting the substrate. Since polycrystalline silicon has high hardness, the polycrystalline silicon layer is disposed on the lower surface of the first silicon dioxide layer, effectively preventing the first silicon dioxide layer from easily detaching due to its lower hardness. The first silicon dioxide layer and the polycrystalline silicon layer form a super back-sealing structure, providing isolation and protection for the substrate and effectively preventing substrate self-doping. Furthermore, since the first silicon dioxide layer and polysilicon layer at the back chamfer and edge sides are removed after the substrate undergoes chemical mechanical polishing, this application forms a second silicon dioxide layer on the lower surface of the polysilicon layer and on the back chamfer and edge sides of the substrate. This adds another layer of silicon dioxide to the super back-sealing structure, achieving complete encapsulation of the lower surface, back chamfer, and edge sides of the substrate. Based on this three-layer back-sealing structure (first silicon dioxide layer, polysilicon layer, and second silicon dioxide layer), the substrate can be effectively isolated during epitaxial processes, preventing dopant leakage, reducing the possibility of edge self-doping, and improving product yield and production efficiency.
[0052] In one embodiment, the thickness of the second silicon dioxide layer 150 is 3000 to 5000 angstroms. It further encloses the back chamfer 113b and edge sidewalls 112 of the substrate 110, based on the first silicon dioxide layer 120 and the polysilicon layer 130. This effectively isolates and protects the substrate, preventing dopants in the substrate from seeping out from the edges and even diffusing to the front side, reducing edge self-doping, and thus improving product yield. For example, the thickness of the second silicon dioxide layer 110 can be 3500 to 4500 angstroms.
[0053] In one embodiment, the first silicon dioxide layer 120 and the second silicon dioxide layer 150 may have the same thickness, or they may have different thicknesses.
[0054] In one embodiment, see Figure 4 The semiconductor device also includes an epitaxial layer 140, forming an epitaxial wafer. The epitaxial layer 140 is disposed on the upper surface layer 111a of the front side of the substrate 110, excluding the front chamfer 111b of the substrate 110. Based on the semiconductor device provided above, the first silicon dioxide layer 120, the polysilicon layer 130, and the second silicon dioxide layer 150 encapsulate the lower surface layer 113a of the back side of the substrate 110, the back chamfer 113b of the substrate, and the edge side 112, effectively preventing dopants in the substrate from diffusing outwards, reducing edge self-doping, and improving product yield.
[0055] In one embodiment, the conductivity of the substrate 110 is less than the conductivity of the epitaxial layer 140. Specifically, the substrate 110 is heavily doped, and the epitaxial layer 140 is lightly doped. For example, the substrate 110 can be heavily p-type doped, and the epitaxial layer 140 can be lightly n-type doped. Similarly, the substrate 110 can be heavily n-type doped, and the epitaxial layer 140 can be lightly p-type doped.
[0056] Based on this, since the first silicon dioxide layer 120, the polysilicon layer 130, and the second silicon dioxide layer 150 cover the back side 113 and the edge side 112 of the substrate 110, the substrate 110 is effectively isolated and protected in the high-temperature environment of the subsequent epitaxial process. The diffusion coefficient of the dopants in the substrate 110 in silicon dioxide is very low, which effectively prevents the diffusion of dopants to the edge and even the front side of the substrate, reduces edge self-doping, and thus improves the product yield of semiconductor devices.
[0057] In this embodiment, the conductivity of the substrate 110 can also be greater than that of the epitaxial layer 140. Specifically, the substrate 110 is lightly doped, and the epitaxial layer 140 is heavily doped. For example, the substrate 110 can be lightly p-type doped, and the epitaxial layer 140 can be heavily n-type doped. Similarly, the substrate 110 can be lightly n-type doped, and the epitaxial layer 140 can be heavily p-type doped. The design can be customized according to product manufacturing requirements, and no limitations are imposed here.
[0058] Please see Figure 5 In one embodiment, a method for fabricating a semiconductor device is provided, including the following steps S502 to S508.
[0059] S502: Provides substrate 110.
[0060] S504: A first silicon dioxide layer 120 is formed on the lower surface layer 113a on the back side of the substrate 110.
[0061] S506: A polycrystalline silicon layer 130 is formed on the lower surface of the first silicon dioxide layer 120.
[0062] S508: A second silicon dioxide layer 150 is formed on the lower surface layer of the polysilicon layer 130 and the back chamfer 113b and edge side 112 of the substrate 110. A cross-sectional schematic diagram of a partial structure of the semiconductor device prepared based on the methods described in steps S502 to S508 above can be found in [reference needed]. Figure 3 .
[0063] The semiconductor device fabrication method provided in the above embodiments utilizes silicon dioxide, which has a high resistivity. Therefore, the first silicon dioxide layer is disposed on the lower surface of the back side of the substrate, effectively isolating and protecting the substrate. Polycrystalline silicon, with its high hardness, forms a polycrystalline silicon layer on the lower surface of the first silicon dioxide layer, effectively preventing the first silicon dioxide layer from detaching. The first silicon dioxide layer and the polycrystalline silicon layer form a super back-sealing structure, providing isolation and protection for the substrate and effectively preventing self-doping. Furthermore, since the first silicon dioxide layer and the polycrystalline silicon layer at the back chamfer and edge sides are removed after the substrate undergoes chemical mechanical polishing, this application forms a second silicon dioxide layer on the lower surface of the polycrystalline silicon layer and on the back chamfer and edge sides of the substrate. This adds another layer of silicon dioxide to the super back-sealing structure, achieving complete encapsulation of the lower surface, back chamfer, and edge sides of the substrate. Based on the three-layer back-sealing structure of the first silicon dioxide layer, the polysilicon layer, and the second silicon dioxide layer, the substrate can be effectively isolated during the epitaxial process, thereby preventing dopants from seeping out of the substrate, reducing the possibility of edge self-doping, and improving product yield and production efficiency.
[0064] In one embodiment, the method for fabricating the semiconductor device provided in the above embodiment may further include a cleaning step using SC1 cleaning solution and SC2 cleaning solution. SC1 cleaning solution includes ammonia, hydrogen peroxide, and water. SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide, and water.
[0065] The semiconductor device fabrication method provided in the above embodiments, after forming the second silicon dioxide layer, uses SC1 cleaning solution and SC2 cleaning solution to clean the semiconductor device, which can effectively remove particles on the substrate surface and avoid particles from having an adverse effect on subsequent processes.
[0066] In one embodiment, the method for fabricating the semiconductor device provided in the above embodiment may further include the step of forming an epitaxial layer 140 on the upper surface layer 111a of the front side of the substrate 110 to obtain an epitaxial wafer. A cross-sectional schematic diagram of the partial structure of the epitaxial wafer can be found in [reference needed]. Figure 4 .
[0067] The semiconductor device fabrication method provided in the above embodiments is based on a three-layer back-sealing structure consisting of a first silicon dioxide layer, a polysilicon layer, and a second silicon dioxide layer. The lower surface layer, back chamfer, and edge sides of the substrate are completely enclosed, thereby preventing dopants in the substrate from seeping outward or even diffusing to the front side of the substrate under epitaxial high-temperature conditions, reducing edge self-doping, and thus improving product yield.
[0068] In one embodiment, the above step of forming an epitaxial layer 140 on the upper surface of the substrate 110 may include: forming an epitaxial layer 140 with a second doping level on the upper surface layer 111a of the front side of the substrate 110, which has a first doping level. The first doping level and the second doping level are different. Specifically, the substrate 110 may be heavily doped or lightly doped. The epitaxial layer 140 may also be heavily doped or lightly doped. For example, the substrate 110 may be heavily p-type doped, and the epitaxial layer may be lightly n-type doped.
[0069] The semiconductor device fabrication method provided in the above embodiments can reduce edge self-doping for substrates and epitaxial layers with different doping levels, and the effect is more obvious for products with heavily doped substrates and lightly doped epitaxial layers.
[0070] In one embodiment, the method for fabricating the semiconductor device provided in the above embodiment may further include a step of removing the second silicon dioxide layer 150 after forming the epitaxial layer 140 on the upper surface layer 111a of the substrate 110. A cross-sectional schematic diagram of the semiconductor device structure after removing the second silicon dioxide layer 150 can be found in [reference needed]. Figure 6 .
[0071] The semiconductor device fabrication method provided in the above embodiments removes the second silicon dioxide layer after the semiconductor device has formed an epitaxial layer through an epitaxial process. This avoids the adverse effects of the second silicon dioxide layer on subsequent processes, thereby improving the product yield.
[0072] In one embodiment, the above step of removing the second silicon dioxide layer 150 may include: removing the second silicon dioxide layer 150 using a cleaning solution. The cleaning solution includes hydrofluoric acid, SC1 cleaning solution, and SC2 cleaning solution. SC1 cleaning solution includes ammonia, hydrogen peroxide, and water. SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide, and water.
[0073] In one embodiment, the concentration of hydrofluoric acid is 49%.
[0074] The semiconductor device fabrication method provided in the above embodiments removes the second silicon dioxide layer using a cleaning solution after the semiconductor device has formed an epitaxial layer through an epitaxial process. This avoids the adverse effects of the second silicon dioxide layer on subsequent processes, thereby improving the product yield.
[0075] To better understand, combine Figure 7 The semiconductor devices and their fabrication methods provided in the above embodiments will be described. For example... Figure 7 As shown, the method for fabricating a semiconductor device includes the following steps S702-S714.
[0076] S702: Provides substrate 110. Specifically, substrate 110 is a heavily doped silicon wafer substrate.
[0077] S704: A first silicon dioxide layer 120 is formed on the lower surface layer 113a on the back side of the substrate 110.
[0078] S706: A polycrystalline silicon layer 130 is formed on the lower surface of the first silicon dioxide layer 120.
[0079] S708: A second silicon dioxide layer 150 is formed on the lower surface layer of the polysilicon layer 130 and on the back chamfer 113b and edge side 112 of the substrate 110. Specifically, the thickness of the second silicon dioxide layer 150 is 3500 angstroms to 4500 angstroms. Based on this, a cross-sectional schematic diagram of a portion of the structure of the fabricated semiconductor device can be found in [reference needed]. Figure 3 .
[0080] S710: Cleaning is performed using SC1 and SC2 cleaning solutions. Specifically, SC1 cleaning solution includes ammonia, hydrogen peroxide, and water. SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide, and water.
[0081] S712: An epitaxial layer 140 with a second doping level is formed on the upper surface layer 111a of the substrate 110 with a first doping level. Based on this, a cross-sectional schematic diagram of the partial structure of the semiconductor device can be found in [reference needed]. Figure 4 .
[0082] S714: Remove the second silicon dioxide layer 150 using a cleaning solution. Specifically, the cleaning solution includes 49% hydrofluoric acid, SC1 cleaning solution, and SC2 cleaning solution. SC1 cleaning solution includes ammonia, hydrogen peroxide, and water. SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide, and water. Based on this, a cross-sectional schematic diagram of the fabricated semiconductor device structure can be found in [reference needed]. Figure 6 .
[0083] Please see Figure 8 and Figure 9 ,in, Figure 8 for Figure 1 The resistivity data of the silicon wafer after the epitaxial process of the semiconductor device shown are obtained after the process control monitor (PCM) test. Figure 9 Provided for the embodiments of this application as follows Figure 7 The semiconductor device fabrication method shown includes resistivity data after PCM testing. A resistivity exceeding 8.5 indicates compliance, exceeding 8 but less than 8.5 indicates within acceptable limits, and less than 8 indicates exceeding specifications. (Comparison) Figure 8 and Figure 9 It can be seen that adding a second silicon dioxide layer to the super back-sealing substrate before epitaxy effectively reduces edge self-doping.
[0084] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.
[0085] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0087] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A first silicon dioxide layer is disposed on the lower surface layer of the back side of the substrate; A polycrystalline silicon layer is disposed on the lower surface layer of the first silicon dioxide layer; after the substrate undergoes a chemical mechanical polishing process, the first silicon dioxide layer and the polycrystalline silicon layer at the back chamfer and edge sides of the substrate are removed; The second silicon dioxide layer is disposed on the lower surface of the polycrystalline silicon layer and on the back chamfer and edge side of the substrate; the second silicon dioxide layer encapsulates the first silicon dioxide layer and the polycrystalline silicon layer, and also encapsulates the back chamfer and edge side of the exposed substrate.
2. The semiconductor device according to claim 1, characterized in that, The thickness of the second silicon dioxide layer is 3,000 to 5,000 angstroms.
3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An epitaxial layer is disposed on the upper surface of the front side of the substrate.
4. The semiconductor device according to claim 3, characterized in that, The electrical conductivity of the substrate is less than that of the epitaxial layer.
5. A method for fabricating a semiconductor device, characterized in that, The method includes: Provide substrate; A first silicon dioxide layer is formed on the lower surface layer of the back side of the substrate; A polycrystalline silicon layer is formed on the lower surface of the first silicon dioxide layer; after the substrate undergoes a chemical mechanical polishing process, the first silicon dioxide layer and the polycrystalline silicon layer at the back chamfer and edge sides of the substrate are removed; A second silicon dioxide layer is formed on the lower surface of the polycrystalline silicon layer and on the back chamfer and edge side of the substrate; the second silicon dioxide layer encapsulates the first silicon dioxide layer and the polycrystalline silicon layer, and also encapsulates the back chamfer and edge side of the exposed substrate.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The method further includes: An epitaxial layer is formed on the upper surface of the front side of the substrate.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The formation of an epitaxial layer on the upper surface of the front side of the substrate includes: An epitaxial layer with a second doping degree is formed on the upper surface of the front side of the substrate having a first doping degree, wherein the first doping degree is different from the second doping degree.
8. The method for fabricating a semiconductor device according to claim 6, characterized in that, After forming an epitaxial layer on the upper surface of the substrate, the method further includes: Remove the second silicon dioxide layer.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The removal of the second silicon dioxide layer includes: The second silicon dioxide layer is removed using a cleaning solution, wherein the cleaning solution includes hydrofluoric acid, SC1 cleaning solution and SC2 cleaning solution.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The concentration of the hydrofluoric acid is 49%.