Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method for manufacturing the same. The semiconductor element includes a substrate, a first bit line structure disposed above the substrate, including a first line portion arranged in parallel with a first direction, and a second line portion connected to a first end of the first line portion and arranged in parallel with a second direction perpendicular to the first direction, a first bit line top contact region including a first strip portion disposed on the first end of the first line portion and arranged in parallel with the first direction, and a second strip portion connected to a first end of the first strip portion and disposed on the second line portion and arranged in parallel with the second direction, and a first top conductive layer electrically coupled to the first bit line top contact region.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 17 / 466,102, filed September 3, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for fabricating the semiconductor element, and particularly to a semiconductor element having a bit line contact region and a method for fabricating the semiconductor element. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems have arisen during this shrinking process, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate, a first element line structure, a first element line top contact region, and a first top conductive layer. The first element line structure is disposed above the substrate and includes a first line portion arranged parallel to a first direction, and a second line portion connected to a first end of the first line portion and arranged parallel to a second direction perpendicular to the first direction. The first element line top contact region includes a first strip portion disposed on the first end of the first line portion and arranged parallel to the first direction, and a second strip portion connected to a first end of the first strip portion, disposed on the second line portion, and arranged parallel to the second direction. The first top conductive layer is electrically coupled to the first element line top contact region.

[0006] In some embodiments, the semiconductor device includes a source region disposed in the substrate. The first line portion of the first element line structure is electrically coupled to the source region.

[0007] In some embodiments, the semiconductor element includes a second bit line structure disposed at the same vertical height as the first bit line structure, and includes a first bit line portion arranged parallel to the first bit line portion of the first bit line structure, and including a first end and a second end; and a second bit line portion connected to the second end of the first bit line portion of the second bit line structure, arranged parallel to the second bit line portion of the first bit line structure, and positioned toward the first bit line portion of the first bit line structure. The first end of the first bit line portion of the second bit line structure is positioned toward the second bit line portion of the first bit line structure, and the second end of the first bit line portion of the second bit line structure is opposite to the first end of the first bit line portion of the second bit line structure.

[0008] In some embodiments, the semiconductor element includes a second bit line top contact region disposed at the same vertical height as the first bit line top contact region, and includes a first strip portion arranged parallel to the first direction, disposed on the second end of the first line portion of the second bit line structure, and including a first end and a second end; and a second strip portion connected to the second end of the first strip portion of the second bit line top contact region, disposed on the second line portion of the second bit line structure, and arranged parallel to the second line portion of the first bit line structure. The first end of the first strip portion of the second bit line top contact region is positioned toward the second strip portion of the first bit line top contact region, and the second end of the first strip portion of the second bit line top contact region is opposite to the first end of the first strip portion of the second bit line top contact region.

[0009] In some embodiments, the semiconductor device includes a second top conductive layer for electrical coupling with the top contact region of the second bit line.

[0010] In some embodiments, the semiconductor element includes a third line portion connected to the second line portion of the first bit line structure, aligned with the first line portion of the second bit line structure, and positioned toward the first line portion of the second bit line structure.

[0011] In some embodiments, the semiconductor element includes a third portion connected to the second portion of the first element line top contact area and disposed on the third portion of the first element line structure.

[0012] In some embodiments, the semiconductor element includes a third line portion connected to the second line portion of the second bit line structure, aligned with the first line portion of the first bit line structure, and positioned toward the first line portion of the first bit line structure.

[0013] In some embodiments, the semiconductor element includes a third stripe that is connected to the second stripe of the second bit line top contact region and is disposed on the third stripe of the second bit line structure.

[0014] In some embodiments, the width of the first strip portion of the first element line top contact area is greater than the width of the first line portion of the first element line structure.

[0015] In some embodiments, the width of the second strip portion of the first element line top contact area is greater than the width of the second line portion of the first element line structure.

[0016] In some embodiments, the third line portion of the first element line structure is completely covered by the third strip portion of the top contact area of ​​the first element line when viewed from a top angle.

[0017] In some embodiments, the width of the first strip portion of the top contact area of ​​the second bit line is greater than the width of the first line portion of the second bit line structure.

[0018] In some embodiments, the width of the second strip portion of the top contact area of ​​the second bit line is greater than the width of the second line portion of the second bit line structure.

[0019] In some embodiments, the third line portion of the second bit line structure is completely covered by the third strip portion of the top contact area of ​​the second bit line.

[0020] In some embodiments, the length of the second line portion of the first bit line structure is less than or equal to a distance between the first line portion of the first bit line structure and the first line portion of the second bit line structure.

[0021] In some embodiments, the length of the second portion of the first element line top contact area is equal to or less than the length of the first portion of the first element line top contact area.

[0022] In some embodiments, the length of the second portion of the first element line top contact area is greater than the length of the first portion of the first element line top contact area.

[0023] In some embodiments, the length of the second portion of the first element line top contact area is greater than or equal to the length of the second portion of the first element line structure.

[0024] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first element line structure on the substrate, including a first line portion arranged parallel to the first direction, and a second line portion connected to a first end of the first line portion and arranged parallel to a second direction perpendicular to the first direction; forming a first element line top contact region, including a first strip portion disposed on the first end of the first line portion and arranged parallel to the first direction, and a second strip portion connected to a first end of the first strip portion, disposed on the second line portion and arranged parallel to the second direction; and forming a first top conductive layer for electrically coupling with the first element line top contact region.

[0025] Due to the design of the semiconductor device disclosed herein, the contact area between the first bit line structure and the first bit line top contact area, and between the second bit line structure and the second bit line top contact area, can be larger. Therefore, the contact area resistance between the first bit line structure and the first bit line top contact area, and between the second bit line structure and the second bit line top contact area, can be reduced. Thus, the performance of the semiconductor device can be improved.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Attached Figure Description

[0027] A more comprehensive understanding of the disclosure of this invention can be obtained by referring to the drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 2 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 It is along Figure 2 A cross-sectional view taken along line A-A'.

[0031] Figure 4 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 5 It is along Figure 4 A cross-sectional view taken along line A-A'.

[0033] Figure 6 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] Figure 7 It is along Figure 6 A cross-sectional view taken along line A-A'.

[0035] Figure 8 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0036] Figure 9 It is along Figure 8 A cross-sectional view taken along line A-A'.

[0037] Figure 10 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0038] Figure 11 yes Figure 10 A cross-sectional view taken along line A-A'.

[0039] Figure 12 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0040] Figure 13 It is along Figure 12 A cross-sectional view taken along line A-A'.

[0041] Figure 14 It is along Figure 12 A cross-sectional view taken along line B-B'.

[0042] Figure 15 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0043] Figure 16 It is along Figure 15 A cross-sectional view taken along line A-A'.

[0044] Figure 17 It is along Figure 15 A cross-sectional view taken along line B-B'.

[0045] Figure 18 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0046] Figure 19 It is along Figure 18 A cross-sectional view taken along line A-A'.

[0047] Figure 20 It is along Figure 18 A cross-sectional view taken along line B-B'.

[0048] Figure 21 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0049] Figure 22 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0050] Figure 23 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0051] Figure 24 It is along Figure 23 A cross-sectional view taken along line A-A'.

[0052] Figure 25 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0053] Figure 26 It is along Figure 25 A cross-sectional view taken along line A-A'.

[0054] Figure 27 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0055] Figure 28 It is along Figure 27 A cross-sectional view taken along line A-A'.

[0056] Figure 29 It is along Figure 27 A cross-sectional view taken along line B-B'.

[0057] Figure 30 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0058] Figure 31 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0059] Figure 32 This is a top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0060] The reference numerals in the attached figures are explained as follows:

[0061] 1A: Semiconductor components

[0062] 1B: Semiconductor components

[0063] 10: Preparation method

[0064] 110: First element line structure

[0065] 110-1: First Line Unit

[0066] 110-3: Second Line Section

[0067] 110-5: Third Line Section

[0068] 111: The bottom of the first element line

[0069] 113: Top of the first element line

[0070] 115: First element line capping layer

[0071] 120: Second-bit line structure

[0072] 120-1: First Line Unit

[0073] 120-3: Second Line Section

[0074] 120-5: Third Line Section

[0075] 121: Second-level bottom line

[0076] 123: Top layer of the second bit line

[0077] 125: Second bit line capping layer

[0078] 131: Bottom contact area of ​​bit line

[0079] 133: Bit line gap

[0080] 210: First Yuan Line Top Touch Zone

[0081] 210-1: First Section

[0082] 210-3: Section Two

[0083] 210-5: Section Three

[0084] 220: Second bit line top touch zone

[0085] 220-1: First Section

[0086] 220-3: Section Two

[0087] 220-5: Article 3

[0088] 301: Base

[0089] 303: Isolation layer

[0090] 305: Active Zone

[0091] 307: Drain region

[0092] 309: Source Region

[0093] 311: First dielectric layer

[0094] 313: Second dielectric layer

[0095] 315: Third dielectric layer

[0096] 317: Fourth dielectric layer

[0097] 319: Fifth dielectric layer

[0098] 321: Top conductive layer

[0099] 330: Character Line

[0100] 331: Character line dielectric layer

[0101] 333: Character line conductive layer

[0102] 335: Character line fill layer

[0103] 337: Character line capping

[0104] 340: Capacitor Structure

[0105] 341: Conductive layer at the bottom of the capacitor

[0106] 343: Capacitor dielectric layer

[0107] 345: Conductive layer on top of capacitor

[0108] 351: Capacitor contact area

[0109] 401: Impurity layer

[0110] 403: First conductive material layer

[0111] 405: Second conductive material layer

[0112] 407: First insulating material layer

[0113] 501: Pre-position line structure

[0114] D1: Distance

[0115] G1: First gap

[0116] G2: Second gap

[0117] L1: Length

[0118] L2: Length

[0119] L3: Length

[0120] L4: Length

[0121] L5: Length

[0122] L6: Length

[0123] L7: Length

[0124] L8: Length

[0125] L9: Length

[0126] L10: Length

[0127] L11: Length

[0128] L12: Length

[0129] M1: First masking layer

[0130] M2: Second masking layer

[0131] OP1: First opening

[0132] S11: Steps

[0133] S13: Steps

[0134] S15: Steps

[0135] S17: Steps

[0136] S19: Steps

[0137] TR1: Character slot

[0138] W1: Width

[0139] W2: Width

[0140] W3: Width

[0141] W4: Width

[0142] W5: Width

[0143] W6: Width

[0144] W7: Width

[0145] W8: Width

[0146] W9: Width

[0147] W10: Width

[0148] W11: Width

[0149] W12: Width

[0150] X: Direction

[0151] Y: direction

[0152] Z: Direction Detailed Implementation

[0153] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0154] Terms such as "an embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0155] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description below of a first feature being formed "on" or "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0156] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figure but also different orientations of the element during use or operation. The element may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be translated accordingly.

[0157] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be intermediate components or layers.

[0158] In this disclosure, semiconductor components generally refer to components that function by utilizing the properties of semiconductors. Electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the scope of semiconductor components.

[0159] In this disclosure, "above" and "up" correspond to the direction of the arrow in direction Z, and "below" and "down" correspond to the opposite direction of the arrow in direction Z.

[0160] Figure 1 A method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure is illustrated in the form of a flowchart. Figure 2 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line A-A'. Figure 4 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line A-A'. Figure 6 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line A-A'.

[0161] Reference Figures 1 to 7 In step S11, a substrate 301 can be provided, an isolation layer 303 can be formed in the substrate 301 to define a plurality of active regions 305, a plurality of impurity layers 401 can be formed in the plurality of active regions 305, and a plurality of word line slots TR1 can be formed in the substrate 301 to transform the plurality of impurity layers 401 into a plurality of drain regions 307 and a plurality of source regions 309.

[0162] Reference Figure 2 and Figure 3The substrate 301 may include a silicon-containing material. Suitable silicon-containing materials for the substrate 301 may include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, silicon germanium carbide, carbon-doped silicon, silicon carbide, or multilayer materials of combinations thereof. Although silicon is the primary semiconductor material used in wafer fabrication, in some embodiments, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, and germanium tin.

[0163] In some embodiments, substrate 301 may include a semiconductor-on-insulator (SOI) structure comprising, from bottom to top, a processing substrate, an insulating layer, and an uppermost semiconductor material layer. The processing substrate and the uppermost semiconductor material layer may be fabricated using the same material, such as bulk silicon, or other suitable semiconductor materials. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The thickness of the insulating layer may range from 10 nanometers (nm) to 200 nanometers.

[0164] Reference Figure 2 and Figure 3A series of deposition processes can be performed to deposit a pad oxide layer (not shown for clarity) and a pad nitride layer (not shown for clarity) on the substrate 301. A photolithography process can be performed to define the location of the isolation layer 303. After the photolithography process, an etching process, such as anisotropic dry etch, can be performed to form trenches penetrating the oxide layer, the pad nitride layer, and the substrate 301. An insulating material can be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, can then be performed to remove excess filler material until the substrate 301 is exposed. The insulating material can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof.

[0165] Reference Figure 2 and Figure 3 The isolation layer 303 can define the positions of multiple active regions 305. For simplicity, clarity, and ease of description, only one active region 305 is described. The active region 305 may include a portion of the substrate 301 and the space above that portion of the substrate 301. Describing an element as disposed on the active region 305 means that the element is disposed on the top surface of that portion of the substrate 301. Describing an element as disposed within the active region 305 means that the element is disposed within that portion of the substrate 301; however, the top surface of the element may be flush with the top surface of that portion of the substrate 301. Describing an element as disposed above the active region 305 means that the element is disposed above the top surface of that portion of the substrate 301. In a top-down view, the active regions 305 may be arranged parallel to directions inclined to both the X and Y directions.

[0166] Reference Figure 4 and Figure 5Multiple impurity layers 401 can be formed, respectively, in multiple active regions 305. For simplicity, clarity, and ease of description, only one impurity layer 401 is described. The impurity layer 401 can be formed in the substrate 301. The top surface of the impurity layer 401 can be substantially coplanar with the top surface of the substrate 301. The impurity layer 401 can be fabricated using n-type or p-type impurity implantation processes. The n-type impurity implantation process adds impurities that contribute free electrons to the intrinsic semiconductor. In silicon-containing substrates, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, or phosphorus. The p-type impurity implantation process adds impurities to the intrinsic semiconductor, thus creating a deficiency of valence electrons. In silicon-containing substrates, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, or indium. The dopant concentration of the impurity layer 401 can be in the range of approximately 1E17 atoms / cm^3 to approximately 1E18 atoms / cm^3.

[0167] In some embodiments, an annealing process can be performed to initiate the impurity layer 401. The process temperature of the annealing process can range from approximately 800°C to approximately 1250°C. The process duration of the annealing process can range from approximately 1 millisecond (ms) to approximately 500 ms. The annealing process can be, for example, rapid thermal annealing, laser spike annealing, or flash lamp annealing.

[0168] It should be understood that, in the description of this disclosure, the surface of an element (or feature) at its highest vertical height along the Z direction is referred to as the top surface of the element (or feature). The surface of an element (or feature) at its lowest vertical height along the Z direction is referred to as the bottom surface of the element (or feature).

[0169] Reference Figure 6 and Figure 7 A first masking layer M1 can be formed on the substrate 301. A photolithography process can be performed to define the positions of multiple character slots TR1. An etching process, such as anisotropic dry etching, can be performed to remove the substrate 301, the isolation layer 303, and the impurity layer 401, while simultaneously forming the multiple character slots TR1. The multiple character slots TR1 can be arranged parallel to the Y direction. The bottom surface of the multiple character slots TR1 can be a vertical height above the bottom surface of the isolation layer 303. Each active region 305 can be traversed by two character slots TR1. The two character slots TR1 divide the impurity layer 401 into two drain regions 307 and a source region 309 located between the two drain regions 307.

[0170] Figure 8An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated by forming a schematic top view. Figure 9 It is along Figure 8 A schematic cross-sectional view taken along line A-A'.

[0171] Reference Figure 1 , Figure 8 and Figure 9 In step S13, multiple character lines 330 can be formed in the multiple character line slots TR1.

[0172] For the sake of brevity, clarity, and ease of description, only one character line 330 will be described.

[0173] Reference Figure 8 and Figure 9 The character line 330 can be formed in the character line slot TR1. In other words, the character line 330 can be arranged parallel to the Y direction. The character line 330 may include a character line dielectric layer 331, a character line conductive layer 333, a character line fill layer 335, and a character line capping layer 337.

[0174] An insulating layer may be conformally formed on the first masking layer M1 and in the plurality of character line slots TR1, and the insulating layer will subsequently become the character line dielectric layer 331. The thickness of the insulating layer may be in the range of about 0.5 nanometers to about 5.0 nanometers. In some embodiments, the thickness of the insulating layer may be in the range of about 0.5 nanometers to about 2.5 nanometers. The insulating layer may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and high-k materials, such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal nitrides, transition metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, or combinations thereof.

[0175] In some embodiments, the high dielectric constant material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or combinations thereof.

[0176] A conductive layer can be conformally formed on the insulating layer, which will later become the character line conductive layer 333. The thickness of the conductive layer can range from about 10 angstroms to about 200 angstroms. The conductive layer may include, for example, one or more conductive metal nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)).

[0177] Techniques for fabricating insulating and conductive layers can include, for example, atomic layer deposition (ALD). In ALD, under predetermined process conditions, two (or more) different source gases are alternately supplied to the workpiece, causing chemical species to be adsorbed onto the workpiece at the atomic layer level and deposited onto the workpiece through surface reactions. For example, first and second source gases are alternately supplied to the workpiece, flowing along its surface, causing molecules in the first source gas to adsorb onto the surface. Molecules in the second source gas then react with the adsorbed molecules from the first source gas, forming a monolayer film. These process steps are repeated, thus forming a high-quality dielectric or conductive film on the workpiece.

[0178] Conductive materials such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), or aluminum can be deposited to completely fill the character line slot TR1. Subsequently, an etch-back process can be performed to remove a portion of the conductive material and conductive layer. After the etch-back process, the remaining conductive material can be referred to as the character line filling layer 335. The remaining conductive layer can be referred to as the character line conductive layer 333. The insulating layer can be referred to as the character line dielectric layer 331.

[0179] In some embodiments, the word line dielectric layer 331 and the word line conductive layer 333 may have a U-shaped cross-sectional profile. Having a U-shaped cross-sectional profile helps avoid corner effects. In some embodiments, the bottom surface of the word line dielectric layer 331 may be flat. In some embodiments, the bottom surface of the word line dielectric layer 331 may be circular to reduce defect density and electric field concentration during operation of the semiconductor device 1A. The word line dielectric layer 331 can prevent junction leakage and prevent dopants from the drain region 307 and source region 309 from migrating into the word line conductive layer 333 and the word line fill layer 335.

[0180] In some embodiments, the top surface of the character line filling layer 335 and the top surface of the character line conductive layer 333 may be substantially coplanar. In some embodiments, the top surface of the character line filling layer 335 may be lower than the vertical height of the top surface of the character line dielectric layer 331.

[0181] Next, a capping material can be deposited to fill the character line slot TR1. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the isolation layer 303 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the character line capping layer 337. The material used to fabricate the character line capping layer 337 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or a high dielectric constant material.

[0182] Figure 10 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 11 It is along Figure 10 A schematic cross-sectional view taken along line A-A'. Figure 12 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 13 It is along Figure 12 A schematic cross-sectional view taken along line A-A'. Figure 14 It is along Figure 12 A schematic cross-sectional view taken along line B-B'. Figure 15 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 16 It is along Figure 15 A schematic cross-sectional view taken along line A-A'. Figure 17 It is along Figure 15 A schematic cross-sectional view taken along line B-B'. Figure 18 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 19 It is along Figure 18 A schematic cross-sectional view taken along line A-A'. Figure 20 It is along Figure 18 A schematic cross-sectional view taken along line B-B'. Figure 21 and Figure 22 A portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure is illustrated in a schematic cross-sectional view.

[0183] Reference Figure 1 and Figures 10 to 22 In step S15, a first bit line structure 110 and a second bit line structure 120 can be formed to electrically couple to multiple source regions 309.

[0184] Reference Figure 10 and Figure 11 The first dielectric layer 311 can be Figure 8 and Figure 9 Blanket deposition is performed on the intermediate semiconductor device shown. In some embodiments, the first dielectric layer 311 may be an etch stop layer. Generally, an etch stop layer provides a mechanism to stop the etching process during the formation of vias and / or contacts. The preferred fabrication technique for the etch stop layer is by using a dielectric material having a different etch selectivity than adjacent layers. In some embodiments, the etch stop layer may be fabricated using silicon nitride, silicon carbonitride, silicon oxycarbon, combinations thereof, or similar materials. The first dielectric layer 311 may be fabricated using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition techniques.

[0185] Reference Figure 10 and Figure 11Multiple first openings OP1 can be formed in the first dielectric layer 311 to expose multiple source regions 309. The multiple first openings OP1 can be fabricated by a photolithography process followed by an etching process. In some embodiments, the sidewalls of the multiple first openings OP1 can be substantially vertical. In some embodiments, the sidewalls of the multiple first openings OP1 can be tapered.

[0186] Reference Figures 12 to 14 The first conductive material layer 403, the second conductive material layer 405, the first insulating material layer 407, and the second shielding layer M2 can be sequentially formed on... Figure 10 and Figure 11 On the intermediate semiconductor element shown, a first conductive material layer 403 can completely fill a plurality of first openings OP1. The first conductive material 403 filled in the plurality of first openings OP1 can be referred to as a plurality of bit-line bottom contact regions 131. The first conductive material 403 can be, for example, a doped semiconductor material (e.g., doped silicon or doped germanium), a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The second conductive material 405 can be, for example, a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0187] In some embodiments, a barrier layer (not shown) may be formed between the first conductive material layer 403 and the second conductive material layer 405. The barrier layer may include, for example, titanium nitride, titanium silicon nitride, tantalum nitride, tantalum silicon nitride, or combinations thereof. The thickness of the barrier layer may range from approximately 10 angstroms to approximately 15 angstroms. In some embodiments, the thickness of the barrier layer may range from approximately 11 angstroms to approximately 13 angstroms.

[0188] The first insulating material layer 407 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. In some embodiments, the second masking layer M2 may be a photoresist layer. Viewed from above, the second masking layer M2 may have a hollow rectangular pattern. The second masking layer M2 may be horizontally aligned parallel to the X-direction and may pass through all of the multiple character lines 330 simultaneously.

[0189] Reference Figures 15 to 17An etching process, such as anisotropic dry etching, can be performed to remove a portion of the first insulating material layer 407, the second conductive material layer 405, and the first conductive material layer 403, while simultaneously forming a pre-bit line structure 501. In a top-view perspective, the pre-bit line structure 501 can have a hollow rectangular outline. The pre-bit line structure 501 can be arranged horizontally parallel to the X-direction and can simultaneously pass through all the multiple character lines 330.

[0190] Reference Figures 18 to 20 A photolithography process using a photoresist layer can be performed to define the pattern of the first bit line structure 110 and the second bit line structure 120. An etching process, such as anisotropic dry etching, can be performed to remove a portion of the pre-defined bit line structure 501 and simultaneously form the first bit line structure 110 and the second bit line structure 120.

[0191] Reference Figures 18 to 20 The first element line structure 110 may include a first line portion 110-1, a second line portion 110-3, and a third line portion 110-5 when viewed from above. In some embodiments, the first element line structure 110 may include only the first line portion 110-1 and the second line portion 110-3 when viewed from above.

[0192] The first line portion 110-1 can be arranged parallel to the X direction. Some bit line bottom contact areas 131 can overlap with the first line portion 110-1 and can be electrically coupled to the first line portion 110-1. In other words, the bit line bottom contact areas 131 can be directly disposed below the first line portion 110-1. The first line portion 110-1 can be linear in shape when viewed from a top angle and can include a first end (e.g., Figure 18 The left end) and the second end opposite the first end (e.g., Figure 18 The second line portion 110-3 can be connected to the first end of the first line portion 110-1 and arranged parallel to the Y direction. The second line portion 110-3 can be linear in plan view and can include two ends, such as a lower end and an upper end. The lower end of the second line portion 110-3 is connected to the first line portion 110-1. The third line portion 110-5 can be connected to the upper end of the second line portion 110-3, arranged parallel to the X direction, and positioned towards the first line portion 120-1. In other words, the third line portion 110-5 can be arranged parallel to the first line portion 110-1. The third line portion 110-5 can be relatively far from the second bit line structure 120, with a first gap G1 between them.

[0193] In some embodiments, the length L1 of the first thread portion 110-1 may be greater than or equal to the length L2 of the second thread portion 110-3. In some embodiments, the length L1 of the first thread portion 110-1 may be less than the length L2 of the second thread portion 110-3. In some embodiments, the length L2 of the second thread portion 110-3 may be greater than or equal to the length L3 of the third thread portion 110-5. In some embodiments, the length L2 of the second thread portion 110-3 may be less than the length L3 of the third thread portion 110-5.

[0194] In some embodiments, the widths W1 of the first line portion 110-1, W2 of the second line portion 110-3, and W3 of the third line portion 110-5 may all be the same. In some embodiments, the widths W1 of the first line portion 110-1, W2 of the second line portion 110-3, and W3 of the third line portion 110-5 may all be different.

[0195] The first bit line structure 110, in cross-section, may include a first bit line bottom layer 111, a first bit line top layer 113, and a first bit line capping layer 115. The first bit line bottom layer 111 may be replaced by a first conductive material layer 403 and may be disposed on some bit line bottom contact areas 131. The first bit line top layer 113 may be replaced by a second conductive material layer 405 and may be disposed on the first bit line bottom layer 111. The first bit line capping layer 115 may be replaced by a first insulating material layer 407 and may be disposed on the first bit line top layer 113. In some embodiments, the first bit line structure 110 may only include the first bit line bottom layer 111 and the first bit line top layer 113.

[0196] Reference Figures 18 to 20 The second bit line structure 120, viewed from a top angle, may include a first line portion 120-1, a second line portion 120-3, and a third line portion 120-5. In some embodiments, the second bit line structure 120 may include only the first line portion 120-1 and the second line portion 120-3.

[0197] The first line portion 120-1 may be arranged parallel to the X direction. In some embodiments, the first line portion 120-1 and the first line portion 110-1 are arranged parallel to each other. Some bit line bottom contact areas 131 may overlap with the first line portion 120-1 and may be electrically coupled to the first line portion 120-1. In other words, the bit line bottom contact areas 131 may be directly disposed below the first line portion 120-1. The first line portion 120-1 may be linear in shape when viewed from a top angle and may include a first end (e.g., Figure 18 The left end) and the second end opposite the first end (e.g., Figure 18The second line portion 120-3 can be connected to the second end of the first line portion 120-1 and arranged parallel to the Y direction. The second line portion 120-3 can be linear in plan view and may include two ends, such as a lower end and an upper end. The upper end of the second line portion 120-3 is connected to the first line portion 120-1. The third line portion 120-5 can be connected to the lower end of the second line portion 120-3, arranged parallel to the X direction, and positioned towards the first line portion 110-1. In other words, the third line portion 120-5 can be arranged parallel to the first line portion 120-1. The third line portion 120-5 can be relatively far from the first element line structure 110, with a second gap G2 between them.

[0198] In some embodiments, the length L4 of the first line portion 120-1 may be greater than or equal to the length L5 of the second line portion 120-3. In some embodiments, the length L4 of the first line portion 120-1 may be less than the length L5 of the second line portion 120-3. In some embodiments, the length L5 of the second line portion 120-3 may be greater than or equal to the length L6 of the third line portion 120-5. In some embodiments, the length L5 of the second line portion 120-3 may be less than the length L6 of the third line portion 120-5. In some embodiments, the length L2 of the second line portion 110-3 or the length L5 of the second line portion 120-3 may be less than the distance D1 between the first line portion 110-1 and the first line portion 120-1.

[0199] In some embodiments, the widths W4 of the first line portion 120-1, W5 of the second line portion 120-3, and W6 of the third line portion 120-5 can all be the same. In some embodiments, the widths W4 of the first line portion 120-1, W5 of the second line portion 120-3, and W6 of the third line portion 120-5 can all be different.

[0200] The second bitline structure 120, in cross-sectional view, may include a second bitline bottom layer 121, a second bitline top layer 123, and a second bitline capping layer 125. The second bitline bottom layer 121 may be replaced by a first conductive material layer 403 and may be disposed on some bitline bottom contact areas 131. The second bitline top layer 123 may be replaced by a second conductive material layer 405 and may be disposed on the second bitline bottom layer 121. The second bitline capping layer 125 may be replaced by a first insulating material layer 407 and may be disposed on the second bitline top layer 123. In some embodiments, the second bitline structure 120 may only include the second bitline bottom layer 121 and the second bitline top layer 123.

[0201] Reference Figure 21 and Figure 22 , can Figures 18 to 20An insulating material is conformally formed on the intermediate semiconductor element shown. An etching process, such as anisotropic dry etching, can be performed to remove a portion of the insulating material and simultaneously form a plurality of bit-line spacers 133 on the sidewalls of the first bit-line structure 110 and the second bit-line structure 120. The insulating material can be, for example, silicon nitride, silicon boron carbide, silicon oxy-carbon nitride, silicon carbonitride, silicon carbide oxide, or similar materials. In some embodiments, the bit-line spacers 133 may be optional.

[0202] Reference Figure 21 and Figure 22 A second dielectric layer 313 can be formed to cover the first bit line structure 110, the second bit line structure 120, and the plurality of bit line spacers 133. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially planar surface for subsequent process steps. In some embodiments, the fabrication technique for the second dielectric layer 313 can be, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k materials, or combinations thereof. The dielectric constant of the low-k material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k material can be less than 2.0. The fabrication technique for the second dielectric layer 313 can be by deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes.

[0203] Figure 23 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 24 It is along Figure 23 A cross-sectional view taken along line A-A'. Figure 25 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 26 It is along Figure 25 A schematic cross-sectional view taken along line A-A'.

[0204] Reference Figure 1 and Figures 23 to 26 In step S17, multiple capacitor contact regions 351 can be formed to be electrically coupled to multiple drain regions 307, and multiple capacitor structures 340 can be formed to be electrically coupled to multiple capacitor contact regions 351.

[0205] Reference Figure 23 and Figure 24 Multiple capacitor contact regions 351 may be formed along the second dielectric layer 313 and the first dielectric layer 311 and multiple drain regions 307. The multiple capacitor contact regions 351 may include, for example, one or more of conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metals (e.g., titanium, tantalum, tungsten, copper or aluminum).

[0206] Reference Figure 25 and Figure 26 The third dielectric layer 315 can be formed on the second dielectric layer 313. In some embodiments, the fabrication technology of the third dielectric layer 315 can be, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material can be less than 2.0. The fabrication technology of the third dielectric layer 315 can be achieved by deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes.

[0207] Reference Figure 25 and 26 Multiple capacitor structures 340 may be formed respectively and correspondingly on the third dielectric layer 315 and multiple capacitor contact regions 351. For the sake of brevity, clarity and convenience, only one capacitor structure 340 is described. The capacitor structure 340 may include a bottom conductive layer 341, a dielectric layer 343, and a top conductive layer 345.

[0208] The bottom conductive layer 341 and the top conductive layer 345 of the capacitor may each have a single-layer structure or a multi-layer structure, including at least one material selected from tungsten, tungsten nitride (WN), WC (tungsten carbide), titanium, titanium nitride, tantalum, tantalum nitride, ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and nickel boron (NiB). In some embodiments, the bottom conductive layer 341 and the top conductive layer 345 of the capacitor may be formed using a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. In some embodiments, the bottom conductive layer 341 and the top conductive layer 345 of the capacitor may be formed using an atomic layer deposition (ALD) process.

[0209] The capacitor dielectric layer 343 may include an oxide film, a nitride film, an insulating metal oxide film, a high-dielectric film, a polymer film, or a combination thereof. The capacitor dielectric layer 343 may be fabricated using atomic layer deposition (ALD). In some embodiments, the capacitor dielectric layer 343 may be fabricated as a high-dielectric layer with a dielectric constant higher than that of the silicon oxide layer. For example, the dielectric constant of the capacitor dielectric layer 343 may be in the range of approximately 10 to approximately 25. In some embodiments, the capacitor dielectric layer 343 may be fabricated using at least one material selected from the group consisting of: hafnium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, lanthanum oxide, lanthanum, and uranium aluminum oxide. Zirconium oxide, zirconium silicon oxide, zirconium oxide nitride, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, and lead scandium tantalum oxide.

[0210] Figure 27 An intermediate semiconductor element according to an embodiment of the present disclosure is illustrated in a schematic top view. Figure 28 It is along Figure 27 A schematic cross-sectional view taken along line A-A'. Figure 29 It is along Figure 27 A schematic cross-sectional view taken along line B-B'. Figure 30 and Figure 31 A portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure is illustrated in a schematic cross-sectional view.

[0211] Reference Figure 1 and Figures 27 to 31 In step S19, a first bit line top contact area 210 can be formed on the first bit line structure 110, a second bit line top contact area 220 can be formed on the second bit line structure 120, and a plurality of top conductive layers 321 can be formed to electrically couple to the first bit line top contact area 210 and the second bit line top contact area 220.

[0212] Reference Figures 27 to 29The fourth dielectric layer 317 may be formed on the third dielectric layer 315. In some embodiments, the fourth dielectric layer 317 may be fabricated using techniques such as silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant materials, or combinations thereof. The dielectric constant of the low dielectric constant material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material may be less than 2.0. The fourth dielectric layer 317 may be fabricated using deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes. In some embodiments, the fourth dielectric layer 317 may be optional.

[0213] Reference Figures 27 to 29 A photolithography process can be performed on the fourth dielectric layer 317 to define the patterns of the first bitline top contact region 210 and the second bitline top contact region 220. Following the photolithography process, an etching process, such as anisotropic dry etching, can be performed to form openings that expose a portion of the first bitline structure 110 and a portion of the second bitline structure 120. Conductive materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (such as tantalum carbide, titanium carbide, and tantalum magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminum nitrides, or combinations thereof, can be deposited to fill these openings. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the first bitline top contact region 210 and the second bitline top contact region 220.

[0214] Reference Figures 27 to 29 The first element line top contact area 210, viewed from a top angle, may include a first strip 210-1 and a second strip 210-3. The first strip 210-1, viewed from a top angle, may be linear or strip-shaped. The first strip 210-1 may be arranged parallel to the X direction and may be formed at the first end of the first line portion 110-1. The first strip 210-1 may include a first end (e.g., Figure 27 The left end) and the second end opposite the first end (e.g., Figure 27 (The right end of the middle). The second strip 210-3 can be linear or strip-shaped when viewed from above. The second strip 210-3 can be connected to the first end of the first strip 210-1, arranged parallel to the Y direction, and formed on the second strip 110-3.

[0215] In some embodiments, the width W7 of the first strip 210-1 and the width W8 of the second strip 210-3 may be the same. In some embodiments, the width W7 of the first strip 210-1 and the width W8 of the second strip 210-3 may be different. In some embodiments, the width W7 of the first strip 210-1 is greater than the width W1 of the first line 110-1. In some embodiments, the width W8 of the second strip 210-3 is greater than the width W2 of the second line 110-3. In some embodiments, from a top view, a portion of the first end of the first line 110-1 may be covered by the second strip 210-3. In some embodiments, from a top view, the first end of the first line 110-1 is not covered by the second strip 210-3.

[0216] In some embodiments, the length L7 of the first strip portion 210-1 may be less than the length L1 of the first line portion 110-1. In some embodiments, the length L7 of the first strip portion 210-1 may be less than or equal to the length L8 of the second strip portion 210-3. In some embodiments, the length L7 of the first strip portion 210-1 may be greater than the length L8 of the second strip portion 210-3. In some embodiments, the length L8 of the second strip portion 210-3 may be greater than or equal to the length L2 of the second line portion 110-3. In some embodiments, the second line portion 110-3 may be completely covered by the second strip portion 210-3 in a top view. In some embodiments, the length L8 of the second strip portion 210-3 may be less than the length L2 of the second line portion 110-3, and may be greater than the width W7 of the first strip portion 210-1. In some embodiments, the second line portion 110-3 may be partially covered by the second strip portion 210-3 in a top view.

[0217] Reference Figures 27 to 29 The second bit line top contact area 220, viewed from a top angle, may include a first strip 220-1 and a second strip 220-3. The first strip 220-1, viewed from a top angle, may be linear or strip-shaped. The first strip 220-1 may be arranged parallel to the X direction and may be formed at the second end of the first strip 120-1. The first strip 220-1 may include a first end (e.g., Figure 27 The left end) and the second end opposite the first end (e.g., Figure 27 (The right end of the first part 220-1). The second part 220-3 can be linear or strip-shaped when viewed from above. The second part 220-3 can be connected to the second end of the first part 220-1, arranged parallel to the Y direction, and formed on the second line part 120-3.

[0218] In some embodiments, the width W9 of the first strip 220-1 and the width W10 of the second strip 220-3 may be the same. In some embodiments, the width W9 of the first strip 220-1 and the width W10 of the second strip 220-3 may be different. In some embodiments, the width W9 of the first strip 220-1 is greater than the width W4 of the first line 120-1. In some embodiments, the width W10 of the second strip 220-3 is greater than the width W5 of the second line 120-3. In some embodiments, a portion of the second end of the first line 120-1 may be covered by the second strip 220-3 from a top-view perspective. In some embodiments, from a top-view perspective, the second end of the first line 120-1 is not covered by the second strip 220-3.

[0219] In some embodiments, the length L9 of the first strip portion 220-1 may be less than the length L4 of the first line portion 120-1. In some embodiments, the length L9 of the first strip portion 220-1 may be less than or equal to the length L10 of the second strip portion 220-3. In some embodiments, the length L9 of the first strip portion 220-1 may be greater than the length L10 of the second strip portion 220-3. In some embodiments, the length L10 of the second strip portion 220-3 may be greater than or equal to the length L5 of the second line portion 120-3. In some embodiments, the second line portion 120-3 may be completely covered by the second strip portion 220-3 in a top view. In some embodiments, the length L10 of the second strip portion 220-3 may be less than the length L5 of the second line portion 120-3 and may be greater than the width W9 of the first strip portion 220-1. In some embodiments, the second line portion 120-3 may be partially covered by the second strip portion 220-3 in a top view.

[0220] Reference Figure 30 and Figure 31 The fifth dielectric layer 319 may be formed on the fourth dielectric layer 317. In some embodiments, the fifth dielectric layer 319 may be, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, a low dielectric constant material, or a combination thereof. The dielectric constant of the low dielectric constant material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low dielectric constant material may be less than 2.0. The fifth dielectric layer 319 may be fabricated by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or a similar process.

[0221] Reference Figure 30 and Figure 31The multiple top conductive layers 321 can be fabricated in the fifth dielectric layer 319 using, for example, a damascene process. The fabrication techniques for the multiple top conductive layers 321 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The multiple top conductive layers 321 can be electrically coupled to the first bit line top contact region 210 and the second bit line top contact region 220, respectively and accordingly.

[0222] Figure 32 An intermediate semiconductor element 1B according to an embodiment of the present disclosure is illustrated in a schematic top view.

[0223] Reference Figure 32 Semiconductor element 1B can have the same characteristics as... Figure 27 Similar structures to those shown in the image. Figure 32 Zhongyu Figure 27 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0224] In semiconductor element 1B, the second strip 210-3 may include an upper end and a lower end opposite to the upper end. The first strip 210-1 may be connected to the lower end of the second strip 210-3. The first element line top contact area 210 may further include a third strip 210-5. The third strip 210-5 may be connected to the upper end of the second strip 210-3, disposed parallel to the first strip 210-1, and disposed towards and away from the first line 120-1.

[0225] In some embodiments, the third line portion 110-5 may be covered by the third strip portion 210-5 in a top view. In some embodiments, the width W11 of the third strip portion 210-5 may be greater than the width W3 of the third line portion 110-5. In some embodiments, the width W11 of the third strip portion 210-5 and the width W8 of the second strip portion 210-3 may be the same. In some embodiments, the width W11 of the third strip portion 210-5 and the width W8 of the second strip portion 210-3 may be different. In some embodiments, the length L11 of the third strip portion 210-5 may be greater than the length L3 of the third line portion 110-5. In some embodiments, the length L11 of the third strip portion 210-5 may be less than or equal to the length L3 of the third line portion 110-5. In some embodiments, the length L11 of the third strip portion 210-5 may be less than or equal to the length L8 of the second strip portion 210-3. In some embodiments, the length L11 of the third strip portion 210-5 may be greater than the length L8 of the second strip portion 210-3.

[0226] In semiconductor element 1B, the second strip 220-3 may include an upper end and a lower end opposite to the upper end. The first strip 220-1 may be connected to the upper end of the second strip 220-3. The second bit line top contact area 220 may further include a third strip 220-5. The third conditional portion 220-5 may be connected to the lower end of the second conditional portion 220-3, and is disposed parallel to the first strip 220-1, facing towards and away from the first line portion 110-1.

[0227] In some embodiments, the third line portion 120-5 may be covered by the third strip portion 220-5 in a top view. In some embodiments, the width W12 of the third strip portion 220-5 may be greater than the width W6 of the third line portion 120-5. In some embodiments, the width W12 of the third strip portion 220-5 and the width W10 of the second strip portion 220-3 may be the same. In some embodiments, the width W12 of the third strip portion 220-5 and the width W10 of the second strip portion 220-3 may be different. In some embodiments, the length L12 of the third strip portion 220-5 may be greater than the length L6 of the third line portion 120-5. In some embodiments, the length L12 of the third strip portion 220-5 may be less than or equal to the length L6 of the third line portion 120-5. In some embodiments, the length L12 of the third strip portion 220-5 may be less than or equal to the length L10 of the second strip portion 220-3. In some embodiments, the length L12 of the third strip portion 220-5 may be greater than the length L10 of the second strip portion 220-3.

[0228] One embodiment of this disclosure provides a semiconductor device, comprising: a substrate; a first element line structure disposed above the substrate, including a first line portion arranged parallel to a first direction, and a second line portion connected to a first end of the first line portion and arranged parallel to a second direction perpendicular to the first direction; a first element line top contact region, including a first strip portion disposed on the first end of the first line portion and arranged parallel to the first direction, and a second strip portion disposed on the second line portion and arranged parallel to the second direction, connected to a first end of the first strip portion; and a first top conductive layer electrically coupled to the first element line top contact region.

[0229] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first element line structure on the substrate, including a first line portion arranged parallel to the first direction, and a second line portion connected to a first end of the first line portion and arranged parallel to a second direction perpendicular to the first direction; forming a first element line top contact region, including a first strip portion disposed on the first end of the first line portion and arranged parallel to the first direction, and a second strip portion connected to a first end of the first strip portion, disposed on the second line portion and arranged parallel to the second direction; and forming a first top conductive layer for electrically coupling with the first element line top contact region.

[0230] Due to the design of the semiconductor device disclosed herein, the contact area between the first bit line structure 110 and the first bit line top contact region 210, and between the second bit line structure 120 and the second bit line top contact region 220, can be larger. Therefore, the contact area resistance between the first bit line structure 110 and the first bit line top contact region 210, and between the second bit line structure 120 and the second bit line top contact region 220, can be reduced. Thus, the performance of the semiconductor device 1A can be improved (e.g., SWTR testing in wafer probing).

[0231] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0232] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor element, comprising: One base; A first element line structure, placed above the substrate and comprising: A first line portion, arranged parallel to a first direction; and A second line portion is connected to a first end of the first line portion and is arranged parallel to a second direction perpendicular to the first direction; The first element line top touch zone includes: A first strip portion, placed on the first end of the first strip portion, and arranged parallel to the first direction; and A second strip, connected to a first end of the first strip, is placed on the second strip and arranged parallel to the second direction; and A first top conductive layer is electrically coupled to the top contact area of ​​the first element line.

2. The semiconductor device of claim 1, further comprising a source region disposed in the substrate; The first line portion of the first element line structure is electrically coupled to the source region.

3. The semiconductor device of claim 2, further comprising a second bit line structure disposed at the same vertical height as the first bit line structure, comprising: A first line portion, arranged parallel to the first line portion of the first element line structure, and including a first end and a second end; as well as A second line portion is connected to the second end of the first line portion of the second bit line structure, and is arranged parallel to the second line portion of the first bit line structure, and is positioned toward the first line portion of the first bit line structure; The first end of the first line portion of the second bit line structure is positioned toward the second line portion of the first bit line structure, and the second end of the first line portion of the second bit line structure is opposite to the first end of the first line portion of the second bit line structure.

4. The semiconductor device of claim 3, further comprising a second bit line top contact region disposed at the same vertical height as the first bit line top contact region, and including: A first strip portion, arranged parallel to the first direction, is placed on the second end of the first strip portion of the second bit line structure, and includes a first end and a second end; and A second strip is connected to the second end of the first strip in the top contact area of ​​the second bit line, is placed on the second strip of the second bit line structure, and is arranged parallel to the second strip of the first bit line structure; The first end of the first strip of the second bit line top contact area is positioned toward the second strip of the first bit line top contact area, and the second end of the first strip of the second bit line top contact area is opposite to the first end of the first strip of the second bit line top contact area.

5. The semiconductor device of claim 4 further includes a second top conductive layer for electrically coupling with the top contact region of the second bit line.

6. The semiconductor device as claimed in claim 3, wherein, The first bit line structure further includes a third bit portion, which is connected to the second bit portion of the first bit line structure, aligned with the first bit portion of the second bit line structure, and positioned toward the first bit portion of the second bit line structure.

7. The semiconductor device of claim 6, wherein, The first element line structure further includes a third section, which is connected to the second section of the first element line top contact area and is placed on the third section of the first element line structure.

8. The semiconductor device as claimed in claim 5, wherein, The second bit line structure further includes a third line portion, which is connected to the second line portion of the second bit line structure, aligned with the first line portion of the first bit line structure, and positioned toward the first line portion of the first bit line structure.

9. The semiconductor device as claimed in claim 8, wherein, The second bit line structure further includes a third section, which is connected to the second section of the top contact area of ​​the second bit line and is placed on the third section of the second bit line structure.

10. The semiconductor element of claim 2, wherein the width of the first strip portion of the first element line top contact area is greater than the width of the first line portion of the first element line structure.

11. The semiconductor element of claim 2, wherein the width of the second strip portion of the first element line top contact area is greater than the width of the second line portion of the first element line structure.

12. The semiconductor element of claim 7, wherein the third line portion of the first element line structure is completely covered by the third strip portion of the top contact area of ​​the first element line in a top view angle.

13. The semiconductor element of claim 5, wherein the width of the first strip portion of the second bit line top contact region is greater than the width of the first line portion of the second bit line structure.

14. The semiconductor element of claim 5, wherein a width of the second strip portion of the second bit line top contact region is greater than a width of the second line portion of the second bit line structure.

15. The semiconductor element of claim 9, wherein the third line portion of the second bit line structure is completely covered by the third strip portion of the top contact area of ​​the second bit line.

16. The semiconductor element of claim 3, wherein a length of the second line portion of the first bit line structure is less than or equal to a distance between the first line portion of the first bit line structure and the first line portion of the second bit line structure.

17. The semiconductor element of claim 2, wherein a length of the second strip of the first element line top contact region is equal to or less than a length of the first strip of the first element line top contact region.

18. The semiconductor element of claim 2, wherein a length of the second strip of the first element line top contact region is greater than a length of the first strip of the first element line top contact region.

19. The semiconductor element of claim 2, wherein a length of the second portion of the first element line top contact region is greater than or equal to a length of the second portion of the first element line structure.

20. A method for fabricating a semiconductor device, comprising: Provide a base; A first element line structure is formed above the substrate, including: A first line portion, arranged parallel to a first direction; and A second line portion is connected to a first end of the first line portion and is arranged parallel to a second direction perpendicular to the first direction; A first-order line top-touching zone is formed, including: A first strip portion, placed on the first end of the first strip portion, and arranged parallel to the first direction; and A second strip, connected to a first end of the first strip, is placed on the second strip and arranged parallel to the second direction; and A first top conductive layer is formed to electrically couple with the top contact area of ​​the first element line.

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