Method for manufacturing semiconductor chip and semiconductor chip

Abstract

The application discloses a semiconductor chip manufacturing method, comprising the following steps: growing a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped substrate and a lightly doped epitaxial layer, the doping type of the substrate and the epitaxial layer being N type; forming a groove on the semiconductor substrate by using a photoetching and etching process with the hard mask medium layer as a barrier layer; removing the hard mask medium layer, growing a first silicon oxide, a silicon nitride and a second silicon oxide; removing the second silicon oxide protruding from the upper surface of the silicon nitride by using a chemical mechanical polishing process, and retaining the second silicon oxide in the groove; forming a first P type doped region and a second P type doped region in the epitaxial layer by using an ion implantation and annealing process; the application provides a semiconductor chip, and the semiconductor chip manufacturing method and the semiconductor chip disclosed by the application have the advantages of EAS characteristics and more stable threshold voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a method for manufacturing semiconductor chips and semiconductor chips. Background Technology

[0002] MOSFET chips are a type of semiconductor chip, belonging to the category of power semiconductor chips. According to their physical structure, MOSFET chips can be classified into two main categories: planar MOSFETs and trench MOSFETs. Among them, trench MOSFETs have higher current density and dominate in low- and medium-voltage MOSFETs. According to their conductivity type, MOSFET chips can be classified into N-channel MOSFETs and P-channel MOSFETs. The majority carriers of N-channel MOSFETs are free electrons, while the majority carriers of P-channel MOSFETs are holes. Therefore, N-channel MOSFETs have higher current density and are used in a wider range of applications.

[0003] DC parameters used to evaluate the quality of a MOSFET chip include breakdown voltage, on-resistance, and threshold voltage. Generally, a higher breakdown voltage is better, and a lower on-resistance is better. Threshold voltage is the gate voltage required to turn on the MOSFET when a channel is formed on the trench sidewall.

[0004] Non-DC parameters used to measure the quality of a MOSFET chip include parasitic capacitance, switching time, and avalanche current (EAS). Among these, avalanche current (EAS) reflects the MOSFET's ability to withstand pulse current. As those skilled in the art know, avalanche current is mainly affected by chip area, base resistance, and contact hole resistance. Summary of the Invention

[0005] This invention provides a method for manufacturing a semiconductor chip and a semiconductor chip with advantages such as EAS characteristics and more stable threshold voltage, solving the problems of unstable EAS and threshold voltage in the original MOSFET.

[0006] The semiconductor chip manufacturing method provided in the embodiments of this application includes the following steps: A hard mask dielectric layer is grown on a semiconductor substrate, the semiconductor substrate comprising a heavily doped substrate and a lightly doped epitaxial layer, the doping type of the substrate and the epitaxial layer being N-type; Using a hard mask dielectric layer as a barrier layer, trenches are formed on a semiconductor substrate using photolithography and etching processes; Remove the hard mask dielectric layer and grow a first silicon oxide, silicon nitride, and a second silicon oxide; A chemical mechanical polishing process is used to remove the second silicon oxide that protrudes above the upper surface of the silicon nitride, while retaining the second silicon oxide in the trench. A first P-type doped region and a second P-type doped region are formed in the epitaxial layer by ion implantation and annealing processes. An etching process is used to remove part of the second silicon dioxide from the trench; The upper and side surfaces of the second P-type doped region were inverted by ion implantation. An etching process is used to sequentially remove all of the second silicon oxide, silicon nitride, and first silicon oxide. A thermal oxidation process is used to grow the third silicon oxide layer, i.e., the gate oxide layer; Polysilicon is deposited, and the polysilicon protruding above the surface of the third silicon oxide is removed, while the polysilicon in the trench is retained; The source region is formed using photolithography, ion implantation, and annealing processes. Fabricate contact holes; A third P-type doped region is formed at the bottom and sides of the contact hole using ion implantation and annealing processes; A fourth P-type doped region is formed at the bottom and sides of the contact hole using ion implantation and annealing processes.

[0007] Preferably, the first P-type doped region is the body region of the MOSFET, the polysilicon is the polysilicon gate of the MOSFET, the substrate and epitaxial layer are the drain of the MOSFET, and the second, third, and fourth P-type doped regions are heavily doped body regions.

[0008] Preferably, the depth of the trench is 0.8 to 1.6 micrometers and the width is 0.1 to 0.4 micrometers.

[0009] Preferably, the thickness of the first silicon oxide is 200-500 angstroms, and the process for growing the first silicon oxide is thermal oxidation; the thickness of the silicon nitride is 200-600 angstroms, and the process for growing the silicon nitride is chemical vapor deposition; the thickness of the second silicon oxide is 2000-8000 angstroms, and the process for growing the second silicon oxide is high-density plasma chemical vapor deposition; and the second silicon oxide fills the trench.

[0010] Preferably, after the process of growing the first silicon oxide, silicon nitride and the second silicon oxide, a high-temperature annealing is performed to make the first silicon oxide, silicon nitride and the second silicon oxide more dense, and the high-temperature annealing temperature is 900 to 1150 degrees Celsius.

[0011] Preferably, the ion implantation and annealing process is used to form a first P-type doped region and a second P-type doped region in the epitaxial layer. The dopant for ion implantation is boron. The ion implantation dose for forming the first P-type doped region is 0.6E13 to 1.5E13 ions / cm², and the ion implantation dose for forming the second P-type doped region is greater than that for forming the first P-type doped region, which is 2E13 to 2E14 ions / cm². The first P-type doped region is distributed from the upper surface of the epitaxial layer to a depth of D1, and the depth of the first P-type doped region (D1) is 0.6 to 1.2 micrometers. The second P-type doped region is distributed from the upper surface of the epitaxial layer to a depth of D2, and the depth of the second P-type doped region (D2) is less than that of the first P-type doped region (D1), which is 0.3 to 0.6 micrometers.

[0012] Preferably, the etching process is used to remove part of the second silicon oxide in the trench. The etching process is quantitative etching, in which all the second silicon oxide from the upper surface of the epitaxial layer to a depth of D3 is etched away, and D3 is 300-800 angstroms smaller than D2.

[0013] Preferably, in the fabrication of the contact hole, the depth D4 of the contact hole in the epitaxial layer is less than the depth D2 of the second P-type doped region, and the depth D4 of the contact hole in the epitaxial layer is 0.2 to 0.4 micrometers. The process involves ion implantation and annealing to form a third P-type doped region at the bottom and sides of the contact hole. The dopant for ion implantation is boron, the implantation dose E4 is 1E15 to 5E15 ions / cm², the implantation energy Y1 is 5 to 25 keV, and the annealing temperature T1 is 900 to 1000 degrees Celsius, using a rapid thermal annealing process.

[0014] Preferably, the ion implantation and annealing process is used to form a fourth P-type doped region on the bottom and sides of the contact hole. The dopant implanted in this step is boron. The implantation dose E5 is greater than the ion implantation dose E2 for forming the second P-type doped region and less than the ion implantation dose E4 for forming the third P-type doped region, which is 5E13 to 5E14 per cm². The implantation energy Y2 is greater than the ion implantation energy Y1 for forming the third P-type doped region, which is 15 to 50 keV. The annealing temperature T2 in this step is less than the annealing temperature T1 for forming the third P-type doped region, which is 800 to 900 degrees Celsius. A rapid thermal annealing process is used.

[0015] The present invention provides a semiconductor chip, which is manufactured according to the above-described semiconductor chip manufacturing method.

[0016] The technical solutions provided in this application embodiment may include the following beneficial effects: 1. This invention rationally sets the ion implantation energy and annealing process temperature for forming the fourth P-type doped region, making the width of the fourth P-type doped region smaller than the width of the second P-type doped region. This invention first fabricates a third P-type doped region with a higher doping concentration, then fabricates a fourth P-type doped region with a lower doping concentration, and anneals them separately. This allows for more precise width distribution of the fourth P-type doped region while ensuring the third P-type doped region with a higher doping concentration is fully activated, using a lower annealing temperature. The width of the fourth P-type doped region is always smaller than the width of the second P-type doped region, thus maximizing the width of the fourth P-type doped region. A larger width results in a lower base resistance and better EAS characteristics for the MOSFET.

[0017] Thus, from the sidewall of the trench to the side of the contact hole, a series of P-type doped regions with increasing doping concentration are formed, consisting of a first P-type doped region, a second P-type doped region, a fourth P-type doped region, and a third P-type doped region. The first P-type doped region has the lowest doping concentration and is the body region of the MOSFET. When the MOSFET is turned on, this region is the channel region. The doping concentration of the first P-type doped region and the second P-type doped region adjacent to the first P-type doped region is relatively small, which is beneficial to the process stability of the MOSFET's threshold voltage. The third P-type doped region has the highest doping concentration and is the metal sintering region. The higher the doping concentration, the lower the contact hole resistance and the better the EAS characteristics of the MOSFET.

[0018] The fourth P-type doped region has a higher doping concentration and is located between the contact hole and the channel. It can significantly reduce the base resistance of the MOSFET, thereby improving its EAS characteristics.

[0019] 2. The third and fourth P-type doped regions are formed by ion implantation through contact holes followed by annealing. As is well known, the formation of contact holes requires photolithography, which inevitably introduces alignment deviations. Therefore, the distance from the boundary of the third and fourth P-type doped regions to the trench sidewall is a non-quantitative value affected by process accuracy and repeatability. However, this invention rationally sets the process parameters so that the width of the fourth P-type doped region is always smaller than the width of the second P-type doped region. Moreover, the second P-type doped region is formed through a series of ion implantation and annealing processes, without the need for photolithography, thus eliminating the photolithography alignment deviation problem. In other words, the distance from the boundary of the second P-type doped region to the trench sidewall is a quantitative distance that can be adjusted through the ion implantation process and is not affected by the photolithography process. Therefore, the MOSFET formed by this invention has more stable EAS characteristics and threshold voltage. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1-A This is a schematic flowchart of the semiconductor chip manufacturing method of the present invention; Figure 1-B This is a schematic flowchart of the semiconductor chip manufacturing method of the present invention; Figure 1 This is a schematic diagram of the structure of step S1 of the present invention; Figure 2 This is a schematic diagram of the structure of step S2 of the present invention; Figure 3 This is a schematic diagram of the structure of step S3 of the present invention; Figure 4 This is a schematic diagram of the structure of step S4 of the present invention; Figure 5 This is a schematic diagram of the structure of step S5 of the present invention; Figure 6 This is a schematic diagram of the structure of step S6 of the present invention; Figure 7 This is a schematic diagram of the structure of step S7 of the present invention; Figure 8 This is a schematic diagram of the structure of step S8 of the present invention; Figure 9 This is a schematic diagram of the structure of step S9 of the present invention; Figure 10 This is a schematic diagram of the structure of step S10 of the present invention; Figure 11 This is a schematic diagram of the structure of step S11 of the present invention; Figure 12 This is a schematic diagram of the structure of step S12 of the present invention; Figure 13 This is a schematic diagram of the structure of step S13 of the present invention; Figure 14 This is a schematic diagram of step S14 of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] Please see Figure 1-A to Figure 1 -B, This invention provides a method 100 for manufacturing a semiconductor chip, comprising the following steps: Step S1: Grow a hard mask dielectric layer 3 on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped substrate 1 and a lightly doped epitaxial layer 2, and the doping type of the substrate 1 and the epitaxial layer 2 is N-type (see [reference]). Figure 1 ); Step S2: Using the hard mask dielectric layer 3 as a barrier layer, trench 4 is formed on the semiconductor substrate using photolithography and etching processes (see...). Figure 2 ); Step S3: Remove the hard mask dielectric layer and grow the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7 (see...) Figure 3 ); Step S4: Using a chemical mechanical polishing process, remove the second silicon oxide 7 that protrudes above the upper surface of the silicon nitride 6, while retaining the second silicon oxide 7 in the trench 4 (see...). Figure 4 ); Step S5: Using ion implantation and annealing processes, a first P-type doped region 8 and a second P-type doped region 9 are formed in the epitaxial layer 2 (see...). Figure 5 ); Step S6: Use an etching process to remove part of the second silicon dioxide 7 in the trench 4 (see...) Figure 6 ); Step S7: Using ion implantation technology, reverse implantation doping is performed on the upper and side surfaces of the second P-type doped region 9 (see...). Figure 7 ); Step S8: Using an etching process, sequentially remove all of the second silicon oxide 7, silicon nitride 6, and first silicon oxide 5 (see...). Figure 8 ); Step S9: Using a thermal oxidation process, grow the third silicon oxide 10, i.e., the gate oxide layer (see...). Figure 9 ); Step S10: Deposit polysilicon 11 and remove the polysilicon 11 protruding above the upper surface of the third silicon oxide 10, retaining the polysilicon 11 in the trench 4 (see...). Figure 10 ); Step S11: The source region 12 is formed using photolithography, ion implantation, and annealing processes (see...). Figure 11 ); Step S12: Fabricate contact hole 13 (see...) Figure 12 ); Step S13: Using ion implantation and annealing processes, a third P-type doped region 14 is formed on the bottom and sides of the contact hole 13 (see...). Figure 13 ); Step S14: Using ion implantation and annealing processes, a fourth P-type doped region 15 is formed on the bottom and sides of the contact hole 13 (see...). Figure 14 ).

[0026] Thus, the main structure of the MOSFET chip formed by the present invention has been formed, wherein the first P-type doped region 8 is the body region of the MOSFET, the polysilicon 12 is the polysilicon gate of the MOSFET, the substrate 1 and the epitaxial layer 2 are the drain of the MOSFET, the second P-type doped region 9, the third P-type doped region 14, and the fourth P-type doped region 15 are heavily doped body regions, and other main structures such as the source region and the gate oxide layer have been described above.

[0027] The subsequent process steps are standard and will not be described in detail.

[0028] It is understood that in this embodiment, the trench 4 has a depth of 0.8 to 1.6 micrometers and a width of 0.1 to 0.4 micrometers (the MOSFET chip is composed of several cells, and the schematic diagram only shows one cell).

[0029] It is understood that in this embodiment, the thickness of the first silicon oxide 5 is 200-500 angstroms, and the preferred process for growing the first silicon oxide 5 is thermal oxidation; the thickness of the silicon nitride 6 is 200-600 angstroms, and the preferred process for growing the silicon nitride 6 is chemical vapor deposition; the thickness of the second silicon oxide 7 is 2000-8000 angstroms, and the preferred process for growing the second silicon oxide 7 is chemical vapor deposition, preferably high-density plasma chemical vapor deposition (HDP). The advantage of HDP is that it has better filling properties and can better fill all corners of the trench without easily generating voids.

[0030] The first silicon oxide 5 and the silicon nitride 6 have relatively small thicknesses, and both uniformly cover the bottom and sidewalls of the trench 4, as well as the area outside the trench 4.

[0031] The second silicon oxide 7 has a relatively large thickness, which fills the trench 4.

[0032] It is understood that in this embodiment, after the process of growing the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7, high-temperature annealing is performed to make the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7 more dense. The high-temperature annealing temperature is 900-1150 degrees Celsius. (After high-temperature annealing, the second silicon oxide 7 becomes more dense, and its corrosion rate is lower in the subsequent etching process. This allows for more precise quantitative etching, thereby accurately defining its etching depth in the process, as detailed below.)

[0033] It is understood that in step S5, the ion implantation and annealing process is used to form a first P-type doped region 8 and a second P-type doped region 9 in the epitaxial layer 2. The dopant implanted by the ions is boron. The ion implantation dose (E1) for forming the first P-type doped region 8 is 0.6E13 to 1.5E13 ions / cm², and the ion implantation dose (E2) for forming the second P-type doped region 9 is greater than the ion implantation dose for forming the first P-type doped region 8, which is 2E13 to 2E14 ions / cm². The first P-type doped region 8 is distributed from the upper surface of the epitaxial layer 2 to a depth of D1, and the depth (D1) of the first P-type doped region 8 is 0.6 to 1.2 micrometers. The second P-type doped region 9 is distributed from the upper surface of the epitaxial layer 2 to a depth of D2, and the depth (D2) of the second P-type doped region 9 is less than the depth (D1) of the first P-type doped region 8, which is 0.3 to 0.6 micrometers.

[0034] Thus, this process involves forming a first P-type doped region with a depth of D1 in the epitaxial layer 2, and forming a second P-type doped region 9 with a higher doping concentration and a shallower depth of D2 on the upper surface of the first P-type doped region.

[0035] It is understood that in step S6, the etching process is used to remove part of the second silicon oxide 7 in the trench 4: the etching process is quantitative etching, and the second silicon oxide 7 from the upper surface of the epitaxial layer 2 to the region with a depth of D3 is completely etched away, where D3 is 300 to 800 angstroms smaller than D2.

[0036] It is understood that in step S7, the ion implantation process is used to implant doping of the upper and side surfaces of the second P-type doped region 9. The dopant implanted is phosphorus, and the implantation dose is E3, which is equal to E2. Phosphorus ions penetrate the first silicon oxide 5 and silicon nitride 6 and enter the upper and side surfaces of the second P-type doped region 9, where they are electrically neutralized with the previously implanted boron ions at a dose of E2. Therefore, the upper and side surfaces of the second P-type doped region 9 are transformed into doped regions with the same resistivity as the first P-type doped region 8. Figure 7The first P-type doped region 8 is shown directly in the middle; below the second P-type doped region 9, this region will not be implanted with phosphorus ions due to the blocking effect of the second silicon oxide 7.

[0037] It can be understood that in step S12, the contact hole 13 is fabricated such that the depth D4 of the contact hole in the epitaxial layer 2 is less than the depth D2 of the second P-type doped region 9, and the depth D4 of the contact hole in the epitaxial layer 2 is 0.2 to 0.4 micrometers.

[0038] It is understood that in step S13, the ion implantation and annealing process is used to form a third P-type doped region 14 at the bottom and side of the contact hole 13. The dopant implanted in this step is boron, the implantation dose E4 is 1E15 to 5E15 particles / cm², the implantation energy Y1 is 5 to 25 keV, and the annealing temperature T1 is 900 to 1000 degrees Celsius. It is preferred to use a rapid thermal annealing process.

[0039] The ion implantation dose in this step is too large (exceeding 1E15 ions / cm²), requiring a higher annealing process temperature to fully activate the dopants and repair the silicon damage caused by ion implantation.

[0040] It is understood that in step S14, the ion implantation and annealing process is used to form a fourth P-type doped region 15 at the bottom and side of the contact hole 13. The dopant implanted in this step is boron, the implantation dose E5 is greater than the ion implantation dose E2 for forming the second P-type doped region 9 and less than the ion implantation dose E4 for forming the third P-type doped region 14, which is 5E13 to 5E14 per cm². The implantation energy Y2 is greater than the ion implantation energy Y1 for forming the third P-type doped region 14, which is 15 to 50 keV. The annealing temperature T2 in this step is less than the annealing temperature T1 for forming the third P-type doped region 14, which is 800 to 900 degrees Celsius. A rapid thermal annealing process is preferred.

[0041] This step involves a small ion implantation dose (less than 1E15 ions / cm²), requiring only a lower annealing temperature to fully activate the dopants and repair silicon damage caused by ion implantation.

[0042] Due to the difference in injected energy, at the bottom of the contact hole 13, the depth of the fourth P-type doped region 15 is greater than the depth of the third P-type doped region 14, and on the side of the contact hole 13, the width of the fourth P-type doped region 15 is greater than the width of the third P-type doped region 14.

[0043] By appropriately setting the ion implantation energy and annealing temperature for forming the fourth P-type doped region 15, the width of the fourth P-type doped region 15 is made smaller than the width of the second P-type doped region 9. In this design, a third P-type doped region 14 with a higher doping concentration is first fabricated, followed by a fourth P-type doped region 15 with a lower doping concentration. The two are annealed separately. This ensures that the fourth P-type doped region 15 is always smaller than the width of the second P-type doped region 9, while ensuring that the third P-type doped region with a higher doping concentration is fully activated. Using a lower annealing temperature makes the distribution width of the fourth P-type doped region 15 more precise, thereby maximizing the width of the fourth P-type doped region 15. The larger the width of the fourth P-type doped region 15, the lower the base resistance of the MOSFET and the better the EAS characteristics.

[0044] Thus, the lateral region from the sidewall of trench 4 to the side of contact hole 13 forms a group of P-type doped regions with increasing doping concentration, namely the first P-type doped region 8, the second P-type doped region 9, the fourth P-type doped region 15, and the third P-type doped region 14. The first P-type doped region 8 has the lowest doping concentration and is the body region of the MOSFET. When the MOSFET is turned on, this region is the channel region. The doping concentration of the first P-type doped region 8 and the second P-type doped region 9 adjacent to the first P-type doped region 8 is relatively small, which is beneficial to the process stability of the MOSFET's threshold voltage. The third P-type doped region 14 has the highest doping concentration. This region is the metal sintering region. The higher the doping concentration, the lower the contact hole resistance, and the better the EAS characteristics of the MOSFET.

[0045] The fourth P-type doped region 15 has a relatively high doping concentration and is located between the contact hole and the channel. It can significantly reduce the base resistance of the MOSFET, thereby improving its EAS characteristics.

[0046] The third P-type doped region 14 and the fourth P-type doped region 15 are formed by ion implantation through contact holes followed by annealing. As is well known, the formation of contact holes requires photolithography, which inevitably introduces alignment deviations. Therefore, the distance from the boundary of the third P-type doped region 14 and the fourth P-type doped region 15 to the sidewall of the trench 4 is a non-quantitative value affected by process accuracy and repeatability. However, this invention rationally sets the process parameters so that the width of the fourth P-type doped region 15 is always smaller than the width of the second P-type doped region 9. Moreover, the second P-type doped region 9 is formed through a series of ion implantation and annealing processes, without the need for photolithography, and thus there is no photolithography alignment deviation problem (in the industry, such process designs that are not affected by photolithography alignment deviations are called self-aligned processes). That is, the distance from the boundary of the second P-type doped region 9 to the sidewall of the trench 4 is a quantitative distance that can be adjusted by the ion implantation process and is not affected by the photolithography process. Therefore, the MOSFET formed by this invention has more stable EAS characteristics and threshold voltage.

[0047] In summary, through a series of process designs, this invention forms a densely doped body region with increasing concentration, consisting of a second P-type doped region 9, a fourth P-type doped region 15, and a third P-type doped region 14, in the lateral region from the trench sidewall to the contact hole, excluding the body region (first P-type doped region 8). This significantly reduces the body resistance and contact hole resistance of the MOSFET. Furthermore, the second P-type doped region 9, which is closest to the channel, is formed using a self-aligned process. Therefore, the threshold voltage, EAS characteristics, and stability of the MOSFET chip fabricated using this invention are much better than those of traditional methods.

[0048] This invention first creates a second P-type doped region 9 with a higher doping concentration on the upper surface of a first P-type doped region 8 with a lower doping concentration. Then, through ion implantation doping with opposite electrical properties, the upper and side surface regions of the second P-type doped region 9 are restored to the doping concentration and doping type of the first P-type doped region 8. A clever technique is employed: implanting dopants of opposite types from the trench sidewalls. This ion implantation doping relies on quantitative etching of the barrier layer (second silicon oxide 7) in the trench. Before quantitatively etching the oxide layer (second silicon oxide 7) in the trench, a chemical mechanical polishing process is used to remove the second silicon oxide protruding above the silicon nitride surface. This method ensures that the initial position of the second silicon oxide remains fixed before quantitative etching, thus precisely guaranteeing the depth of quantitative etching. The high-temperature annealing following the growth of the first silicon oxide 5, silicon nitride 6, and second silicon oxide 7, as mentioned above, is also to reduce the etching rate of the second silicon oxide 7, thereby enabling more precise quantitative etching at the operational level. Precisely ensuring the depth of quantitative etching allows for a more accurate definition of the region where the side surface of the second P-type doped region 9 is doped with the opposite type of implantation using ion implantation, thus forming the doped region structure distribution required in this case.

[0049] Therefore, the seemingly simple combination of process steps in this case is actually achieved through very ingenious process design, ultimately achieving process effects that other people in the industry cannot achieve. Moreover, compared with the traditional process method for manufacturing MOSFET chips, this case does not add a photolithography layer, and still maintains an advantage in terms of process cost.

[0050] Another embodiment of the present invention provides a semiconductor chip, which is manufactured according to the semiconductor chip manufacturing method 100 described above.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor chip, characterized in that, Includes the following steps: A hard mask dielectric layer is grown on a semiconductor substrate, the semiconductor substrate comprising a heavily doped substrate and a lightly doped epitaxial layer, the doping type of the substrate and the epitaxial layer being N-type; Using a hard mask dielectric layer as a barrier layer, trenches are formed on a semiconductor substrate using photolithography and etching processes; Remove the hard mask dielectric layer and grow a first silicon oxide, silicon nitride, and a second silicon oxide; A chemical mechanical polishing process is used to remove the second silicon oxide that protrudes above the upper surface of the silicon nitride, while retaining the second silicon oxide in the trench. An ion implantation and annealing process is used to form a first P-type doped region and a second P-type doped region in the epitaxial layer, wherein the depth D2 of the second P-type doped region is less than the depth D1 of the first P-type doped region. An etching process is used to remove part of the second silicon dioxide from the trench; The upper and side surfaces of the second P-type doped region were inverted by ion implantation. An etching process is used to sequentially remove all of the second silicon oxide, silicon nitride, and first silicon oxide. A thermal oxidation process is used to grow the third silicon oxide layer, i.e., the gate oxide layer; Polysilicon is deposited, and the polysilicon protruding above the surface of the third silicon oxide is removed, while the polysilicon in the trench is retained; The source region is formed using photolithography, ion implantation, and annealing processes. Fabricate contact holes; A third P-type doped region is formed at the bottom and sides of the contact hole using ion implantation and annealing processes; A fourth P-type doped region is formed at the bottom and sides of the contact hole using ion implantation and annealing processes; The width of the fourth P-type doped region is smaller than the width of the second P-type doped region; A set of P-type doped regions with increasing doping concentrations is formed in the transverse region between the sidewall of the trench and the side of the contact hole, consisting of the first P-type doped region, the second P-type doped region, the fourth P-type doped region, and the third P-type doped region.

2. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The first P-type doped region is the body region of the MOSFET, the polysilicon is the polysilicon gate of the MOSFET, the substrate and epitaxial layer are the drain of the MOSFET, and the second, third, and fourth P-type doped regions are heavily doped body regions.

3. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The trench has a depth of 0.8 to 1.6 micrometers and a width of 0.1 to 0.4 micrometers.

4. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The thickness of the first silicon oxide is 200-500 angstroms, and the process for growing the first silicon oxide is thermal oxidation. The thickness of the silicon nitride is 200-600 angstroms, and the process for growing the silicon nitride is chemical vapor deposition. The thickness of the second silicon oxide is 2000-8000 angstroms, and the process for growing the second silicon oxide is high-density plasma chemical vapor deposition. The second silicon oxide fills the trench.

5. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, After the process of growing the first silicon oxide, silicon nitride and the second silicon oxide, high-temperature annealing is performed to make the first silicon oxide, silicon nitride and the second silicon oxide more dense. The high-temperature annealing temperature is 900 to 1150 degrees Celsius.

6. The method for manufacturing a semiconductor chip according to claim 1, characterized in that, The process employs ion implantation and annealing to form a first P-type doped region and a second P-type doped region in the epitaxial layer. The dopant used for ion implantation is boron. The ion implantation dose for forming the first P-type doped region is 0.6E13 to 1.5E13 ions / cm², and the ion implantation dose for forming the second P-type doped region is greater than that for forming the first P-type doped region, being 2E13 to 2E14 ions / cm². The first P-type doped region is distributed across the entire region from the upper surface of the epitaxial layer to a depth of D1, with a depth D1 of 0.6 to 1.2 micrometers. The second P-type doped region is distributed across the entire region from the upper surface of the epitaxial layer to a depth of D2, with a depth D2 of 0.3 to 0.6 micrometers.

7. The method for manufacturing a semiconductor chip according to claim 6, characterized in that, The etching process is used to remove part of the second silicon oxide in the trench. The etching process is quantitative etching, in which all the second silicon oxide from the upper surface of the epitaxial layer to a depth of D3 is etched away. D3 is 300-800 angstroms smaller than D2.

8. The method for manufacturing a semiconductor chip according to claim 7, characterized in that, The contact hole is fabricated such that its depth D4 in the epitaxial layer is less than the depth D2 of the second P-type doped region. The depth D4 of the contact hole in the epitaxial layer is 0.2 to 0.4 micrometers. The process involves ion implantation and annealing to form a third P-type doped region at the bottom and sides of the contact hole. The dopant for ion implantation is boron, the implantation dose E4 is 1E15 to 5E15 ions / cm², the implantation energy Y1 is 5 to 25 keV, and the annealing temperature T1 is 900 to 1000 degrees Celsius using a rapid thermal annealing process.

9. The method for manufacturing a semiconductor chip according to claim 8, characterized in that, The process employs ion implantation and annealing to form a fourth P-type doped region on the bottom and sides of the contact hole. The dopant implanted in this step is boron. The implantation dose E5 is greater than the ion implantation dose E2 for forming the second P-type doped region and less than the ion implantation dose E4 for forming the third P-type doped region, which is 5E13 to 5E14 per cm². The implantation energy Y2 is greater than the ion implantation energy Y1 for forming the third P-type doped region, which is 15 to 50 keV. The annealing temperature T2 in this step is less than the annealing temperature T1 for forming the third P-type doped region, which is 800 to 900 degrees Celsius. A rapid thermal annealing process is used.

10. A semiconductor chip, characterized in that, The semiconductor chip is manufactured according to the semiconductor chip manufacturing method according to claim 1.

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