Method for manufacturing gate interlayer of sgt semiconductor device

Abstract

The application discloses a manufacturing method of gate dielectric layer of SGT semiconductor device, comprising the following steps: step one, forming a gate trench, a bottom dielectric layer and a shielding gate conductive material layer in the gate trench; step two, forming a second dielectric layer covering the inner and outer surfaces of the gate trench with the shielding gate conductive material layer; step three, forming a first mask layer to completely fill the first gap in the gate trench and extend to the outside of the first gap, and performing patterning to form a first opening in the first mask layer, the first opening being located on both sides of the gate trench and exposing the surface of the bottom second dielectric layer; step four, performing etching on the second dielectric layer from the bottom of the first opening by wet etching, and forming the gate dielectric layer by the second dielectric layer after the wet etching; step five, removing the first mask layer; and step six, forming a gate dielectric layer and a gate conductive material layer. The application can independently and accurately adjust the thickness of the gate dielectric layer, and the process is simple.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing the inter-gate dielectric layer of a trench gate (SGT) semiconductor device with a shielded gate. Background Technology

[0002] In SGT semiconductor devices such as SGT MOSFETs, the most crucial process step is the isolation between the two polysilicon gates in the gate trench—the polysilicon shield gate and the polysilicon gate itself. This isolation is typically achieved using an oxide layer, known as the inter-polysilicon oxide (IPO). The polysilicon shield gate connects to the source, which is composed of a front-side metal layer; hence, the polysilicon shield gate is also called the source polysilicon. The polysilicon gate connects to the gate, which is also composed of a front-side metal layer. The thickness and stability of the IPO not only affect the isolation effect between the gate and source but also the input capacitance, making it critical for the SGT process.

[0003] Currently, there are two main IPO production methods in the industry: thermal oxidation process for IPO formation and high-density plasma (HDP) chemical vapor deposition (CVD) process for IPO deposition.

[0004] In the thermal oxidation process for forming the IPO, after the bottom source polysilicon is formed, heavy ion implantation is performed to further create defects on the surface of the source polysilicon. Meanwhile, the semiconductor material, such as silicon, in the sidewall channel region of the gate trench (Mesa) remains in a relatively good single-crystal structure. Then, a thermal oxidation process is performed to form the IPO on top of the source polysilicon, while a gate oxide layer (GOX) is formed on the sidewall of the gate trench. Taking advantage of the numerous defects on the surface of the source polysilicon, the thickness of the IPO is made greater than the thickness of the gate oxide layer. This process is simple in steps but quite difficult. Furthermore, the IPO to GOX thickness ratio is fixed, limiting the adjustable thickness range and making it unsuitable for thin gate oxide products. Additionally, a significant thinning of the IPO is likely to occur at the polycorner of the source polysilicon.

[0005] In HDP CVD deposition of the IPO (Initial Gate Isolation), an oxide layer is formed to completely fill the gate trench using HDP CVD, and then the oxide layer is etched back to form the IPO of the desired thickness. This process allows for a wide adjustable range of IPO thickness, unaffected by the thickness of the gate oxide layer. However, the process is complex and costly. Furthermore, it is limited by the filling capacity of HDP, making it difficult to achieve an aspect ratio greater than 3. The IPO thickness depends on the oxide layer etch-back, resulting in significant fluctuations. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing an inter-gate dielectric layer of an SGT semiconductor device, wherein the thickness of the inter-gate dielectric layer can be independent of the thickness of the gate dielectric layer and the thickness of the inter-gate dielectric layer can be precisely adjusted, and the process is simple and the process difficulty is low.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the inter-gate dielectric layer of an SGT semiconductor device, comprising the following steps:

[0008] Step 1: Form a gate trench on a semiconductor substrate, and form a bottom dielectric layer and a shielding gate conductive material layer in the gate trench; in the device cell region of the active region, the shielding gate conductive material layer fills the bottom of the gate trench and the bottom dielectric layer isolates the shielding gate conductive material layer from the gate trench.

[0009] Step 2: Form a second dielectric layer. The second dielectric layer covers the surface of the shielding gate conductive material layer, the surface of the bottom dielectric layer, the side of the gate trench at the top of the bottom dielectric layer, and the outer surface of the gate trench. The thickness of the second dielectric layer is set to the target thickness required for the inter-gate dielectric layer. The second dielectric layer does not completely fill the gate trench and forms a first gap in the gate trench.

[0010] Step 3: Form a first mask layer, which completely fills the first gap and extends to the surface of the second dielectric layer outside the first gap.

[0011] The first mask layer is patterned, and a first opening is formed in the patterned first mask layer in the device cell region. The first opening is located on both sides of the gate trench and exposes the surface of the bottom second dielectric layer.

[0012] Step 4: Perform wet etching. In the wet etching process, the wet etching solution starts etching the second dielectric layer from the bottom surface of the first opening. Then, it gradually etches the second dielectric layer along the area defined between the first mask layer and the outer surface of the gate trench, as well as the side surface of the first mask layer and the gate trench, until the required position of the inter-gate dielectric layer is reached. The remaining second dielectric layer after the wet etching forms the inter-gate dielectric layer. The thickness of the middle region of the inter-gate dielectric layer is equal to the thickness of the second dielectric layer. The thickness of the edge region of the inter-gate dielectric layer is determined by the wet etching process. The edge region of the inter-gate dielectric layer is the region between the first mask layer and the side surface of the gate trench.

[0013] Step 5: Remove the first mask layer.

[0014] Step 6: Form a gate dielectric layer on the side of the gate trench at the top of the inter-gate dielectric layer, and fill the gate trench with a gate conductive material layer.

[0015] A further improvement is that the material of the second dielectric layer in step two includes an oxide layer.

[0016] A further improvement is that, in step two, the second dielectric layer is formed by CVD deposition or by thermal oxidation combined with CVD deposition.

[0017] A further improvement is that, in step three, the first mask layer is made of photoresist and formed by a coating process.

[0018] A further improvement is that, in step three, a photolithography process is used to pattern the first mask layer.

[0019] A further improvement is that, in step three, the first photomask used in the photolithography process is formed by creating the pattern of the first opening in the device unit area based on the second photomask in the active region.

[0020] A further improvement is that, in step one, the top view structure of the gate trench is a strip-shaped structure.

[0021] Multiple gate trenches are formed on the semiconductor substrate, and in top view, the gate trenches are arranged in parallel.

[0022] On a top view, each of the first openings and the gate trenches are parallel.

[0023] A further improvement is that multiple aligned first openings are arranged on the same side of the gate trench; the length of each first opening is shorter than the length of the gate trench, the length sides of each first opening are aligned, and the width sides of each first opening are spaced apart by material of the first mask layer to enhance the support of the first mask layer.

[0024] A further improvement is that, in step one, the semiconductor substrate includes a silicon substrate.

[0025] A further improvement is that the material of the bottom dielectric layer includes an oxide layer.

[0026] In step six, the material of the gate dielectric layer includes an oxide layer.

[0027] A further improvement is that the material of the shielding gate conductive material layer includes polycrystalline silicon.

[0028] The material of the gate conductive material layer includes polycrystalline silicon.

[0029] A further improvement is that, in step one, a first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

[0030] It also includes the following steps:

[0031] Step 7: Form a body region doped with a second conductivity type on the surface of the semiconductor substrate.

[0032] The gate conductive material layer passes through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as the channel region.

[0033] The first epitaxial layer at the bottom of the body region serves as the drift region.

[0034] Step 8: Form a heavily doped source region of the first conductivity type on the surface of the body region.

[0035] A further improvement is that, in step four, the wet etching ensures that the surface of the edge region of the formed inter-gate dielectric layer is located at the bottom of the body region.

[0036] A further improvement is that the top surface of the edge region of the inter-gate dielectric layer is equal to, higher than or lower than the top surface of the middle region of the inter-gate dielectric layer.

[0037] A further improvement is that the SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type.

[0038] Alternatively, the SGT semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0039] The inter-gate dielectric layer of this invention is formed by wet etching using a second dielectric layer formation process. The wet etching employs a first mask layer to form a first opening. Since the first opening is formed on both sides of the gate trench, the direction of wet etching can be well controlled. That is, starting from the bottom of the first opening, lateral etching is first performed along the area between the outer surface of the gate trench and the first mask layer towards the gate trench. After the lateral etching is completed, etching is performed from top to bottom along the area between the side of the gate trench and the first mask layer. Finally, the top surface of the edge region of the inter-gate dielectric layer is formed. The top surface of the middle region of the inter-gate dielectric layer remains unchanged because it is covered by the first mask layer. The overlapping area of ​​the shielding gate conductive material layer and the gate conductive material layer is mainly located in the middle region of the inter-gate dielectric layer. Since the thickness of the middle region of the inter-gate dielectric layer is not affected by wet etching but is completely determined by the formation process of the second dielectric layer, this invention can achieve the setting of the thickness of the inter-gate dielectric layer independently of the thickness of the gate dielectric layer and can precisely adjust the thickness of the inter-gate dielectric layer. Moreover, the thickness adjustment of the inter-gate dielectric layer is easy and has good repeatability, enabling stable production.

[0040] In addition, since the edge region of the inter-gate dielectric layer is located outside the overlapping region of the shielding gate conductive material layer and the gate conductive material layer, the precision requirements for wet etching in this invention are not very high. The fluctuations in wet etching will not have a significant impact on the isolation between the shielding gate conductive material layer and the gate conductive material layer. Therefore, this invention also has the advantages of simple process flow and low process difficulty, which is also conducive to achieving stable production. Attached Figure Description

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0042] Figure 1 This is a flowchart of a method for manufacturing the inter-gate dielectric layer of an SGT semiconductor device according to an embodiment of the present invention;

[0043] Figures 2A-2H This is a schematic diagram of the device cross-sectional structure in each step of the manufacturing method of the inter-gate dielectric layer of the SGT semiconductor device according to an embodiment of the present invention;

[0044] Figure 3 yes Figure 2E The corresponding top view. Detailed Implementation

[0045] like Figure 1 The diagram shown is a flowchart of a method for manufacturing the inter-gate dielectric layer 105 of an SGT semiconductor device according to an embodiment of the present invention; as shown... Figures 2A to 2H The diagram shown is a schematic cross-sectional view of the device structure in each step of the manufacturing method of the inter-gate dielectric layer 105 of the SGT semiconductor device according to an embodiment of the present invention; as shown... Figure 3 As shown, is Figure 2E The corresponding top view; the manufacturing method of the inter-gate dielectric layer 105 of the SGT semiconductor device in this embodiment of the invention includes the following steps:

[0046] Step 1, such as Figure 2A As shown, a gate trench 102 is formed on a semiconductor substrate 101.

[0047] In the process of forming the gate trench 102, a hard mask layer 201 needs to be formed first. The hard mask layer 102 is a single oxide layer or a stacked layer of oxide-nitride-oxide (ONO).

[0048] Then, photolithography is used to open the formation region of the gate trench 102 shown;

[0049] Subsequently, the hard mask layer 201 and the semiconductor substrate 101 are etched sequentially to form the gate trench 102.

[0050] like Figure 2B As shown, a bottom dielectric layer 103 and a shielding gate conductive material layer 104 are formed in the gate trench 102.

[0051] Figure 2B In the process, after filling the shielding gate conductive material layer 104, in the device cell region of the active region 109, the shielding gate conductive material layer 104 needs to be etched back to remove the shielding gate conductive material layer 104 outside the gate trench 102 and on the top of the gate trench 102, so that the shielding gate conductive material layer 104 only fills the bottom region of the gate trench 102.

[0052] like Figure 2C As shown, the bottom dielectric layer 103 then needs to be etched back so that the bottom dielectric layer 103 is located only in the bottom region of the gate trench 102 and between the shielding gate conductive material layer 104 and the gate trench 102.

[0053] In this embodiment of the invention, the semiconductor substrate 101 includes a silicon substrate.

[0054] The material of the bottom dielectric layer 103 includes an oxide layer.

[0055] The material of the shielding gate conductive material layer 104 includes polycrystalline silicon. The shielding gate conductive material layer 104 is also referred to as source polycrystalline silicon.

[0056] In some preferred embodiments, a first epitaxial layer doped with a first conductivity type is also formed on the surface of the semiconductor substrate 101, and the gate trench 102 is formed in the first epitaxial layer.

[0057] Step 2, as follows Figure 2D As shown, a second dielectric layer 105a is formed, which covers the surface of the shielding gate conductive material layer 104, the surface of the bottom dielectric layer 103, the side of the gate trench 102 at the top of the bottom dielectric layer 103, and the outer surface of the gate trench 102; the thickness of the second dielectric layer 105a is set to the target thickness required by the inter-gate dielectric layer 105, and the second dielectric layer 105a does not completely fill the gate trench 102 and forms a first gap in the gate trench 102.

[0058] In this embodiment of the invention, the material of the second dielectric layer 105a includes an oxide layer. The second dielectric layer 105a is formed by CVD deposition or by thermal oxidation combined with CVD deposition. In some embodiments, the CVD process for the second dielectric layer 105a can be a standard CVD process on a production line, without the need for complex or costly CVD processes such as HDPCVD. The thin films deposited by the CVD process include USG thin films and TEOS thin films.

[0059] Step 3, as follows Figure 2E As shown, a first mask layer 202 is formed, which completely fills the first gap and extends to the surface of the second dielectric layer 105a outside the first gap.

[0060] The first mask layer 202 is patterned, and a first opening 203 is formed in the patterned first mask layer 202 in the device cell region. The first opening 203 is located on both sides of the gate trench 102, and the first opening 203 exposes the surface of the bottom second dielectric layer 105a. Please refer to the top view of the first opening 203 and the gate trench 102. Figure 3 As shown.

[0061] In this embodiment of the invention, the first mask layer 202 is made of photoresist and is formed by a coating process.

[0062] The first mask layer 202 is patterned using photolithography.

[0063] In some preferred embodiments, the first photomask used in the photolithography process is formed by creating a pattern of the first opening 203 in the device unit region based on a second photomask in the active region 109.

[0064] like Figure 3 As shown, the top view of the gate trench 102 has a strip-shaped structure.

[0065] Multiple gate trenches 102 are formed on the semiconductor substrate 101, and in top view, the gate trenches 102 are arranged in parallel.

[0066] On a top view, each of the first openings 203 and the gate trenches 102 are parallel.

[0067] In some preferred embodiments, a plurality of aligned first openings 203 are arranged on the same side of the gate trench 102; the length of each first opening 203 is shorter than the length of the gate trench 102, the length sides of each first opening 203 are aligned, and the width sides of each first opening 203 are spaced apart by material of the first mask layer 202 to enhance the support of the first mask layer 202. Figure 3 In the middle, the material of the first mask layer 202 between the width sides of each of the first openings 203 is marked separately by a mark 202a, and the material 202a serves as a lateral support strip.

[0068] Step 4, as follows Figure 2F As shown, wet etching is performed. In the wet etching process, the wet etching solution etches the second dielectric layer 105a starting from the bottom surface of the first opening 203. Then, it gradually etches the second dielectric layer 105a along the region defined between the outer surface of the first mask layer 202 and the gate trench 102, as well as the side surface of the first mask layer 202 and the gate trench 102, until the required position of the inter-gate dielectric layer 105 is reached. The direction of the wet etching is shown by arrow line 204. The remaining second dielectric layer 105a after the wet etching constitutes the inter-gate dielectric layer 105. The thickness of the middle region of the inter-gate dielectric layer 105 is equal to the thickness of the second dielectric layer 105a. The thickness of the edge region of the inter-gate dielectric layer 105 is determined by the wet etching process. The edge region of the inter-gate dielectric layer 105 is the region between the first mask layer 202 and the side surface of the gate trench 102. Figure 2F In the diagram, the middle region of the inter-gate dielectric layer 105 is marked with a dashed box 205, and the region outside the dashed box 205 is the edge region of the inter-gate dielectric layer 105.

[0069] In some embodiments, combined with Figure 3 and Figure 2F As shown, the material 202a of the first mask layer 202 between the width sides of each of the first openings 203, i.e. the transverse support strip, will support the material of the entire first mask layer 202 during the wet etching process, preventing the first mask layer 202 from collapsing when the first opening 203 is too long.

[0070] Step 5, as follows Figure 2GAs shown, the first mask layer 202 is removed.

[0071] Step Six, as Figure 2H As shown, a gate dielectric layer 106 is formed on the side of the gate trench 102 on top of the gate dielectric layer 105, and a gate conductive material layer 107 is filled in the gate trench 102.

[0072] In this embodiment of the invention, the material of the gate dielectric layer 106 includes an oxide layer.

[0073] The gate conductive material layer 107 is made of polysilicon, and the gate conductive material layer 107 is also called a polysilicon gate.

[0074] like Figure 2H As shown, the SGT semiconductor device in this embodiment of the invention is an SGT MOSFET, and the invention further includes the following steps:

[0075] Step 7: Form a body region 108 doped with a second conductivity type on the surface of the semiconductor substrate 101.

[0076] The gate conductive material layer 107 passes through the body region 108, and the surface of the body region 108 covered by the side of the gate conductive material layer 107 serves as a channel region.

[0077] The first epitaxial layer at the bottom of the body region 108 serves as a drift region.

[0078] In step four above, the wet etching process only needs to ensure that the surface of the edge region of the formed inter-gate dielectric layer 105 is located at the bottom of the body region 108. Therefore, the requirements for the wet etching process in this embodiment of the invention are not very high; it is only necessary to ensure that the channel region can be formed. Figure 2H Although it is shown that the top surface of the edge region of the inter-gate dielectric layer 105 is higher than the top surface of the middle region of the inter-gate dielectric layer 105, in other embodiments, the top surface of the edge region of the inter-gate dielectric layer 105 may be equal to or lower than the top surface of the middle region of the inter-gate dielectric layer 105.

[0079] Step 8: Form a source region 109 with a first conductivity type heavily doped on the surface of the body region 108.

[0080] Following that, it also includes:

[0081] Formation of interlayer membrane 111;

[0082] An opening for a contact hole 112 is formed through the interlayer film 111, and a heavily doped bulk contact region 110 of the second conductivity type is formed at the bottom of the opening of the contact hole 112 at the top of the source region 109.

[0083] The contact hole 112 is formed by filling the opening of the contact hole 112 with metal. The contact hole 112 at the top of the source region 109 contacts the source region 109 and is electrically connected to the body region 108 through the body contact region 110.

[0084] A front-side metal layer 113 is formed, and the front-side metal layer 113 is patterned to form the source and gate electrodes. Both the source region 109 and the shielding gate conductive material layer 104 are connected to the source electrode through the top contact hole 112. Figure 2H Only the contact hole 112 at the top of the source region 109 is shown; the gate conductive material layer 107 is connected to the gate through the contact hole 112 at the top.

[0085] The following back-side finishes are also included:

[0086] The semiconductor substrate 101 is thinned, and then heavy doped ions of the first conductivity type are implanted on the back side to form a drain region on the back side of the drift region.

[0087] In this embodiment of the invention, the SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the SGT semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0088] In this embodiment of the invention, the inter-gate dielectric layer 105 is formed by wet etching using the same process as the second dielectric layer 105a. The wet etching utilizes a first mask layer 202 to form the first opening 203. Since the first opening 203 is formed on both sides of the gate trench 102, the direction of the wet etching can be well controlled. Specifically, starting from the bottom of the first opening 203, lateral etching is first performed along the area between the outer surface of the gate trench 102 and the first mask layer 202, moving towards the gate trench 102. After the lateral etching is completed, top-down etching is then performed along the side of the gate trench 102 and the area between the first mask layer 202, ultimately forming the top edge region of the inter-gate dielectric layer 105. The top surface of the middle region of the inter-gate dielectric layer 105 remains unchanged because it is covered by the first mask layer 202. The overlapping area of ​​the shielding gate conductive material layer 104 and the gate conductive material layer 107 is mainly located in the middle region of the inter-gate dielectric layer 105. Since the thickness of the middle region of the inter-gate dielectric layer 105 is not affected by wet etching but is completely determined by the formation process of the second dielectric layer 105a, the embodiment of the present invention can realize that the thickness of the inter-gate dielectric layer 105 can be set independently of the thickness of the gate dielectric layer 106 and the thickness of the inter-gate dielectric layer 105 can be precisely adjusted. Moreover, the thickness adjustment of the inter-gate dielectric layer 105 is easy and has good repeatability, enabling stable production.

[0089] Furthermore, since the edge region of the inter-gate dielectric layer 105 is located outside the overlapping region of the shielding gate conductive material layer 104 and the gate conductive material layer 107, the precision requirements for wet etching in this embodiment of the invention are not very high. Fluctuations in wet etching will not have a significant impact on the isolation between the shielding gate conductive material layer 104 and the gate conductive material layer 107. Therefore, this embodiment of the invention also has the advantages of simple process flow and low process difficulty, which is also conducive to achieving stable production.

[0090] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing an inter-gate dielectric layer of an SGT semiconductor device, characterized in that, Includes the following steps: Step 1: Form a gate trench on a semiconductor substrate, and form a bottom dielectric layer and a shielding gate conductive material layer in the gate trench; in the device cell region of the active region, the shielding gate conductive material layer fills the bottom of the gate trench and the bottom dielectric layer is isolated between the shielding gate conductive material layer and the gate trench; Step 2: Form a second dielectric layer. The second dielectric layer covers the surface of the shielding gate conductive material layer, the surface of the bottom dielectric layer, the side of the gate trench at the top of the bottom dielectric layer, and the outer surface of the gate trench. The thickness of the second dielectric layer is set to the target thickness required for the inter-gate dielectric layer. The second dielectric layer does not completely fill the gate trench and forms a first gap in the gate trench. Step 3: Form a first mask layer, which completely fills the first gap and extends to the surface of the second dielectric layer outside the first gap; The first mask layer is patterned, and a first opening is formed in the patterned first mask layer in the device cell region. The first opening is located on both sides of the gate trench and exposes the surface of the bottom second dielectric layer. Step 4: Perform wet etching. In the wet etching, the wet etching solution starts etching the second dielectric layer from the bottom surface of the first opening, and then gradually etches the second dielectric layer along the area defined between the first mask layer and the outer surface of the gate trench, as well as the side surface of the first mask layer and the gate trench, until the required position of the inter-gate dielectric layer is reached. The remaining second dielectric layer after the wet etching forms the inter-gate dielectric layer. The thickness of the middle region of the inter-gate dielectric layer is equal to the thickness of the second dielectric layer. The thickness of the edge region of the inter-gate dielectric layer is determined by the wet etching. The edge region of the inter-gate dielectric layer is the region between the first mask layer and the side surface of the gate trench. Step 5: Remove the first mask layer; Step 6: Form a gate dielectric layer on the side of the gate trench at the top of the inter-gate dielectric layer, and fill the gate trench with a gate conductive material layer.

2. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: The material of the second dielectric layer in step two includes an oxide layer.

3. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 2, characterized in that: In step two, the second dielectric layer is formed by CVD deposition or by thermal oxidation combined with CVD deposition.

4. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step three, the first mask layer is formed using photoresist and a coating process.

5. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 4, characterized in that: In step three, photolithography is used to pattern the first mask layer.

6. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 5, characterized in that: In step three, the first photomask used in the photolithography process is formed by creating the pattern of the first opening in the device unit area based on the second photomask in the active region.

7. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 6, characterized in that: In step one, the top view of the gate trench is a strip-shaped structure; Multiple gate trenches are formed on the semiconductor substrate, and in top view, the gate trenches are arranged in parallel. On a top view, each of the first openings and the gate trenches are parallel.

8. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 7, characterized in that: Multiple aligned first openings are arranged on the same side of the gate trench; the length of each first opening is shorter than the length of the gate trench, the length sides of each first opening are aligned, and the width sides of each first opening are spaced apart by material of the first mask layer to enhance the support of the first mask layer.

9. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, the semiconductor substrate includes a silicon substrate.

10. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 9, characterized in that: The material of the bottom dielectric layer includes an oxide layer; In step six, the material of the gate dielectric layer includes an oxide layer.

11. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: The material of the conductive material layer of the shielding gate includes polycrystalline silicon; The material of the gate conductive material layer includes polycrystalline silicon.

12. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, a first epitaxial layer doped with a first conductivity type is also formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer; It also includes the following steps: Step 7: Form a bulk region doped with a second conductivity type on the surface of the semiconductor substrate; The gate conductive material layer passes through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as the channel region. The first epitaxial layer at the bottom of the body region serves as the drift region; Step 8: Form a heavily doped source region of the first conductivity type on the surface of the body region.

13. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 12, characterized in that: In step four, the wet etching ensures that the surface of the edge region of the formed inter-gate dielectric layer is located at the bottom of the body region.

14. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 13, characterized in that: The top surface of the edge region of the inter-gate dielectric layer is equal to, higher than or lower than the top surface of the middle region of the inter-gate dielectric layer.

15. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 12, characterized in that: SGT semiconductor devices are N-type devices, with N-type as the first conductivity type and P-type as the second conductivity type; Alternatively, the SGT semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

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