Refrigeration infrared detector and preparation method of indium column thereof

Abstract

The application provides a refrigeration infrared detector and a preparation method of an indium column thereof, and is applied to the technical field of semiconductors. Specifically, the indium column formed on the device chip is concave or convex, and the indium column formed on the readout circuit chip is convex or concave, so that the indium columns formed on the device chip and the readout circuit chip are concave and convex respectively, thereby avoiding side sliding and displacement caused by the contact of the top ends of the indium columns during the process of forming the refrigeration infrared detector by means of flip-chip interconnection of the device chip and the readout circuit chip, so that the pressure of the indium columns formed on the device chip and the readout circuit chip can be slowly released during flip-chip, and the contact area of the two is increased, thereby ensuring that the physical connection and electrical connection of the readout circuit chip and the device chip can meet the process requirements, and finally avoiding the problem of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a cooled infrared detector and a method for fabricating its indium pillar. Background Technology

[0002] With the continuous promotion and development of infrared applications, advanced infrared detection technology requires detectors to have higher spatial resolution and better target recognition capabilities. An infrared detector is an optoelectronic device that converts infrared radiation into electronic signals. The photoelectric reaction occurs only on the photosensitive element, while the subsequent signal processing involves only electronic technology. Therefore, the infrared detection chip is the core component of an infrared detector.

[0003] Since current CMOS integrated circuit technology is primarily based on Si technology, infrared detection chips need to be hybrid integrated with Si readout circuits using indium pillar flip-chip bonding technology to form an integrated detector module consisting of a photosensitive chip and a readout circuit. Corresponding indium pillar electrodes are fabricated on each pixel structure. By aligning and pressing the pixels of the readout circuit with those of the photosensitive chip, a reliable electrical connection is formed between the readout circuit pixels and the photosensitive chip pixels through indium pillar-to-indium pillar van der Waals forces or indium pillar-to-indium pillar / metal electrode thermal fusion bonding, achieving hybrid integration. Therefore, the size, morphology, and consistency of the indium pillars directly determine the interconnection connectivity between the readout circuit chip and the photosensitive chip.

[0004] Currently, infrared detectors are developing towards a center-to-center spacing of 15µm, 1024x1024 devices, and a chip area of ​​17mmx17mm. Therefore, as infrared detectors develop towards larger pixel scales and smaller center-to-center spacing, the number of flip-soldering points needs to reach over a million, which drastically increases the difficulty of flip-soldering. Furthermore, although fabricating indium spheres on both sides of the readout circuit and the photosensitive chip can compensate to some extent for the decrease in connectivity caused by the reduction in center-to-center spacing and indium pillar size, the special size and morphology of the indium spheres and the mutual constraints between the pressure and time parameters of the flip-soldering interconnection process can lead to indium sphere misalignment and lateral slippage after flip-soldering between the readout circuit and the photosensitive chip. This results in the physical and electrical connections between the readout circuit and the photosensitive chip failing to meet process requirements, ultimately causing device failure. Summary of the Invention

[0005] The purpose of this invention is to provide a cooled infrared detector and a method for fabricating its indium spheres, in order to solve the problem in the prior art where the indium spheres are misaligned and slipped after the readout circuit and the device chip are flip-wired due to the special size and morphology of the indium spheres and the mutual constraints between the pressure and time parameters of the flip-wire interconnection process. This results in the physical and electrical connections between the readout circuit and the device chip failing to meet the process requirements, and ultimately causing device failure.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for preparing an indium pillar for a cooled infrared detector, comprising the following steps:

[0007] S1, a chip is provided, wherein the chip is a device chip of the cooled infrared detector or a readout circuit chip of the cooled infrared detector;

[0008] S2, depositing a dielectric material layer on a portion of the chip surface to form at least one trench surrounded by the dielectric material layer and the exposed top surface of the chip, the trench having a concave cross-sectional shape perpendicular to the top surface of the chip;

[0009] S3, depositing an indium pillar material layer in the trench to form concave indium pillars on the surface of the chip.

[0010] Furthermore, the dielectric material layer may include photoresist or SU-8 adhesive and lift-off photoresist with curing properties.

[0011] Furthermore, the dielectric material layer may also include a silicon dioxide layer, a silicon nitride layer, or a ethyl silicate layer.

[0012] Furthermore, the device chip provided in step S1 may also have multiple device isolation structures and PN junction structures separated by the device isolation structures, as well as electrodes located on the top surface of the device chip corresponding to the PN junction structures for electrically leading out the PN junction structures.

[0013] Furthermore, the indium pillar can be a hollow closed ring or other irregular shape, and the hollow closed ring includes a circular ring, an elliptical ring or a polygonal ring.

[0014] The indium pillar can also be a positioning pillar array composed of positioning pillars located at the four corners of the trench, and the cross-sectional shape of the positioning pillar array perpendicular to the top surface of the chip is concave.

[0015] Furthermore, the step of forming the trench in step S2 may include:

[0016] S2.1, A first photoresist layer is formed on the device chip, a first opening is formed in the first photoresist layer, and the electrode formed on the device chip is exposed from the first opening;

[0017] S2.2, A first metal layer is formed in the first opening, the top surface of the first metal layer being lower than the top surface of the first photoresist layer;

[0018] S2.3, a second photoresist layer is formed on a portion of the surface of the first metal layer, so that the first photoresist layer, the second photoresist layer and the exposed first metal layer form two second openings;

[0019] S2.4, deposit a second metal layer or a non-metallic dielectric material layer in the second opening, and remove the second photoresist layer to form two metal blocks at the edge position of the electrode surface exposed in the first opening, and the top surface of the metal blocks is lower than the top surface of the first photoresist layer.

[0020] The step of forming the indium pillar in step S3 may include:

[0021] S3.1, deposit an indium pillar material layer in the first opening to form an indium pillar with a hollow closed ring shape in the first opening;

[0022] S3.2, Remove the first photoresist layer.

[0023] Furthermore, the step of forming the trench in step S2 may include:

[0024] S2.1, an SU-8 adhesive layer is formed on the device chip, a third opening is formed in the SU-8 adhesive layer, and the electrode formed on the device chip is exposed from the third opening;

[0025] S2.2, a third metal layer is formed in the third opening, the top surface of the third metal layer being lower than the top surface of the SU-8 adhesive layer;

[0026] S2.3, A lift-off photoresist layer is formed on the device chip, and a fourth opening is formed in the lift-off photoresist layer so that a portion of the surface of the third metal layer is exposed from the fourth opening;

[0027] The step of forming the indium pillar in step S3 may include:

[0028] S3.1, deposit an indium pillar material layer on the top surface of the Lift-off photoresist layer, the bottom surface of the fourth opening, and the sidewalls to form indium pillars with a hollow closed ring shape on the device chip.

[0029] Furthermore, the step of forming the trench in step S2 may include:

[0030] S2.1, A third photoresist layer is formed on the device chip, a fifth opening is formed in the third photoresist layer, and the electrode formed on the device chip is exposed from the fifth opening;

[0031] S2.2, a fourth metal layer is formed in the fifth opening, the top surface of the fourth metal layer being lower than the top surface of the third photoresist layer;

[0032] S2.3, a fourth photoresist layer is formed on a portion of the surface of the fourth metal layer, so that the third photoresist layer, the fourth photoresist layer and the exposed fourth metal layer form two sixth openings;

[0033] The step of forming the indium pillar in step S3 may include:

[0034] S3.1, depositing indium pillar material layers on the top surfaces of the third and fourth photoresist layers, as well as on the bottom and sidewalls of the sixth opening, to form an indium pillar array consisting of the plurality of positioning pillars on the device chip.

[0035] Secondly, based on the above-described method for fabricating the indium pillar of a cooled infrared detector, this invention provides a method for fabricating a cooled infrared detector, which may specifically include the following steps:

[0036] S1, a device chip for forming the cooled infrared detector and a readout circuit chip for forming the cooled infrared detector are provided, wherein a plurality of PN junction structures are formed on the device chip;

[0037] S2, forming indium pillars with a concave or convex shape on the device chip, and forming indium pillars with a convex or concave shape on the readout circuit chip, to ensure that the indium pillars formed on the device chip and the readout circuit chip are respectively concave and convex.

[0038] S3. Using a flip-flop interconnect process, the device chip and the readout circuit chip are interconnected through the indium pillars to obtain a cooled infrared detector.

[0039] Thirdly, based on the preparation method of the cooled infrared detector described above, the present invention provides a cooled infrared detector, which can be specifically manufactured using the preparation method of the cooled infrared detector described above.

[0040] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0041] In the present invention, a method for fabricating an indium pillar for a cooled infrared detector is provided. By forming a concave or convex indium pillar on the device chip used to form the cooled infrared detector, and forming a convex or concave indium pillar on the readout circuit chip used to form the cooled infrared detector, the shape of the indium pillars formed on the device chip and the readout circuit chip is ensured to be concave and convex respectively. This avoids the side slippage and displacement caused by the contact between the tips of the indium pillars formed on the device chip and the readout circuit chip during the flip-soldering interconnect process to form the cooled infrared detector. This allows the pressure of the indium pillars formed on the device chip and the readout circuit chip to be released slowly during flip-soldering, while increasing the contact area between them. This ensures that the physical and electrical connection between the readout circuit chip and the device chip meets the process requirements and ultimately avoids device problems. Attached Figure Description

[0042] Figure 1 This is a schematic flowchart of a method for preparing a cooled infrared detector indium pillar according to an embodiment of the present invention.

[0043] Figures 2a to 2f This is a schematic diagram of the fabrication process of the indium pillar of the cooled infrared detector in one embodiment of the present invention.

[0044] Figures 3a-3b This is a schematic diagram of the fabrication process of the indium pillar of the cooled infrared detector in another embodiment of the present invention.

[0045] Figures 4a to 4d This is a schematic diagram of the fabrication process of the indium pillar of the cooled infrared detector in another embodiment of the present invention.

[0046] Figure 5 This is a top view of an indium pillar with a hollow, annular shape, as shown in one embodiment of the present invention.

[0047] Figure 6 This is a top view of an indium pillar with a hollow, square-shaped structure formed in one embodiment of the present invention;

[0048] Figure 7 This is a top view of an indium column with a cross-shaped structure formed in one embodiment of the present invention;

[0049] Figure 8 This is a schematic flowchart illustrating the fabrication method of a cooled infrared detector according to an embodiment of the present invention.

[0050] The reference numerals in the attached figures are as follows:

[0051] 100 - Device chip; 110 - First photoresist layer;

[0052] 101 - First opening; 120 - First metal layer;

[0053] 130 - Second photoresist layer; 102 - Second opening;

[0054] 140 - Metal block; 150 - Indium pillar with a hollow, closed ring shape;

[0055] 210-SU-8 adhesive layer; 201-third opening;

[0056] 220 - Third metal layer; 230 - Lift-off photoresist layer;

[0057] 202 - Fourth opening; 240 - Indium pillar with a hollow, closed ring shape;

[0058] 310 - Third photoresist layer; 320 - Fourth metal layer;

[0059] 330 - Fourth photoresist layer; 302 - Sixth opening;

[0060] 340 - Indium pillar material layer; 340' - Indium pillar array of positioning pillars composed of the plurality of positioning pillars. Detailed Implementation

[0061] As described in the background section, with the continuous promotion and development of infrared applications, advanced infrared detection technology requires detectors to have higher spatial resolution and better target recognition capabilities. An infrared detector is an optoelectronic device that converts infrared radiation into electronic signals. The photoelectric reaction occurs only on the photosensitive element, while subsequent signal processing involves only electronic technology. Therefore, the infrared detection chip is the core component of an infrared detector.

[0062] Since current CMOS integrated circuit technology is mainly based on Si technology, infrared detection chips need to be hybrid integrated with Si readout circuits using indium pillar flip-chip bonding technology to form an integrated detector module consisting of a photosensitive chip and a readout circuit. The traditional indium pillar fabrication process involves depositing a thin layer of gold electrode as the underlayer on metal electrodes such as chromium, platinum, or nickel, and then fabricating the indium pillars using photolithography and metal evaporation. Corresponding indium pillar electrodes are fabricated on each pixel structure. By aligning and pressing the pixels of the readout circuit with those of the photosensitive chip, a reliable electrical connection is formed between the readout circuit pixels and the photosensitive chip pixels through indium pillar-to-indium van der Waals forces or indium pillar-to-indium / metal electrode thermal fusion bonding, achieving hybrid integration. Therefore, the size, morphology, and consistency of the indium pillars directly determine the interconnection connectivity between the readout circuit chip and the photosensitive chip. In the mid-1990s, foreign countries had already developed megapixel-level HgCdTe infrared detectors with a pixel size of 1024×1024 and a center-to-center distance of 30 micrometers. Currently, infrared detectors are developing towards a center-to-center spacing of 15µm, a 1024x1024 pixel size, and a chip area of ​​17mmx17mm. Therefore, as infrared detectors develop towards larger pixel sizes and smaller center-to-center spacing, the number of flip-soldering points needs to reach over a million, drastically increasing the difficulty of flip-soldering. Furthermore, although fabricating indium spheres on both sides of the readout circuit and the photosensitive chip can compensate to some extent for the decrease in connectivity caused by the reduced center-to-center spacing and indium pillar size, the special size and morphology of the indium spheres, along with the mutual constraints between the pressure and time parameters of the flip-soldering interconnection process, can lead to indium sphere misalignment and slippage after flip-soldering. This results in the physical and electrical connections between the readout circuit and the photosensitive chip failing to meet process requirements, ultimately causing device failure.

[0063] To address this issue, the present invention provides a cooled infrared detector and a method for fabricating its indium spheres, thereby solving the problem in the prior art where the indium spheres are misaligned and slipped after the readout circuit and the device chip are flip-wired due to the special size and morphology of the indium spheres and the mutual constraints between the pressure and time parameters of the flip-wire interconnection process. This results in the physical and electrical connections between the readout circuit and the device chip failing to meet process requirements, ultimately leading to device failure.

[0064] refer to Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating an indium pillar of a cooled infrared detector according to an embodiment of the present invention. The method includes the following steps:

[0065] Step S1: Provide a chip, wherein the chip is a device chip of the cooled infrared detector or a readout circuit chip of the cooled infrared detector;

[0066] Step S2, depositing a dielectric material layer on a portion of the chip surface to form at least one trench surrounded by the dielectric material layer and the exposed top surface of the chip, wherein the cross-sectional shape of the trench perpendicular to the top surface of the chip is concave.

[0067] Step S3: Deposit an indium pillar material layer in the trench to form concave indium pillars on the surface of the chip.

[0068] In the present invention, a method for fabricating an indium pillar for a cooled infrared detector is provided. This method involves forming concave or convex indium pillars on the device chip used to form the cooled infrared detector, and forming convex or concave indium pillars on the readout circuit chip used to form the cooled infrared detector. This ensures that the indium pillars formed on the device chip and the readout circuit chip are concave and convex respectively. This avoids slippage and displacement caused by the tip-to-tip contact of the indium pillars formed on the device chip and the readout circuit chip during the flip-soldering interconnection process to form the cooled infrared detector. Furthermore, this method allows for slow pressure release during flip-soldering of the indium pillars on the device chip and the readout circuit chip, while increasing their contact area. This ensures that the physical and electrical connections between the readout circuit chip and the device chip meet process requirements and ultimately avoids device problems.

[0069] The cooled infrared detector and its indium pillar fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0070] Figures 2a to 2f This is a schematic diagram of the fabrication process of the indium pillar of the cooled infrared detector in one embodiment of the present invention.

[0071] In step S1, a chip is provided. This chip can be a device chip for the cooled infrared detector or a readout circuit chip for the cooled infrared detector. For example, in this embodiment of the invention, the chip is device chip 100. Figure 2aAs shown; wherein, the device chip 100 is a substrate having formed a plurality of device isolation structures and PN junction or NP junction structures A separated by the device isolation structures, and electrodes (not shown) for electrically leading out the PN junction or NP junction structures are also formed on the top surface of the substrate corresponding to the PN junction or NP junction structures. Exemplarily, in this embodiment of the invention, for ease of description, the junction structure formed in the substrate material of the device chip 100 is assumed to be a PN junction in the following description.

[0072] It is understandable that the process of forming a PN junction structure in a substrate involves implanting N-type or P-type ions into a P-type or N-type substrate, such as... Figure 2a As shown in region A, a PN junction or NP junction structure is formed at the junction of the P-type substrate and the N-type ion implantation region. This is prior art, and the present invention does not specifically limit it.

[0073] In this embodiment, to address the problem in the prior art where the size and morphology of the indium balls, along with the mutual constraints between the pressure and time parameters of the flip-flop interconnection process, lead to indium ball misalignment and slippage after flip-flop bonding between the readout circuit and the device chip, resulting in insufficient physical and electrical connections between the readout circuit and the device chip to meet process requirements, this invention proposes fabricating concave indium pillars on the device chip used for cooled infrared detectors or on the readout circuit chip used for cooled infrared detectors, while fabricating convex indium pillars on another chip. This increases the contact area between the two after flip-flop bonding, thereby ensuring that the physical and electrical connections between the readout circuit chip and the device chip meet process requirements. Since the formation process of the convex indium pillars is prior art, this invention will not elaborate on it. Furthermore, for ease of understanding, this invention explains its innovation by describing the process of forming concave indium pillars on the device chip; therefore, the process of forming concave indium pillars on the readout circuit chip is the same and will not be elaborated upon here.

[0074] In step S2, please refer to the following for details. Figures 2b to 2f As shown or Figures 3a-3b As shown or Figures 4a to 4d As shown, a dielectric material layer is deposited on a portion of the surface of the chip to form at least one trench enclosed by the dielectric material layer and the exposed top surface of the chip, the trench having a concave cross-sectional shape perpendicular to the top surface of the chip.

[0075] The dielectric material layer may include photoresist, or may include SU-8 photoresist and Lift-off photoresist with curing properties; and when the dielectric material layer includes SU-8 photoresist and Lift-off photoresist with curing properties, the dielectric material layer may also include a silicon dioxide layer, a silicon nitride layer or an ethyl silicate layer.

[0076] In this embodiment, when the chip is a device chip, its concave indium pillars are formed above the electrodes already formed on the device chip for electrically leading out the PN junction structure. Specifically, a dielectric material layer can be formed above the electrodes first, and then photolithography and / or etching processes can be performed on the dielectric material layer to form trenches for depositing the indium pillar material. The specific number of trenches formed depends on the number of PN junction structures formed on the device chip.

[0077] It is understood that, since this invention proposes various patterns of concave indium pillars, correspondingly, when forming the grooves, it is necessary to form grooves of specific shapes for different patterns of concave indium pillars. The concave indium pillars can be hollow closed loops or other irregular shapes, and the hollow closed loops include circular rings, elliptical rings, or polygonal rings, such as... Figure 5 The top view is a hollow ring or Figure 6 The top view shown is a hollow, square-shaped structure; alternatively, the concave indium pillar can be an array of positioning pillars composed of positioning pillars located at the four corners of the groove, such as... Figure 7 The top view shown is a cross structure, and the cross-sectional shape of the positioning column array perpendicular to the top surface of the chip is concave.

[0078] Specifically, when the concave indium pillar is a hollow closed ring, the present invention provides a specific implementation of a groove for forming the concave indium pillar with the hollow closed ring shape, which may include the following steps:

[0079] S2.1, see details. Figure 2b As shown, a first photoresist layer 110 is formed on the device chip 100, and a first opening 101 is formed in the first photoresist layer 110, so that the electrode (not shown) formed on the device chip 100 is exposed from the first opening 101;

[0080] S2.2, see details. Figure 2c As shown, a first metal layer 120 is formed in the first opening 101, and the top surface of the first metal layer 120 is lower than the top surface of the first photoresist layer 110.

[0081] S2.3, see also Figure 2c As shown, a second photoresist layer 130 is formed on a portion of the surface of the first metal layer 120, so that the first photoresist layer 110, the second photoresist layer 130 and the exposed first metal layer 120 form two second openings 102.

[0082] S2.4, see details. Figure 2dAs shown, a second metal layer is deposited in the second opening 102, and the second photoresist layer 130 is removed to form two metal blocks 140 at the edge of the electrode surface exposed in the first opening 101, with the top surface of the metal blocks 140 lower than the top surface of the first photoresist layer 110. The second metal layer can be a non-metallic dielectric material layer, such as a silicon dioxide layer or a silicon nitride layer. Exemplarily, a metal layer is used as an example in this embodiment of the invention.

[0083] In this embodiment, a photoresist layer can first be formed on the device chip corresponding to the PN junction structure. Then, the photoresist layer is exposed and developed to form an opening, namely the first opening 101, thereby exposing the electrodes on the device chip. Since the electrodes are not shown in this invention, the accompanying drawings provided in this embodiment all show the PN junction structure of the device chip directly exposed from the first opening 101. A first metal layer 120 and a photoresist layer are then sequentially formed on the surface of the PN junction structure exposed in the first opening 101. The material of the metal layer can be a metal such as copper or aluminum. Then, the photoresist layer formed on the surface of the first metal layer 120 is exposed and developed so that it only covers the middle portion of the surface of the first metal layer 120 (forming the second photoresist layer 130), thereby exposing the partial surfaces of the two side edges of the first metal layer 120 to form two second openings 102. A second metal layer is deposited in the second opening 102 to form a concave trench. Finally, an indium pillar material layer is deposited in the concave trench to form a hollow, closed-loop indium pillar 150. The first photoresist layer 110 is then removed. Figure 2f As shown.

[0084] Due to the embodiments of the present invention, Figure 2b In the structure shown, the height of the first photoresist 110 formed is higher than the height of the second metal layer 120, so that the shape of the trench formed in step S2.4 is a concave trench, so that the indium pillars formed in the concave trench by the deposition process are also concave, thereby achieving the inventive objective of the present invention.

[0085] Alternatively, when the concave indium pillar is a hollow closed ring, the present invention also provides another implementation of the groove for forming the concave indium pillar with the hollow closed ring shape, which may specifically include the following steps:

[0086] S2.1, see details. Figure 3aAs shown, an SU-8 adhesive layer 210 is formed on the device chip 100, and a third opening 201 is formed in the SU-8 adhesive layer 210, exposing the electrode (not shown) formed on the device chip 100 through the third opening 201;

[0087] S2.2, see also Figure 3a As shown, a third metal layer 220 is formed in the third opening 201, and the top surface of the third metal layer 220 is lower than the top surface of the SU-8 adhesive layer 210;

[0088] S2.3, see details. Figure 3b As shown, a lift-off photoresist layer 230 is formed on the device chip 100, and a fourth opening 202 is formed in the lift-off photoresist layer 230 so that a portion of the surface of the third metal layer 220 is exposed from the fourth opening 202.

[0089] In this embodiment, a SU-8 adhesive layer 210 with a curing function is first formed on the device chip with a PN junction structure to form a U-shaped trench (third opening 201) on the device chip 100. Then, a metal layer 220 is deposited in the U-shaped trench. Next, a Lift-off photoresist layer 230 is deposited at both ends of the U-shaped trench to form a recess with a narrowed opening (fourth opening 202). Finally, an indium pillar material layer is deposited on the top surface of the Lift-off photoresist layer 230, the bottom of the fourth opening 202, and the sidewalls to form an indium pillar 240 with a hollow closed ring shape on the device chip 100.

[0090] In this embodiment of the invention, a concave trench is formed on the surface of the device chip using photolithography and / or etching processes with a curing SU-8 adhesive layer 210 and a lift-off photoresist 230. Then, indium pillar material is deposited in the concave trench to ultimately form a concave indium pillar 240. Because the SU-8 adhesive layer has a curing effect, it does not need to be removed during the subsequent formation of the concave trench, thus serving as part of the concave trench. This saves on process steps, speeds up manufacturing, and reduces manufacturing costs.

[0091] It is understood that the SU-8 adhesive and Lift-off photoresist can be replaced with a silicon dioxide layer, a silicon nitride layer, or a ethyl silicate layer.

[0092] Furthermore, when the concave indium pillar is a positioning pillar array composed of positioning pillars located at the four corners of the groove, the present invention provides a specific implementation of a groove for forming a concave indium pillar array composed of positioning pillars located at the four corners of the groove, which may include the following steps:

[0093] S2.1, see details. Figure 4a As shown, a third photoresist layer 310 is formed on the device chip 100, and a fifth opening 301 is formed in the third photoresist layer 310, so that the electrode (not shown) formed on the device chip 100 is exposed from the fifth opening 301;

[0094] S2.2, see also Figure 4a As shown, a fourth metal layer 320 is formed in the fifth opening 301, and the top surface of the fourth metal layer 320 is lower than the top surface of the third photoresist layer 310.

[0095] S2.3, see details. Figure 4b As shown, a fourth photoresist layer 330 is formed on a portion of the surface of the fourth metal layer 320, so that the third photoresist layer 310, the fourth photoresist layer 330 and the exposed fourth metal layer 320 form two sixth openings 302.

[0096] In this embodiment, photoresist or curable SU-8 adhesive and lift-off photoresist can be used to form four columnar positioning pillars (a total of four) at the four corners of a certain range on a device chip with a PN junction structure. No two adjacent positioning pillars are adjacent, thus forming a cross-shaped structure in the top view (e.g., ...). Figure 7 As shown), the back-shaped structure (such as...) Figure 6 As shown), brackets (not shown), and other structures, while the cross-sectional view along the direction perpendicular to the surface of the device chip shows a concave groove structure, such as... Figure 4b As shown, subsequently, an indium pillar material layer 340 is filled into the sixth opening 302 in the groove of the concave structure to form an indium pillar array consisting of the plurality of positioning pillars on the device chip, as shown. Figure 4d The diagram shows 340'. The top view of the positioning pillar array of indium pillars is a cross structure, while the cross-sectional view along the direction perpendicular to the surface of the device chip is a concave structure.

[0097] In step S3, please refer to the following for details. Figure 2e or Figure 3b or Figure 4c As shown, an indium pillar material layer is deposited in the trench to form concave indium pillars on the surface of the chip.

[0098] In addition, refer to Figure 8 , Figure 8 This is a schematic flowchart illustrating a method for fabricating a cooled infrared detector according to an embodiment of the present invention. Figure 8 As shown, based on the above-described method for fabricating the indium pillar of a cooled infrared detector, this invention also provides a method for fabricating a cooled infrared detector, which specifically includes the following steps:

[0099] S1, a device chip for forming the cooled infrared detector and a readout circuit chip for forming the cooled infrared detector are provided, wherein a plurality of PN junction structures are formed on the device chip;

[0100] S2, forming indium pillars with a concave or convex shape on the device chip, and forming indium pillars with a convex or concave shape on the readout circuit chip, to ensure that the indium pillars formed on the device chip and the readout circuit chip are respectively concave and convex.

[0101] S3. Using a flip-flop interconnect process, the device chip and the readout circuit chip are interconnected through the indium pillars to obtain a cooled infrared detector.

[0102] Furthermore, based on the fabrication method of the cooled infrared detector described above, the present invention also provides a cooled infrared detector. The cooled infrared detector can be fabricated using the fabrication method described above.

[0103] In summary, the present invention provides a method for fabricating an indium pillar for a cooled infrared detector. By forming concave or convex indium pillars on the device chip used to form the cooled infrared detector, and forming convex or concave indium pillars on the readout circuit chip used to form the cooled infrared detector, the indium pillars formed on the device chip and the readout circuit chip are ensured to be concave and convex respectively. This avoids the side slippage and displacement caused by the contact between the tips of the indium pillars formed on the device chip and the readout circuit chip during the flip-soldering interconnect process to form the cooled infrared detector. This allows the pressure on the indium pillars formed on the device chip and the readout circuit chip to be released slowly during flip-soldering, while increasing the contact area between them. This ensures that the physical and electrical connections between the readout circuit chip and the device chip meet the process requirements and ultimately avoids device problems.

[0104] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of protection of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of protection of the present invention.

[0105] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0106] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0107] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating an indium pillar for a cooled infrared detector, characterized in that, Includes the following steps: S1, a chip is provided, wherein the chip is a device chip of the cooled infrared detector or a readout circuit chip of the cooled infrared detector; S2, depositing a dielectric material layer on a portion of the chip surface to form at least one trench surrounded by the dielectric material layer and the exposed top surface of the chip, the trench having a concave cross-sectional shape perpendicular to the top surface of the chip; S3, depositing an indium pillar material layer in the trench to form concave indium pillars on the surface of the chip; The dielectric material layer includes photoresist or SU-8 photoresist and lift-off photoresist with curing properties; The device chip provided in step S1 also has a plurality of device isolation structures and PN junction structures separated by the device isolation structures, as well as electrodes located on the top surface of the device chip corresponding to the PN junction structures for electrically leading out the PN junction structures. The indium pillar is a hollow closed ring, and the hollow closed ring includes a circular ring, an elliptical ring, or a polygonal ring; or, the indium pillar is a positioning pillar array composed of positioning pillars located at the four corners of the trench, and the cross-sectional shape of the positioning pillar array perpendicular to the top surface of the chip is concave. When the indium pillar is a hollow closed ring, and the hollow closed ring includes a circular ring, an elliptical ring, or a polygonal ring, the step of forming the groove in step S2 includes: S2.1, A first photoresist layer is formed on the device chip, a first opening is formed in the first photoresist layer, and the electrode formed on the device chip is exposed from the first opening; S2.2, A first metal layer is formed in the first opening, the top surface of the first metal layer being lower than the top surface of the first photoresist layer; S2.3, a second photoresist layer is formed on a portion of the surface of the first metal layer, so that the first photoresist layer, the second photoresist layer and the exposed first metal layer form two second openings; S2.4, deposit a second metal layer or a non-metallic dielectric material layer in the second opening, and remove the second photoresist layer to form two metal blocks at the edge position of the electrode surface exposed in the first opening, and the top surface of the metal blocks is lower than the top surface of the first photoresist layer. The step of forming the indium pillar in step S3 includes: S3.1, deposit an indium pillar material layer in the first opening to form an indium pillar with a hollow closed ring shape in the first opening; S3.2, Remove the first photoresist layer; or The step of forming the trench in step S2 includes: S2.1, an SU-8 adhesive layer is formed on the device chip, a third opening is formed in the SU-8 adhesive layer, and the electrode formed on the device chip is exposed from the third opening; S2.2, a third metal layer is formed in the third opening, the top surface of the third metal layer being lower than the top surface of the SU-8 adhesive layer; S2.3, A lift-off photoresist layer is formed on the device chip, and a fourth opening is formed in the lift-off photoresist layer so that a portion of the surface of the third metal layer is exposed from the fourth opening; The step of forming the indium pillar in step S3 includes: S3.1, deposit an indium pillar material layer on the top surface of the Lift-off photoresist layer, the bottom surface of the fourth opening, and the sidewalls to form an indium pillar with a hollow closed ring shape on the device chip; When the indium pillar is a positioning pillar array composed of positioning pillars located at the four corners of the trench, and the cross-sectional shape of the positioning pillar array perpendicular to the top surface of the chip is concave, the step of forming the trench in step S2 includes: S2.1, A third photoresist layer is formed on the device chip, a fifth opening is formed in the third photoresist layer, and the electrode formed on the device chip is exposed from the fifth opening; S2.2, a fourth metal layer is formed in the fifth opening, the top surface of the fourth metal layer being lower than the top surface of the third photoresist layer; S2.3, a fourth photoresist layer is formed on a portion of the surface of the fourth metal layer, so that the third photoresist layer, the fourth photoresist layer and the exposed fourth metal layer form two sixth openings; The step of forming the indium pillar in step S3 includes: S3.1, depositing indium pillar material layers on the top surfaces of the third and fourth photoresist layers, as well as on the bottom and sidewalls of the sixth opening, to form an array of indium pillars consisting of a plurality of the positioning pillars on the device chip.

2. The method for preparing the indium pillar of the cooled infrared detector as described in claim 1, characterized in that, The dielectric material layer further includes a silicon dioxide layer, a silicon nitride layer, or a ethyl silicate layer.

3. A method for fabricating a cooled infrared detector, characterized in that, Includes the following steps: A device chip for forming the cooled infrared detector and a readout circuit chip for forming the cooled infrared detector are provided, wherein a plurality of PN junction structures are formed on the device chip; Indium pillars with concave or convex shapes are formed on the device chip, and indium pillars with convex or concave shapes are formed on the readout circuit chip, to ensure that the indium pillars formed on the device chip and the readout circuit chip are respectively concave and convex. Using a flip-flop interconnect process, the device chip and the readout circuit chip are interconnected via the indium pillars to obtain a cooled infrared detector; wherein the step of forming the concave indium pillars includes: S2 deposits a dielectric material layer on a portion of the chip surface to form at least one trench enclosed by the dielectric material layer and the exposed top surface of the chip, the trench having a concave cross-sectional shape perpendicular to the top surface of the chip; S3, depositing an indium pillar material layer in the trench to form concave indium pillars on the surface of the chip; The dielectric material layer includes photoresist or SU-8 photoresist and Lift-off photoresist with curing properties; an electrode for electrically leading out the PN junction structure is also formed on the top surface of the device chip corresponding to the PN junction structure; The indium pillar is a hollow closed ring, and the hollow closed ring includes a circular ring, an elliptical ring, or a polygonal ring; or, the indium pillar is a positioning pillar array composed of positioning pillars located at the four corners of the trench, and the cross-sectional shape of the positioning pillar array perpendicular to the top surface of the chip is concave. When the indium pillar is a hollow closed ring, and the hollow closed ring includes a circular ring, an elliptical ring, or a polygonal ring, the step of forming the groove in step S2 includes: S2.1, A first photoresist layer is formed on the device chip, a first opening is formed in the first photoresist layer, and the electrode formed on the device chip is exposed from the first opening; S2.2, A first metal layer is formed in the first opening, the top surface of the first metal layer being lower than the top surface of the first photoresist layer; S2.3, a second photoresist layer is formed on a portion of the surface of the first metal layer, so that the first photoresist layer, the second photoresist layer and the exposed first metal layer form two second openings; S2.4, deposit a second metal layer or a non-metallic dielectric material layer in the second opening, and remove the second photoresist layer to form two metal blocks at the edge position of the electrode surface exposed in the first opening, and the top surface of the metal blocks is lower than the top surface of the first photoresist layer. The step of forming the indium pillar in step S3 includes: S3.1, deposit an indium pillar material layer in the first opening to form an indium pillar with a hollow closed ring shape in the first opening; S3.2, Remove the first photoresist layer; or The step of forming the trench in step S2 includes: S2.1, an SU-8 adhesive layer is formed on the device chip, a third opening is formed in the SU-8 adhesive layer, and the electrode formed on the device chip is exposed from the third opening; S2.2, a third metal layer is formed in the third opening, the top surface of the third metal layer being lower than the top surface of the SU-8 adhesive layer; S2.3, A lift-off photoresist layer is formed on the device chip, and a fourth opening is formed in the lift-off photoresist layer so that a portion of the surface of the third metal layer is exposed from the fourth opening; The step of forming the indium pillar in step S3 includes: S3.1, deposit an indium pillar material layer on the top surface of the Lift-off photoresist layer, the bottom surface of the fourth opening, and the sidewalls to form an indium pillar with a hollow closed ring shape on the device chip; When the indium pillar is a positioning pillar array composed of positioning pillars located at the four corners of the trench, and the cross-sectional shape of the positioning pillar array perpendicular to the top surface of the chip is concave, the step of forming the trench in step S2 includes: S2.1, A third photoresist layer is formed on the device chip, a fifth opening is formed in the third photoresist layer, and the electrode formed on the device chip is exposed from the fifth opening; S2.2, a fourth metal layer is formed in the fifth opening, the top surface of the fourth metal layer being lower than the top surface of the third photoresist layer; S2.3, a fourth photoresist layer is formed on a portion of the surface of the fourth metal layer, so that the third photoresist layer, the fourth photoresist layer and the exposed fourth metal layer form two sixth openings; The step of forming the indium pillar in step S3 includes: S3.1, depositing indium pillar material layers on the top surfaces of the third and fourth photoresist layers, as well as on the bottom and sidewalls of the sixth opening, to form an array of indium pillars consisting of a plurality of the positioning pillars on the device chip.

4. A cooled infrared detector, characterized in that, It is manufactured using the method described in claim 3 for preparing a cooled infrared detector.

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