Light-emitting diode with improved luminous efficiency and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode with improved luminous efficiency and a method for preparing the same, which belongs to the field of optoelectronic manufacturing technology. The method for preparing the light-emitting diode includes providing a substrate; growing an n-type layer on the substrate; alternately growing multiple quantum well layers and multiple quantum barrier layers on the n-type layer to form a light-emitting layer; growing a p-type layer on the light-emitting layer; wherein the quantum well layer is formed in the following manner: forming a first InGaN layer; introducing hydrogen into the reaction chamber to form a second InGaN layer on the first InGaN layer; stopping the introduction of hydrogen to form a third InGaN layer on the second InGaN layer. The embodiments of the present disclosure can improve the electron-hole recombination efficiency and enhance the luminous efficiency of the light-emitting diode.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved luminous efficiency and a preparation method thereof. Background Art

[0002] As a new product with great influence in the optoelectronics industry, light emitting diode (LED) has the characteristics of small size, long service life, rich colors and low energy consumption, and is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields. The core structure of LED is epitaxial wafer, and the production of epitaxial wafer has a great influence on the optoelectronic characteristics of LED.

[0003] Epitaxial wafers usually include: substrate, n-type layer, light-emitting layer and p-type layer, which are stacked on the substrate in sequence. Electrons in the n-type layer will migrate to the light-emitting layer, and holes in the p-type layer will migrate to the light-emitting layer. Holes and electrons recombine in the light-emitting layer to emit light. Therefore, allowing more holes and electrons to recombine in the light-emitting layer is of great significance to improving the luminous efficiency of light-emitting diodes. Summary of the invention

[0004] The embodiment of the present disclosure provides a light-emitting diode with improved luminous efficiency and a method for preparing the same, which can improve the electron-hole recombination efficiency and enhance the luminous efficiency of the light-emitting diode. The technical solution is as follows:

[0005] On the one hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: providing a substrate; growing an n-type layer on the substrate; alternately growing a plurality of quantum well layers and a plurality of quantum barrier layers on the n-type layer to form a light-emitting layer; growing a p-type layer on the light-emitting layer; wherein the quantum well layer is formed in the following manner: forming a first InGaN layer; introducing hydrogen into a reaction chamber to form a second InGaN layer on the first InGaN layer; and stopping introducing hydrogen to form a third InGaN layer on the second InGaN layer.

[0006] Optionally, when hydrogen is introduced into the reaction chamber, the flow rate of hydrogen is controlled to be 5 sccm to 30 sccm, and the introduction time is controlled to be 5 s to 20 s.

[0007] Optionally, the forming of the first InGaN layer includes: introducing ammonia, ethylgallium and trimethylindium into the reaction chamber for a period of 30s to 60s; the forming of the second InGaN layer on the first InGaN layer also includes: introducing ammonia, ethylgallium and trimethylindium into the reaction chamber while introducing hydrogen for a period of 5s to 20s; the forming of the third InGaN layer on the second InGaN layer includes: introducing ammonia, ethylgallium and trimethylindium into the reaction chamber for a period of 30s to 60s.

[0008] Optionally, the growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0009] Optionally, the growth temperature of the quantum barrier layer is 850° C. to 950° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0010] Optionally, before alternately growing a plurality of quantum well layers and a plurality of quantum barrier layers on the n-type layer, the method further includes: growing a shallow well layer on the n-type layer, the shallow well layer comprising a plurality of InGaN potential well layers and a plurality of GaN potential barrier layers, and the plurality of InGaN potential well layers and the plurality of GaN potential barrier layers are alternately stacked.

[0011] On the other hand, an embodiment of the present disclosure provides a light-emitting diode, which includes a substrate, an n-type layer, a light-emitting layer and a p-type layer stacked in sequence; the light-emitting layer includes a plurality of quantum well layers and a plurality of quantum barrier layers, the plurality of quantum well layers and the plurality of quantum barrier layers are alternately stacked, each of the quantum well layers includes a first InGaN layer, a second InGaN layer and a third InGaN layer stacked in sequence, the content of hydrogen element in the second InGaN layer is greater than the content of hydrogen element in the first InGaN layer and / or the content of hydrogen element in the third InGaN layer.

[0012] Optionally, the hydrogen content in the second InGaN layer is greater than 5.5×10 17 Atom / cm 3 .

[0013] Optionally, the content of hydrogen in the second InGaN layer is not less than 1×10 18 Atom / cm 3 .

[0014] Optionally, the light-emitting layer includes 8 to 12 quantum well layers and 8 to 12 quantum barrier layers.

[0015] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0016] In the light-emitting diode of the disclosed embodiment, when growing the quantum well layer, the first InGaN layer is formed first; then hydrogen is introduced into the reaction chamber to form the second InGaN layer on the first InGaN layer; then, the introduction of hydrogen is stopped to form the third InGaN layer on the second InGaN layer. When growing the second InGaN layer, hydrogen is introduced. This can effectively reduce the number and size of hillocks in the In-rich region and disperse the density of V-shaped pits, reduce non-radiative recombination of carriers, and improve luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0019] Figure 2 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 3 It is a schematic diagram of growth parameters of a single quantum well layer provided in an embodiment of the present disclosure.

[0021] The descriptions of the marks in the figure are as follows:

[0022] 10. Substrate;

[0023] 20. n-type layer;

[0024] 30, light-emitting layer; 31, quantum well layer; 311, first InGaN layer; 312, second InGaN layer; 313, third InGaN layer; 32, quantum barrier layer;

[0025] 40. p-type layer; 41. low-temperature p-type GaN layer; 42. p-type AlGaN layer; 43. high-temperature p-type GaN layer; 44. p-type ohmic contact layer;

[0026] 51. buffer layer; 52. undoped GaN layer;

[0027] 60. Shallow well layer; 61. In x Ga 1-x N potential well layer; 62. GaN barrier layer. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0029] Figure 1 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode includes a substrate 10, an n-type layer, a light emitting layer 30 and a p-type layer 40 which are stacked in sequence.

[0030] like Figure 1 As shown, the light-emitting layer 30 includes a plurality of quantum well layers 31 and a plurality of quantum barrier layers 32, and the plurality of quantum well layers 31 and the plurality of quantum barrier layers 32 are alternately stacked, and each quantum well layer 31 includes a first InGaN layer 311, a second InGaN layer 312 and a third InGaN layer 313 stacked in sequence, and the content of hydrogen elements in the second InGaN layer 312 is greater than the content of hydrogen elements in the first InGaN layer 311 and / or the content of hydrogen elements in the third InGaN layer 313.

[0031] The light-emitting diode of the embodiment of the present disclosure includes a substrate 10, an n-type layer, a light-emitting layer 30 and a p-type layer 40 stacked in sequence, and the light-emitting layer 30 includes a quantum well layer 31 and a quantum barrier layer 32 stacked alternately. Among them, the quantum well layer 31 includes a first InGaN layer 311, a second InGaN layer 312 and a third InGaN layer 313 stacked in sequence. Among them, when growing the second InGaN layer 312, hydrogen can be introduced so that the content of hydrogen in the second InGaN layer 312 is greater than the content of hydrogen in the first InGaN layer 311 and / or the content of hydrogen in the third InGaN layer 313. In this way, the number and size of hillocks in the In-rich region and the density of dispersed V-shaped pits can be effectively reduced, the non-radiative recombination of carriers can be reduced, and the luminous efficiency can be improved.

[0032] Optionally, the substrate 10 is a sapphire substrate 10, a silicon substrate 10 or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0033] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a common substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a sapphire flat sheet substrate 10.

[0034] Optionally, the n-type layer may be an n-type GaN layer. The thickness of the n-type layer is 1.5 μm to 3.5 μm. The dopant of the n-type layer is silane.

[0035] Optionally, the p-type layer 40 may include a low-temperature p-type GaN layer 41, a p-type AlGaN layer 42, a high-temperature p-type GaN layer 43 and a p-type ohmic contact layer 44 sequentially stacked on the light-emitting layer 30. The dopant of the p-type layer 40 is bis(cyclopentadienyl)magnesium.

[0036] For example, the low-temperature p-type GaN layer 41 may be a GaN layer grown at a temperature of 700° C. to 800° C., and the high-temperature p-type GaN layer 43 may be a GaN layer grown at a temperature of 900° C. to 1050° C. Both the low-temperature p-type GaN layer 41 and the high-temperature p-type GaN layer 43 are doped with Mg.

[0037] The thickness of the low-temperature p-type GaN layer may be 30 nm to 120 nm. For example, the thickness of the low-temperature p-type GaN layer may be 100 nm.

[0038] The thickness of the high temperature p-type GaN layer 43 may be 50 nm to 150 nm. For example, the thickness of the high temperature p-type GaN layer 43 may be 100 nm.

[0039] In the embodiment of the present disclosure, the p-type AlGaN layer 42 serves as an electron blocking layer for blocking electrons from entering the p-type layer 40. Both the p-type AlGaN layer 42 and the p-type ohmic contact layer 44 are doped with Mg.

[0040] Optionally, the thickness of the p-type AlGaN layer 42 may be 50 nm to 150 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type AlGaN layer 42 is 80 nm.

[0041] If the thickness of the p-type AlGaN layer 42 is too thin, the blocking effect on electrons will be reduced. If the thickness of the p-type AlGaN layer 42 is too thick, the absorption of light by the p-type AlGaN layer 42 will increase, thereby reducing the luminous efficiency of the LED.

[0042] Optionally, the thickness of the p-type ohmic contact layer 44 may be 3 nm to 10 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type ohmic contact layer 44 is 8 nm.

[0043] If the thickness of the p-type ohmic contact layer 44 is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the thickness of the p-type ohmic contact layer 44 is too thick, it will increase the absorption of light by the p-type ohmic contact layer 44, thereby reducing the luminous efficiency of the LED.

[0044] In the embodiment of the present disclosure, the thickness of the quantum well layer 31 in the light emitting layer 30 is 2 nm to 5 nm.

[0045] By controlling the thickness of the quantum well layer 31 within the above range, it is possible to avoid the quantum well layer 31 being too thin to achieve the purpose of electron-hole recombination; it is also possible to avoid the quantum well layer 31 being too thick to increase the manufacturing cost.

[0046] Exemplarily, the thickness of the quantum well layer 31 may be 3 nm, wherein the thickness of the first InGaN layer 311 is 1 nm, the thickness of the second InGaN layer 312 is 1 nm, and the thickness of the third InGaN layer 313 is 1 nm.

[0047] Optionally, the quantum barrier layer 32 may be an n-type GaN quantum barrier layer 32 with a thickness of 5 nm to 15 nm.

[0048] By controlling the thickness of the n-type GaN quantum barrier layer 32 within the above range, it is possible to avoid setting the thickness of the n-type GaN quantum barrier layer 32 too thin to achieve the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the n-type GaN quantum barrier layer 32 too thick to increase the manufacturing cost.

[0049] Exemplarily, the thickness of the n-type GaN quantum barrier layer 32 is 10 nm.

[0050] Optionally, the light emitting layer 30 includes 8 to 12 quantum well layers 31 and 8 to 12 quantum barrier layers 32 .

[0051] By controlling the number of quantum well layers 31 and quantum barrier layers 32 within the above range, it is possible to avoid setting the number of quantum well layers 31 and quantum barrier layers 32 too small, which would result in the thickness of the light-emitting layer 30 being too small and failing to achieve the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the light-emitting layer 30 too thick and increasing the production cost.

[0052] By way of example, the number of layers of the quantum well layer 31 may be 10, and the number of layers of the quantum barrier layer 32 may be 10.

[0053] It should be noted that Figure 1 Only a part of the structure of the light emitting layer 30 is shown, and it is not intended to limit the number of cycles of the alternate stacking of the quantum well layer 31 and the quantum barrier layer 32 .

[0054] Optionally, the hydrogen content in the first InGaN layer 311 and the third InGaN layer 313 is 5.5×10 17 Atom / cm 3 to 6.5×10 17 Atom / cm 3 .

[0055] For example, the content of hydrogen in the first InGaN layer 311 and the third InGaN layer 313 is 6×10 17 Atom / cm3 .

[0056] Optionally, the hydrogen content in the second InGaN layer 312 is greater than 5.5×10 17 Atom / cm 3 .

[0057] For example, the hydrogen content in the second InGaN layer 312 is 7×10 17 Atom / cm 3 .

[0058] Optionally, the content of hydrogen in the second InGaN layer 312 is not less than 1×10 18 Atom / cm 3 .

[0059] For example, the hydrogen content in the second InGaN layer 312 is 1.1×10 18 Atom / cm 3 .

[0060] In this way, the hydrogen content in the second InGaN layer is controlled to be higher than that in the first InGaN layer and the third InGaN layer, which can effectively reduce the number and size of hillocks in the In-rich region and disperse the density of V-pits, reduce non-radiative recombination of carriers, and improve luminescence efficiency.

[0061] Alternatively, if Figure 1 As shown, a buffer layer 51 and a non-doped GaN layer 52 are further included between the substrate 10 and the p-type layer 40 . The buffer layer 51 and the non-doped GaN layer 52 are sequentially stacked on the substrate 10 .

[0062] In the embodiment of the present disclosure, the buffer layer 51 may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 500° C. and 650° C.

[0063] The thickness of the buffer layer 51 may be 2 nm to 8 nm. For example, the thickness of the buffer layer 51 may be 5 nm.

[0064] By setting the thickness of the buffer layer 51 within the above range, it is possible to avoid the buffer layer 51 being too thin, thereby reducing the crystal quality of the epitaxial layer grown on the thinner buffer layer 51; it is also possible to avoid the buffer layer 51 being too thick, thereby increasing the absorption of light by the buffer layer 51, thereby reducing the luminous efficiency of the epitaxial wafer.

[0065] In an embodiment of the present disclosure, an undoped GaN layer 52 is further grown between the buffer layer 51 and the n-type layer. Compared with the substrate 10, since the crystal structure of the undoped GaN layer 52 is similar to that of the n-type layer, by setting the undoped GaN layer 52 as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0066] Among them, the thickness of the undoped GaN layer 52 is 1 μm to 2 μm. Exemplarily, the thickness of the undoped GaN layer 52 is 1.5 μm.

[0067] By setting the thickness of the undoped GaN layer 52 within the above range, it is possible to avoid the thickness of the undoped GaN layer 52 being too thin to play a transition role and reduce the crystal quality of the grown epitaxial layer; it is also possible to avoid the thickness of the undoped GaN layer 52 being too thick, which will increase the light absorption of the undoped GaN layer 52, thereby reducing the light emission efficiency of the epitaxial wafer.

[0068] Optionally, as Figure 1 shown, a shallow well layer 60 is further included between the n-type layer and the light-emitting layer 30.

[0069] Among them, the shallow well layer 60 may include 5 to 20 successively overlapping In x Ga 1-x N(0 < x < 0.1) well layers 61 and GaN barrier layers 62.

[0070] Exemplarily, the thickness of the In x Ga 1-x N well layer 61 is 1 nm to 4 nm. For example, the thickness of the In x Ga 1-x N well layer 61 is 3 nm.

[0071] Exemplarily, the thickness of the GaN barrier layer 62 is 10 nm to 30 nm. For example, the thickness of the GaN barrier layer 62 is 20 nm.

[0072] In the above implementation, the shallow well layer 60 adopts a superlattice structure formed by multiple successively alternating In x Ga 1-x N well layers 61 and GaN barrier layers 62. The superlattice structure can be used to relieve the lattice mismatch between heterogeneous materials, which is beneficial to improving the overall crystal quality of the epitaxial wafer and ultimately improving the light emission efficiency of the LED.

[0073] Figure 2 is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure. This method is used to manufacture Figure 1 the epitaxial wafer shown. As Figure 2 shown, this manufacturing method includes:

[0074] S11: Provide a substrate.

[0075] S12: growing an n-type layer on the substrate.

[0076] S13: growing a light-emitting layer on the n-type layer.

[0077] The light-emitting layer includes multiple quantum well layers and multiple quantum barrier layers, which are alternately stacked. Each quantum well layer includes a first InGaN layer, a second InGaN layer and a third InGaN layer stacked in sequence. When the second InGaN layer is grown, hydrogen is introduced.

[0078] S14: growing a p-type layer on the light-emitting layer.

[0079] In the light-emitting diode prepared by the preparation method, when growing the quantum well layer, the first InGaN layer is formed first; then hydrogen is introduced into the reaction chamber to form a second InGaN layer on the first InGaN layer; then, the introduction of hydrogen is stopped to form a third InGaN layer on the second InGaN layer. When growing the second InGaN layer, hydrogen is introduced to make the content of hydrogen in the second InGaN layer greater than the content of hydrogen in the first InGaN layer and / or the content of hydrogen in the third InGaN layer. This can effectively reduce the number and size of hillocks in the In-rich region and disperse the density of V-shaped pits, reduce non-radiative recombination of carriers, and improve luminous efficiency.

[0080] In step S11, the substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0081] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0082] In step S11, the sapphire substrate may be subjected to a high temperature cleaning treatment in a hydrogen atmosphere at 1000° C. to 1200° C. for 5 min to 20 min, and then subjected to a nitridation treatment.

[0083] In step S11, the sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0084] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0085] Before step S12, the following steps may also be included:

[0086] In the first step, a buffer layer is grown on the substrate.

[0087] In the embodiment of the present disclosure, the buffer layer may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 500° C. and 650° C.

[0088] The thickness of the buffer layer may be 2 nm to 8 nm. For example, the thickness of the buffer layer may be 5 nm.

[0089] Specifically, after the high-temperature treatment of the sapphire substrate is completed, the temperature is dropped to 500°C to 650°C, and a low-temperature GaN buffer layer with a thickness of 2nm to 8nm is first grown. Then the temperature is increased to 1000°C to 1100°C, and annealing is performed for 3min to 10min. The growth pressure is 50Torr to 200Torr, V / III is 50 to 300, and the rotation speed is 200r / min to 600r / min.

[0090] In the second step, a non-doped GaN layer is grown on the buffer layer.

[0091] In the embodiment of the present disclosure, an undoped GaN layer is also grown between the buffer layer and the n-type layer. Compared with the substrate, since the crystal structure of the undoped GaN layer is similar to that of the n-type layer, the crystal quality of the subsequent epitaxial layer can be improved by providing the undoped GaN layer as a transition layer.

[0092] The thickness of the non-doped GaN layer is 1 μm to 2 μm. For example, the thickness of the non-doped GaN layer is 1.5 μm.

[0093] Specifically, after the growth of the low-temperature GaN buffer layer is completed, the temperature is adjusted to 1000° C. to 1200° C., and an epitaxial non-doped GaN layer with a thickness of 1 μm to 2 μm is grown. The growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 200 to 3000.

[0094] Step S12 may include: growing an n-type layer on the non-doped GaN layer.

[0095] Optionally, the n-type layer may be an n-type GaN layer. The thickness of the n-type layer is 1.5 μm to 3.5 μm. The dopant of the n-type layer is silane.

[0096] Specifically, after the growth of the undoped GaN layer, an n-type GaN layer with a stable Si doping concentration is grown, having a thickness of 1.5 μm to 3.5 μm, a growth temperature of 950 °C to 1150 °C, a growth pressure of 300 Torr to 500 Torr, and a V / III ratio of 400 to 3000.

[0097] Before step S13, it further includes: growing a shallow well layer on the n-type layer.

[0098] Among them, the shallow well layer may include 5 to 20 successively overlapping In x Ga 1-x N (0 < x < 0.1) well layers and GaN barrier layers.

[0099] Exemplarily, the thickness of the In x Ga 1-x N well layer is 1 nm to 4 nm. For example, the thickness of the In x Ga 1-x N well layer is 3 nm.

[0100] Exemplarily, the thickness of the GaN barrier layer is 10 nm to 30 nm. For example, the thickness of the GaN barrier layer is 20 nm.

[0101] Specifically, after the growth of the n-type doped GaN layer, a shallow well layer is grown. Among them, the growth temperature of the In x Ga 1-x N well layer is 750 °C to 850 °C, the growth pressure is 100 Torr to 500 Torr, the thickness is 1 nm to 4 nm, and the V / III ratio is 500 to 10000. The growth temperature of the GaN barrier layer is 850 °C to 950 °C, the growth pressure is 100 Torr to 500 Torr, the V / III ratio is 500 to 10000, and the thickness is 10 nm to 30 nm.

[0102] Step S13 may include: growing a light-emitting layer on the shallow well layer.

[0103] Specifically, after the growth of the shallow well layer, alternately stacked quantum well layers and quantum barrier layers are grown.

[0104] Among them, the quantum well layer is an In y Ga 1-y N (0.1 < y < 0.3) layer. The quantum well layer may include successively stacked first InGaN layer, second InGaN layer, and third InGaN layer.

[0105] Figure 3 It is a schematic diagram of the growth parameters of a single quantum well layer provided by an embodiment of the present disclosure. As Figure 3As shown, when growing the first InGaN layer, ammonia, ethylgallium and trimethylindium are introduced into the reaction chamber for 30s to 60s.

[0106] When growing the second InGaN layer, hydrogen is introduced into the reaction chamber, the flow rate of hydrogen is controlled to be 5 sccm to 30 sccm, and the introduction time is 5 s to 20 s.

[0107] Wherein, ammonia, ethylgallium and trimethylindium are introduced into the reaction chamber simultaneously with the introduction of hydrogen, and the introduction time is 5s to 20s.

[0108] When growing the third InGaN layer, ammonia, ethylgallium and trimethylindium are introduced into the reaction chamber for 30s to 60s.

[0109] When growing the quantum well layer, the growth temperature in the reaction chamber is controlled to be 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, the V / III ratio is 2000 to 20000, and the thickness is 2 nm to 5 nm.

[0110] Exemplarily, the thickness of the quantum well layer may be 3 nm, wherein the thickness of the first InGaN layer is 1 nm, the thickness of the second InGaN layer is 1 nm, and the thickness of the third InGaN layer is 1 nm.

[0111] In the embodiment of the present disclosure, the quantum barrier layer may be an n-type GaN quantum barrier layer.

[0112] When growing the quantum barrier layer, the growth temperature in the reaction chamber is controlled to be 850° C. to 950° C., the growth pressure is controlled to be 100 Torr to 500 Torr, the V / III ratio is controlled to be 2000 to 20000, and the thickness is controlled to be 5 nm to 15 nm.

[0113] Exemplarily, the thickness of the n-type GaN quantum barrier layer is 10 nm.

[0114] Optionally, the number of quantum well layers and the number of quantum barrier layers are both 8 to 12. Exemplarily, the number of quantum well layers and the number of quantum barrier layers are both 10.

[0115] Step S14 may include: growing a p-type layer on the light-emitting layer.

[0116] Optionally, the thickness of the p-type layer is 30 nm to 120 nm. The dopant of the p-type layer is bis(cyclopentadienyl)magnesium.

[0117] The p-type layer may include a low-temperature p-type GaN layer, a p-type AlGaN layer, a high-temperature p-type GaN layer and a p-type ohmic contact layer sequentially stacked on the light-emitting layer. Both the low-temperature p-type GaN layer and the high-temperature p-type GaN layer are doped with Mg.

[0118] The thickness of the low-temperature p-type GaN layer may be 30 nm to 120 nm. For example, the thickness of the low-temperature p-type GaN layer may be 100 nm.

[0119] The thickness of the high temperature p-type GaN layer may be 50 nm to 150 nm, for example, the thickness of the low temperature p-type GaN layer may be 100 nm.

[0120] In the embodiment of the present disclosure, the p-type AlGaN layer is used as an electron blocking layer to block electrons from entering the p-type layer. Both the p-type AlGaN layer and the p-type ohmic contact layer are doped with Mg.

[0121] Optionally, the thickness of the p-type AlGaN layer may be 50 nm to 150 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type AlGaN layer is 80 nm.

[0122] Optionally, the thickness of the p-type ohmic contact layer may be 3 nm to 10 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type ohmic contact layer is 8 nm.

[0123] Specifically, after the growth of the light-emitting layer is completed, a low-temperature p-type GaN layer with a thickness of 30nm to 120nm is grown, the growth temperature is 700°C to 800°C, the growth time is 3min to 15min, the pressure is 100Torr to 600Torr, and the V / III ratio is 1000 to 4000.

[0124] After the growth of the low-temperature p-type GaN layer is completed, a p-type AlGaN layer with a thickness of 50nm to 150nm is grown, the growth temperature is 900°C to 1000°C, the growth time is 4min to 15min, the growth pressure is 50Torr to 300Torr, and the V / III ratio is 1000 to 10000.

[0125] After the growth of the p-type AlGaN layer is completed, a high-temperature p-type GaN layer with a thickness of 50nm to 150nm is grown, the growth temperature is between 900℃ and 1050℃, the growth time is 10min to 20min, the growth pressure is 100Torr to 500Torr, and the V / III ratio is 500 to 4000.

[0126] After the growth of the high-temperature p-type GaN layer is completed, a p-type ohmic contact layer with a thickness of 3nm to 10nm is grown, the growth temperature is 700℃ to 850℃, the growth time is 0.5min to 5min, the growth pressure is 100Torr to 500Torr, and the V / III ratio is 10000 to 20000.

[0127] After step S14, the preparation method may further include: annealing the epitaxial wafer.

[0128] After the epitaxial growth is completed, the temperature of the reaction chamber is lowered to 600℃ to 900℃, and annealing treatment is carried out in PN2 atmosphere for 10min to 30min, and then gradually lowered to room temperature. Subsequently, a single 22×35mil chip is made through subsequent processing such as cleaning, deposition, photolithography and etching.

[0129] In specific implementation, the embodiments of the present disclosure can use high-purity H2 and / or N2 as carrier gas, TEGa or TMGa as Ga source, TMIn as In source, SiH4 as n-type dopant, TMAl as aluminum source, ammonia as N source, and Cp2Mg as p-type dopant.

[0130] The luminous effect of the epitaxial wafer is explained through the following examples:

[0131] In the first example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 5s; the growth time of the third InGaN layer is 30s to 60s.

[0132] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0133] In the second example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 10s; the growth time of the third InGaN layer is 30s to 60s.

[0134] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0135] In the third example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 15s; the growth time of the third InGaN layer is 30s to 60s.

[0136] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0137] In the fourth example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 20s; the growth time of the third InGaN layer is 30s to 60s.

[0138] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0139] In the fifth example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 25s; the growth time of the third InGaN layer is 30s to 60s.

[0140] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0141] In the sixth example, a single quantum well layer includes three InGaN layers from bottom to top, and the growth time of the first InGaN layer is 30s to 60s; when the second InGaN layer grows, hydrogen is introduced with a flow rate of 15sccm for 30s; the growth time of the third InGaN layer is 30s to 60s.

[0142] The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0143] In the seventh example, the quantum well layer is a single-layer InGaN layer in the related art. When growing the InGaN layer, no hydrogen is introduced, and the growth temperature of the quantum well layer is 700°C to 850°C, the growth pressure is 100Torr to 500Torr, and the V / III ratio is 2000 to 20000.

[0144] The light emitting diode is made into a single LED chip with a size of 22×35mil through semiconductor processes such as cleaning, deposition, photolithography and etching. After testing the LED chip, it was found that compared with Example 7, the luminous efficiency of Examples 1 to 6 increased by 0.7%, 0.9% and 1% respectively. However, as the amount of hydrogen introduced continued to increase, the increase in luminous efficiency decreased. Examples 4, 5 and 6 increased by 0.6%, 0.1% and -0.46% respectively. When the hydrogen was introduced for 30S, the luminous efficiency decreased significantly. The reason for the decrease in luminous efficiency is that the blocking effect of excessive hydrogen on In doping is significantly enhanced.

[0145] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; growing an n-type layer on the substrate; Alternatingly growing a plurality of quantum well layers and a plurality of quantum barrier layers on the n-type layer to form a light-emitting layer; growing a p-type layer on the light-emitting layer; Wherein, the quantum well layer is formed in the following manner: forming a first InGaN layer; Introducing hydrogen into the reaction chamber to form a second InGaN layer on the first InGaN layer; The introduction of hydrogen gas is stopped, and a third InGaN layer is formed on the second InGaN layer.

2. The preparation method according to claim 1, characterized in that: When hydrogen is introduced into the reaction chamber, the flow rate of hydrogen is controlled to be 5 sccm to 30 sccm, and the introduction time is controlled to be 5 s to 20 s.

3. The preparation method according to claim 2, characterized in that: The forming of the first InGaN layer comprises: introducing ammonia, ethyl gallium and trimethyl indium into the reaction chamber for a period of 30 seconds to 60 seconds; The forming of the second InGaN layer on the first InGaN layer further comprises: introducing ammonia, ethyl gallium and trimethyl indium into the reaction chamber while introducing hydrogen, the introduction time being 5s to 20s; The forming of the third InGaN layer on the second InGaN layer comprises: introducing ammonia, ethyl gallium and trimethyl indium into a reaction chamber for a period of 30 seconds to 60 seconds.

4. The preparation method according to claim 1, characterized in that: The growth temperature of the quantum well layer is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The growth temperature of the quantum barrier layer is 850° C. to 950° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

6. The preparation method according to any one of claims 1 to 4, characterized in that: Before the multiple quantum well layers and multiple quantum barrier layers are alternately grown on the n-type layer, the method further comprises: A shallow well layer is grown on the n-type layer, wherein the shallow well layer includes a plurality of InGaN potential well layers and a plurality of GaN barrier layers, and the plurality of InGaN potential well layers and the plurality of GaN barrier layers are alternately stacked.

7. A light emitting diode, characterized in that: The light-emitting diode comprises a substrate (10), an n-type layer (20), a light-emitting layer (30) and a p-type layer (40) which are stacked in sequence; The light-emitting layer (30) comprises a plurality of quantum well layers (31) and a plurality of quantum barrier layers (32), wherein the plurality of quantum well layers (31) and the plurality of quantum barrier layers (32) are alternately stacked, and each of the quantum well layers (31) comprises a first InGaN layer (311), a second InGaN layer (312) and a third InGaN layer (313) stacked in sequence, wherein the content of hydrogen in the second InGaN layer (312) is greater than the content of hydrogen in the first InGaN layer (311) and / or the content of hydrogen in the third InGaN layer (313).

8. The light emitting diode according to claim 7, characterized in that: The hydrogen content in the second InGaN layer (312) is greater than 5.5×10 17 Atom / cm 3 .

9. The light emitting diode according to claim 7, characterized in that: The content of hydrogen in the second InGaN layer (312) is not less than 1×10 18 Atom / cm 3 .

10. The light emitting diode according to any one of claims 7 to 9, characterized in that: The light-emitting layer (30) includes 8 to 12 quantum well layers (31) and 8 to 12 quantum barrier layers (32).

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