Micro light emitting element and method for manufacturing the same

Abstract

The application discloses a micro light emitting element and a preparation method thereof, which moves an ITO process forward, combines ITO / MESA photolithography, simplifies a process flow, reduces ITO over-etching caused by ITO and MESA pattern overlay deviation, forms MESA / DE patterns through secondary uniform coating, photolithography and one-time ICP etching without removing glue, reduces one-time ICP etching and reduces chip manufacturing cost, and increases a SiO2 mask layer, which effectively protects a P-type gallium nitride layer and an ITO conductive layer in the process of ICP etching, avoids ICP over-etching damage to the P-type gallium nitride layer and the ITO conductive layer, and through the preparation method disclosed in the embodiment of the application, the process is simplified, the chip manufacturing cost is reduced, and the effective area of the chip is increased.

Description

Technical Field

[0001] This application relates to the field of optoelectronic device technology, and more specifically, to a micro-light-emitting element and its fabrication method. Background Technology

[0002] LEDs are semiconductor devices that convert electrical energy into light energy. Due to their advantages such as small size, long lifespan, rich colors, and low energy consumption, they are widely used in lighting, displays, backlighting, and other fields. MiniLEDs, as sub-millimeter light-emitting diodes, typically have a size of 80-200µm. They represent a new generation of LED technology, inheriting the high efficiency, high reliability, high brightness, and fast response time of small-pitch LEDs, while also having lower power consumption and cost compared to small-pitch LEDs.

[0003] Currently, Mini LEDs adopt a flip-chip structure. The existing Mini LED fabrication process is as follows: First, MESA etching is performed, that is, after a positive photoresist mask, ICP etching is used to expose the N-GaN mesa; then, DE etching is performed, that is, after MESA etching, a positive photoresist mask is used again, and ICP is used for deep etching to achieve device separation between Mini LEDs; finally, after DE etching, ITO is prepared as a current conducting layer, and ITO pattern is etched by ITO photolithography.

[0004] The existing Mini LED fabrication process has the following problems:

[0005] 1. The process involves three photolithography steps: two ICP etching steps and one ITO etching step to form MESA, DE, and ITO patterns respectively. This process is complex and costly.

[0006] 2. The smaller the chip size, the more likely it is to use a positive photoresist mask. Due to the thicker positive photoresist mask, the higher the exposure energy on the upper surface, the more severe the diffraction will be. After high-temperature baking, the morphology of the photoresist will change significantly. This will lead to the etching pattern deformation caused by the overlap of ITO and MESA, as well as the problem of over-etching of ITO. Summary of the Invention

[0007] In view of this, this application provides a micro-light-emitting element and its fabrication method to solve the problems of complex processes, high costs, and the tendency for pattern deformation and over-etching to occur as the fabrication size becomes smaller in existing micro-light-emitting element fabrication methods.

[0008] To address the above problems, embodiments of the present invention provide the following technical solutions:

[0009] The first aspect of this invention provides a method for fabricating a micro-light-emitting element, the method comprising:

[0010] An LED epitaxial chip is provided, the LED epitaxial chip comprising a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer;

[0011] An ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip;

[0012] Two spin coating processes are performed on a portion of the SiO2 mask layer. After the first spin coating, a MESA pattern is formed by photolithography and an ITO pattern is etched. After the second spin coating, the DE channel is exposed by photolithography.

[0013] An ICP etching is performed on the photolithography layer formed after two spin coatings, simultaneously forming the MESA / DE pattern and the N-type gallium nitride mesa;

[0014] An N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively.

[0015] A composite DBR reflective layer is formed on the upper surface of the current LED epitaxial chip;

[0016] Pad openings are formed in the DBR reflective layer at positions corresponding to the N and P electrodes;

[0017] A PAD pad is formed at the opening of the pad.

[0018] Optionally, an ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip, including:

[0019] An ITO conductive layer is formed on the upper surface of the LED epitaxial chip using a magnetron sputtering device or an ion reactive plating (RPD) device, wherein the thickness of the ITO conductive layer ranges from 600 Å to 5000 Å.

[0020] SiO2 is deposited on the surface of the ITO conductive layer as a SiO2 mask layer.

[0021] Optionally, an ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip, including:

[0022] An ITO conductive material of a predetermined thickness is deposited on the surface of the LED epitaxial chip, and annealed in an oxygen environment with a predetermined flow rate using a rapid thermal annealing (RTA) process to form an ITO conductive layer; the predetermined thickness ranges from 600A to 5000A, the predetermined flow rate ranges from 0.5sccm to 4sccm, and the annealing temperature ranges from 400℃ to 600℃.

[0023] SiO2 was deposited on the surface of the annealed ITO conductive layer using a PECVD process to form a SiO2 mask layer.

[0024] Optionally, two spin coating processes are performed on a portion of the SiO2 mask layer, including:

[0025] A first spin coating is performed on a portion of the SiO2 mask layer to form a first photoresist layer.

[0026] Exposure, development, and hardening of the first photoresist layer at temperature T1 to form a MESA pattern;

[0027] The SiO2 mask layer outside the first photoresist layer is etched, and the ITO conductive layer outside the MESA pattern is etched to expose the P-type gallium nitride layer, and the etched ITO conductive layer is placed under the SiO2 mask layer.

[0028] A second spin coating process is performed to form a second photoresist layer covering the first photoresist layer and the exposed P-type gallium nitride layer;

[0029] Exposure, development, and hardening at temperature T2 to create the second photoresist layer, exposing the DE channel;

[0030] Wherein, temperature T1 is greater than temperature T2.

[0031] Optionally, the temperature T1-T2 is greater than 5°C, the ratio of the thickness of the first photoresist layer to the thickness of the second photoresist layer is greater than 1.2, and the sum of the thickness of the first photoresist layer and the thickness of the second photoresist layer is greater than 6µm.

[0032] Optionally, the etching of the SiO2 mask layer other than the first photoresist layer includes:

[0033] The SiO2 mask layer outside the first photoresist layer was etched using a 1:5 buffered oxide etching solution (BOE).

[0034] Etching the ITO conductive layer outside the MESA pattern includes:

[0035] The ITO conductive layer outside the MESA pattern is etched using an ITO etching solution.

[0036] Optionally, perform one ICP etching to simultaneously form the MESA / DE pattern and the N-type gallium nitride mesa, including:

[0037] On the photolithography layer formed after two spin coatings, a multi-step ICP etching is performed sequentially, and the photolithography layer is removed after the ICP etching.

[0038] Remove the SiO2 mask layer to form a MESA / DE pattern and an N-type gallium nitride mesa;

[0039] The ratio of the depth of the first ICP etching step to the depth of the third ICP etching step ranges from 2:1 to 4:1.

[0040] Optionally, the conditions for performing the first step of ICP etching include: using Cl2 and BCl3 gases, with a Cl2:BCl3 ratio greater than 8:1, an excitation power SRF ranging from 1000W to 1500W, and a bias power BRF ranging from 300W to 500W.

[0041] The conditions for performing the second step of ICP etching include: using O2 and Ar gas, with an O2:Ar ratio greater than 4:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W.

[0042] The etching conditions for the third step of ICP include: using Cl2 and BCl3 gases, with a Cl2:BCl3 ratio greater than 8:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W.

[0043] Optionally, an N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively, including:

[0044] NP-Metal was prepared on the N-type gallium nitride mesa and the ITO conductive layer by homogenization, photolithography, development and evaporation to form N-electrodes and P-electrodes;

[0045] The N-electrode and P-electrode structures are one or more combinations of Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

[0046] Optionally, a composite DBR reflective layer is formed on the upper surface of the LED epitaxial chip, comprising:

[0047] Under preset growth conditions, Ti3O5 and SiO2 are deposited in overlapping layers on the upper surface of the LED epitaxial chip to form a DBR reflective layer composed of high / low refractive index Ti3O5 / SiO2 thin films.

[0048] A SiO2 insulating capping layer is deposited on the DBR reflective layer by PECVD to form a composite DBR reflective layer.

[0049] The preset growth conditions are as follows: the ion source baffle is turned on, O2 is introduced at 40 sccm to 60 sccm, the ion source power ranges from 600W to 1000W, the process vacuum ranges from 2.0E-2Pa to 9.0E-Pa, the coating temperature ranges from 120℃ to 150℃, and each Ti3O5 layer is bombarded with O2 after evaporation; the thickness of the SiO2 insulating cover layer ranges from 800 Å to 10000 Å, and the thickness of the composite DBR reflective layer ranges from 2 μm to 5 μm.

[0050] A second aspect of the present invention provides a micro-light-emitting element, the micro-light-emitting element comprising:

[0051] An LED epitaxial chip consisting of a substrate, an N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer;

[0052] A stepped structure is formed on an N-type gallium nitride layer by two spin coatings and one ICP etching. The stepped structure includes an N-type gallium nitride mesa, an ITO conductive layer and a MESA / DE pattern.

[0053] The N-electrode and P-electrode are formed by the N-type gallium nitride mesa and the NP-Metal electrode on the ITO conductive layer;

[0054] A composite DBR reflective layer covering the LED epitaxial chip, and pad openings on the composite DBR reflective layer located above the N and P electrodes;

[0055] PAD pads are connected to the N and P electrodes through the pad openings.

[0056] Optionally, the N-electrode and P-electrode structures are one or more combinations of Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

[0057] Optionally, the thickness of the ITO conductive layer ranges from 600 Å to 5000 Å.

[0058] Optionally, the composite DBR reflective layer is composed of overlapping evaporated Ti3O5 and SiO2 and a SiO2 insulating capping layer on top of the overlapping layer. The thickness of the SiO2 insulating capping layer ranges from 800 Å to 10000 Å, and the thickness of the composite DBR reflective layer ranges from 2 μm to 5 μm.

[0059] Based on the above embodiments of the present invention, a micro-light-emitting element and its fabrication method are provided, comprising an LED epitaxial chip, the LED epitaxial chip including a substrate, an N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer; an ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip; two spin coating processes are performed on a portion of the SiO2 mask layer, and after the first spin coating, a MESA pattern is formed by photolithography, and an ITO pattern is etched; after the second spin coating, a DE channel is exposed by photolithography; an ICP etching process is performed on the photolithographic layer formed after the two spin coating processes, simultaneously forming a MESA / DE pattern and an N-type gallium nitride mesa; an N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively; a composite DBR reflective layer is formed on the upper surface of the LED epitaxial chip; pad openings are formed on the DBR reflective layer at positions corresponding to the N-electrode and P-electrode; and PAD pads are formed at the pad openings. In this embodiment of the invention, the ITO process is moved forward, and the ITO / MESA combined photolithography simplifies the process flow and reduces over-etching caused by the misalignment of ITO and MESA patterns. Furthermore, without removing the resist, a second layer of homogenization and photolithography are performed, and MESA / DE patterns are formed simultaneously through a single ICP etching. This reduces the number of ICP etching steps, lowering chip manufacturing costs. Additionally, an SiO2 mask layer is added to effectively protect the P-type gallium nitride layer and the ITO conductive layer during ICP etching, preventing damage to these layers from over-etching. The fabrication method disclosed in this embodiment not only simplifies the process and reduces chip manufacturing costs but also increases the effective area of ​​the chip. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0061] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0062] Figure 1 A flowchart illustrating a method for fabricating a micro-light-emitting element according to an embodiment of the present invention;

[0063] Figures 2 to 12 This is a process flow diagram of a method for fabricating a micro-light-emitting element provided in an embodiment of the present invention.

[0064] Among them, the substrate is 1, the N-type gallium nitride layer is 2, the active layer is 3, the P-type gallium nitride layer is 4, the ITO conductive layer is 5, the SiO2 mask layer is 6, the first photoresist layer is 7.1, the second photoresist layer is 7.2, the DE pattern is 8, the MESA pattern is 9, the NP-Metal electrode is 10, the composite DBR layer is 11, and the PAD pad is 12. Detailed Implementation

[0065] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0066] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] like Figure 1 The diagram shows a flowchart of a method for fabricating a micro-light-emitting element according to an embodiment of the present invention. The fabrication method mainly includes the following steps:

[0068] S101: Provides an LED epitaxial chip.

[0069] In S101, such as Figure 2 As shown, the LED epitaxial chip includes a substrate 1, an N-type gallium nitride layer 2, an active layer 3, and a P-type gallium nitride layer 4.

[0070] The LED epitaxial chip is a normally grown LED epitaxial chip.

[0071] In one embodiment of the present invention, the substrate 1 is preferably a sapphire substrate.

[0072] S102: An ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip.

[0073] In the specific implementation of S102, the ITO formation process is moved forward. A transparent conductive layer such as ITO is prepared on the upper surface of the LED epitaxial chip, that is, on the upper surface of the P-type gallium nitride layer 4. Then, SiO2 is deposited on the formed ITO conductive layer 5 as a mask layer, thus forming the SiO2 mask layer 6. The specific structure is as follows: Figure 3 As shown.

[0074] In one embodiment of the present invention, firstly, an ITO conductive layer is formed on the upper surface of the LED epitaxial chip using a magnetron sputtering device or an ion reactive plating (RPD) device.

[0075] Preferably, the thickness of the ITO conductive layer ranges from 600 Å to 5000 Å.

[0076] Then, SiO2 is deposited on the surface of the formed ITO conductive layer as a SiO2 mask layer.

[0077] In one embodiment of the present invention, firstly, an ITO conductive material of a predetermined thickness is deposited on the upper surface of the LED epitaxial chip, and then annealed in an oxygen environment with a predetermined flow rate using a rapid thermal annealing (RTA) process to form an ITO conductive layer.

[0078] Preferably, the preset thickness ranges from 600 Å to 5000 Å.

[0079] Preferably, the preset flow rate range includes 0.5 sccm to 4 sccm, and the annealing temperature range includes 400°C to 600°C.

[0080] Then, SiO2 is deposited on the surface of the annealed ITO conductive layer using a PECVD process to form a SiO2 mask layer.

[0081] S103: Perform the first spin coating on the surface of the SiO2 mask layer, and expose the MESA pattern by photolithography after spin coating.

[0082] S104: Etch the SiO2 mask layer and the ITO conductive layer to create the ITO pattern.

[0083] S105: Perform a second spin coating on the photoresist surface formed by the first spin coating, and expose the DE channel by photolithography.

[0084] The specific execution process of S103 to S105 can be understood as performing two spin coatings in a part of the SiO2 mask layer. After the first spin coating, the MESA pattern is formed by photolithography and the ITO pattern is etched. After the second spin coating, the DE channel is exposed by photolithography.

[0085] In the specific implementation of S103 to S105, after the first spin coating, exposure, development, and hardening are performed to expose the MESA pattern. Then, the SiO2 mask layer is etched by BOE, followed by ITO etching to expose the ITO pattern. This combines ITO / MESA photolithography, which not only simplifies the process but also reduces over-etching caused by ITO and MESA pattern misalignment. After ITO etching, a second spin coating is performed without stripping, followed by exposure, development, and hardening to expose the DE channel.

[0086] In one embodiment of the present invention, firstly, as Figure 4 As shown, a first photoresist layer 7.1 is formed by performing a first photoresist layer in a portion of the SiO2 mask layer 6.

[0087] Then, the first photoresist layer is exposed, developed, and hardened at temperature T1 to form the MESA pattern.

[0088] Then, as Figure 5 and Figure 6 As shown, the SiO2 mask layer 6 other than the first photoresist layer 7.1 is etched, and the ITO conductive layer 5 other than the MESA pattern is etched to expose the P-type gallium nitride layer 4, and the etched ITO conductive layer 5 is placed under the SiO2 mask layer 6.

[0089] It should be noted that the specific etching time of the ITO conductive layer 5 only needs to be ensured. The etched ITO conductive layer 5 can then be placed under the SiO2 mask layer 6.

[0090] Then, as Figure 7 As shown, a second spin coating is performed to form a second photoresist layer 7.2 covering the first photoresist layer 7.1 and the exposed P-type gallium nitride layer 4.

[0091] Finally, the second photoresist layer is exposed and developed at temperature T2 to expose the ED channel.

[0092] Wherein, temperature T1 is greater than temperature T2.

[0093] Preferably, the temperature T1-T2 is greater than 5°C, the ratio of the thickness of the first photoresist layer 7.1 to the thickness of the second photoresist layer 7.2 is greater than 1.2, and the sum of the thicknesses of the first photoresist layer 7.1 and the second photoresist layer 7.2 is greater than 6µm.

[0094] It should be noted that in the entire process described above, after ITO etching, a second photoresist coating is performed without removing the photoresist, followed by exposure and development to expose the DE channel. By controlling the hardening temperature of the first and second photoresist coatings, as well as the thickness ratio of the first and second photoresist layers, the MESA / DE step height difference can be simultaneously formed.

[0095] In one embodiment of the present invention, the SiO2 mask layer outside the first photoresist layer is etched. The specific process is as follows: the SiO2 mask layer outside the first photoresist layer is etched with a 1:5 buffer oxide etching solution (BOE).

[0096] In one embodiment of the present invention, the ITO conductive layer outside the MESA pattern is etched. Specifically, the process is to use an ITO etching solution to etch the ITO conductive layer outside the MESA pattern.

[0097] S106: Perform an ICP etching on the photolithography layer formed after two spin coatings to simultaneously form the MESA / DE pattern and the N-type gallium nitride mesa.

[0098] In the specific execution of S106, MESA pattern 9, DE pattern 8, and N-type gallium nitride mesas are formed on the photolithography layer formed after two spin coating processes through a multi-step ICP etching process. The resulting structure is as follows: Figure 8 As shown.

[0099] In one embodiment of the present invention, a multi-step ICP etching is performed sequentially on the photolithography layer formed after two spin coatings, and the photolithography layer is removed after the ICP etching; then, the SiO2 mask layer is removed to form MESA\DE patterns and N-type gallium nitride mesa.

[0100] The ratio of the depth of the first ICP etching step to the depth of the third ICP etching step ranges from 2:1 to 4:1.

[0101] It should be noted that this SiO2 mask layer can effectively protect the P-type gallium nitride layer and prevent damage to the P-type gallium nitride layer from ICP over-etching. This helps to increase the effective area of ​​the chip.

[0102] In one embodiment of the present invention, the specific process of performing a three-step ICP etching is as follows:

[0103] The conditions for performing the first step of ICP etching include: using Cl2 and BCl3 gases with a Cl2:BCl3 ratio greater than 8:1, an excitation power SRF ranging from 1000W to 1500W, and a bias power BRF ranging from 300W to 500W.

[0104] The conditions for performing the second step of ICP etching include: using O2 and Ar gases, with an O2:Ar ratio greater than 4:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W.

[0105] The etching conditions for performing the third step of ICP include: using Cl2 and BCl3 gases, with a Cl2:BCl3 ratio greater than 9:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W.

[0106] Preferably, in the above-mentioned multi-step one-time etching process using ICP etching, the etching depth ratio of the first and third steps is controlled, and the residual resist in the N-type gallium nitride region is removed by etching O2 Plasma in the second step to ensure the smoothness of MESA etching and the etching depth of the third step.

[0107] S107: An N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively.

[0108] In the specific implementation of S107, such as Figure 9 As shown, an NP-Metal electrode 10 is prepared on the N-type gallium nitride mesa and the ITO conductive layer 5 by homogenization, photolithography, development and evaporation to form an N electrode and a P electrode.

[0109] The N-electrode and P-electrode structures are composed of one or more metals selected from Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

[0110] S108: A composite DBR reflective layer is formed on the upper surface of the current LED epitaxial chip.

[0111] In one embodiment of the present invention, firstly, under preset growth conditions, Ti3O5 and SiO2 are deposited in overlapping layers on the upper surface of the LED epitaxial chip to form a DBR reflective layer composed of high / low refractive index Ti3O5 / SiO2 thin films.

[0112] Then, a SiO2 insulating capping layer is deposited on the DBR reflective layer using PECVD to form a composite DBR reflective layer 11. The specific structure formed is as follows: Figure 10 As shown.

[0113] The preset growth conditions are as follows: the ion source baffle is turned on, O2 is introduced at 40 sccm to 60 sccm, the ion source power ranges from 600W to 1000W, the process vacuum ranges from 2.0E-2Pa to 9.0E-Pa, the coating temperature ranges from 120℃ to 150℃, and each Ti3O5 layer is bombarded with O2 after evaporation; the thickness of the SiO2 insulating cover layer ranges from 800Å to 10000Å, and the thickness of the composite DBR reflective layer ranges from 2µm to 5µm.

[0114] S109: A pad opening is formed in the DBR reflective layer at the position corresponding to the N electrode and the P electrode.

[0115] In the specific implementation of S109, CF4 / CHF3 etching gases were used for etching the opening areas of the DBR structure pads after spin coating, exposure, and development. The resulting structure is as follows: Figure 11 As shown.

[0116] S110: A PAD pad is formed at the opening of the pad.

[0117] In the specific implementation of S110, such as Figure 12 As shown, PAD pads 12 are formed at the pad openings using a photolithographic mask.

[0118] Preferably, the metal structure of PAD is one or more of the following metals: Cr, Ni, Al, Ti, Pt, and Au.

[0119] In the fabrication method of the micro-light-emitting element provided in the embodiments of the present invention, the ITO process is moved forward, the ITO / MESA combined photolithography simplifies the process flow, and reduces the ITO over-etching phenomenon caused by the over-etching misalignment of ITO and MESA patterns. Without removing the resist, the MESA / DE pattern is formed simultaneously through a second homogenization and photolithography, and an ICP etching process, reducing one ICP etching step, lowering the chip manufacturing cost, and adding a SiO2 mask layer to effectively protect the P-type gallium nitride layer and ITO conductive layer during the ICP etching process, avoiding damage to the P-type gallium nitride layer and ITO conductive layer by ICP over-etching. The fabrication method disclosed in the embodiments of the present invention not only simplifies the process and reduces the chip manufacturing cost, but also increases the effective area of ​​the chip.

[0120] Based on the fabrication method of the micro-light-emitting element disclosed in the above embodiments of the present invention, the present invention also discloses a micro-light-emitting element, which is as follows: Figure 12 As shown, it mainly includes:

[0121] An LED epitaxial chip consisting of a substrate 1, an N-type gallium nitride layer 2, an active layer 3, and a P-type gallium nitride layer 4.

[0122] A stepped structure is formed on the N-type gallium nitride layer 2 through a second spin coating and a first ICP etching. The stepped structure includes an N-type gallium nitride mesa, an ITO conductive layer 5, a MESA pattern 9, and a DE pattern 8.

[0123] The N-type gallium nitride mesa and the NP-Metal electrode 10 on the ITO conductive layer 4 form the N-electrode and the P-electrode.

[0124] A composite DBR reflective layer 11 covering the LED epitaxial chip, and pad openings on the composite DBR reflective layer 11 located above the N electrode and P electrode.

[0125] PAD pads 12 are connected to the N and P electrodes through the pad openings.

[0126] In this embodiment of the invention, an N-electrode is formed on the N-type gallium nitride mesa, and a P-electrode is formed on the ITO conductive layer 4. Preferably, the N-electrode and P-electrode structures are one or more combinations of Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

[0127] In one embodiment of the present invention, the thickness of the ITO conductive layer 4 ranges from 600 Å to 5000 Å.

[0128] In one embodiment of the present invention, the composite DBR reflective layer 11 is composed of overlapping evaporated Ti3O5 and SiO2 and a SiO2 insulating cover layer on the overlapping layer. The thickness of the composite DBR reflective layer 11 ranges from 2 μm to 5 μm, and the thickness of the SiO2 insulating cover layer ranges from 800 Å to 10000 Å.

[0129] In summary, the effective area of ​​the micro-light-emitting element formed by the fabrication method of the micro-light-emitting element disclosed in the above embodiments of the present invention is larger than that of existing micro-light-emitting elements, and the fabrication cost is simple and low.

[0130] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0131] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0132] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0133] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0134] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a micro-light-emitting element, characterized in that, The preparation method includes: An LED epitaxial chip is provided, the LED epitaxial chip comprising a substrate, an N-type gallium nitride layer, an active layer and a P-type gallium nitride layer; An ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip; Two spin coating processes are performed on a portion of the SiO2 mask layer. After the first spin coating, a MESA pattern is formed by photolithography and an ITO pattern is etched. After the second spin coating, the DE channel is exposed by photolithography. An ICP etching is performed on the photolithography layer formed after two spin coatings, simultaneously forming the MESA / DE pattern and the N-type gallium nitride mesa; An N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively. A composite DBR reflective layer is formed on the upper surface of the current LED epitaxial chip; Pad openings are formed in the DBR reflective layer at positions corresponding to the N and P electrodes; A PAD pad is formed at the opening of the pad.

2. The preparation method according to claim 1, characterized in that, An ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip, including: An ITO conductive layer is formed on the upper surface of the LED epitaxial chip using a magnetron sputtering device or an ion reactive plating (RPD) device, wherein the thickness of the ITO conductive layer ranges from 600 Å to 5000 Å. SiO2 is deposited on the surface of the ITO conductive layer as a SiO2 mask layer.

3. The preparation method according to claim 1, characterized in that, An ITO conductive layer and a SiO2 mask layer are formed on the upper surface of the LED epitaxial chip, including: An ITO conductive material of a predetermined thickness is deposited on the surface of the LED epitaxial chip, and annealed in an oxygen environment with a predetermined flow rate using a rapid thermal annealing (RTA) process to form an ITO conductive layer; the predetermined thickness ranges from 600A to 5000A, the predetermined flow rate ranges from 0.5sccm to 4sccm, and the annealing temperature ranges from 400℃ to 600℃. SiO2 is deposited on the surface of the annealed ITO conductive layer using a PECVD process to form a SiO2 mask layer.

4. The preparation method according to claim 1, characterized in that, Two spin coating processes are performed on a portion of the SiO2 mask layer, including: A first spin coating is performed on a portion of the SiO2 mask layer to form a first photoresist layer; Exposure, development, and hardening of the first photoresist layer at temperature T1 to form a MESA pattern; The SiO2 mask layer outside the first photoresist layer is etched, and the ITO conductive layer outside the MESA pattern is etched to expose the P-type gallium nitride layer, and the etched ITO conductive layer is placed under the SiO2 mask layer. A second spin coating process is performed to form a second photoresist layer covering the first photoresist layer and the exposed P-type gallium nitride layer; Exposure, development, and hardening at temperature T2 to create the second photoresist layer, exposing the DE channel; Wherein, temperature T1 is greater than temperature T2.

5. The preparation method according to claim 4, characterized in that, The temperature T1-T2 is greater than 5°C, the ratio of the thickness of the first photoresist layer to the thickness of the second photoresist layer is greater than 1.2, and the sum of the thickness of the first photoresist layer and the thickness of the second photoresist layer is greater than 6µm.

6. The preparation method according to claim 4, characterized in that etching the SiO2 mask layer other than the first photoresist layer includes: The SiO2 mask layer outside the first photoresist layer was etched using a 1:5 buffered oxide etching solution (BOE). Etching the ITO conductive layer outside the MESA pattern includes: The ITO conductive layer outside the MESA pattern is etched using an ITO etching solution.

7. The preparation method according to claim 1, characterized in that, Perform one ICP etching operation to simultaneously form MESA / DE patterns and N-type gallium nitride mesa, including: On the photolithography layer formed after two spin coatings, a multi-step ICP etching is performed sequentially, and the photolithography layer is removed after the ICP etching. Remove the SiO2 mask layer to form a MESA / DE pattern and an N-type gallium nitride mesa; The ratio of the depth of the first ICP etching step to the depth of the third ICP etching step ranges from 2:1 to 4:

1.

8. The preparation method according to claim 7, characterized in that, The conditions for performing the first step of ICP etching include: using Cl2 and BCl3 gases, with a Cl2:BCl3 ratio greater than 8:1, an excitation power SRF ranging from 1000W to 1500W, and a bias power BRF ranging from 300W to 500W. The conditions for performing the second step of ICP etching include: using O2 and Ar gas, with an O2:Ar ratio greater than 4:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W. The etching conditions for the third step of ICP include: using Cl2 and BCl3 gases, with a Cl2:BCl3 ratio greater than 9:1, an excitation power SRF ranging from 600W to 900W, and a bias power BRF ranging from 100W to 200W.

9. The preparation method according to claim 1, characterized in that, An N-electrode and a P-electrode are formed on the N-type gallium nitride mesa and the ITO conductive layer, respectively, including: NP-Metal was prepared on the N-type gallium nitride mesa and the ITO conductive layer by homogenization, photolithography, development and evaporation to form N-electrodes and P-electrodes; The N-electrode and P-electrode structures are one or more combinations of Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

10. The preparation method according to claim 1, characterized in that, A composite DBR reflective layer is formed on the upper surface of the LED epitaxial chip described herein, comprising: Under preset growth conditions, Ti3O5 and SiO2 are deposited in overlapping layers on the upper surface of the LED epitaxial chip to form a DBR reflective layer composed of high / low refractive index Ti3O5 / SiO2 thin films. A SiO2 insulating capping layer is deposited on the DBR reflective layer by PECVD to form a composite DBR reflective layer. The preset growth conditions are as follows: the ion source baffle is turned on, O2 is introduced at 40 sccm to 60 sccm, the ion source power ranges from 600W to 1000W, the process vacuum ranges from 2.0E-2Pa to 9.0E-Pa, the coating temperature ranges from 120℃ to 150℃, and each Ti3O5 layer is bombarded with O2 after evaporation; the thickness of the SiO2 insulating cover layer ranges from 800 Å to 10000 Å, and the thickness of the composite DBR reflective layer ranges from 2 μm to 5 μm.

11. A micro-light-emitting element, characterized in that, The micro-light-emitting element includes: An LED epitaxial chip consisting of a substrate, an N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer; A stepped structure is formed on an N-type gallium nitride layer through two spin coatings and one ICP etching. The stepped structure includes an N-type gallium nitride mesa, an ITO conductive layer, and a MESA / DE pattern. Specifically, after the first spin coating, the MESA pattern is formed by photolithography and the ITO pattern is etched. After the second spin coating, the DE channel is exposed by photolithography. The N-electrode and P-electrode are formed by the N-type gallium nitride mesa and the NP-Metal electrode on the ITO conductive layer; A composite DBR reflective layer covering the LED epitaxial chip, and pad openings on the composite DBR reflective layer located above the N and P electrodes; PAD pads are connected to the N and P electrodes through the pad openings.

12. The micro-light-emitting element according to claim 11, characterized in that, The N-electrode and P-electrode structures are one or more combinations of Cr, Ni, Al, Ti, Pt, and Au, and the surface cutoff layer of the N-electrode and P-electrode is Pt.

13. The micro-light-emitting element according to claim 11, characterized in that, The thickness of the ITO conductive layer ranges from 600 Å to 5000 Å.

14. The micro-light-emitting element according to claim 11, characterized in that, The composite DBR reflective layer is composed of overlapping evaporated Ti3O5 and SiO2 and a SiO2 insulating capping layer on top of the overlapping layer. The thickness of the SiO2 insulating capping layer ranges from 800 Å to 10000 Å, and the thickness of the composite DBR reflective layer ranges from 2 μm to 5 μm.

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