A hardware interface overcurrent protection device, method, server and electronic equipment

Abstract

The application belongs to the technical field of overcurrent protection, and specifically provides a hardware interface overcurrent protection device, method, server and electronic equipment. The device comprises a hardware interface, a fast charging protocol chip, a logic chip and a charging chip. The hardware interface is connected with the charging chip through the fast charging protocol chip. A direct current power supply detection module for detecting whether the external power supply is in action is arranged at the position of the hardware interface. The fast charging protocol chip and the direct current power supply detection module are connected with the logic chip respectively. When the hardware interface is connected with the external power supply, the external power supply charges the charging chip through the fast charging protocol chip. The logic chip is connected with the charging chip, and is used for controlling the signal delay of charging the charging chip by the external power supply according to the on-off of the internal path of the direct current power supply detection module and the fast charging protocol chip. The effect of protecting the NMOS tube in the fast charging protocol chip is achieved.

Description

Technical Field

[0001] This invention relates to the field of overcurrent protection technology, specifically to a hardware interface overcurrent protection device, method, server, and electronic device. Background Technology

[0002] Because the Type-C interface supports 100W charging at 20V / 5A, Intel CPUs require an external fast charging protocol chip that supports charger / CC signal decoding. This fast charging protocol chip uses a 20V / 3A charging switch that activates via a signal from a detection pin. The switch is typically made of NMOS transistors. An NMOS design specification states that when the external power supply (NMOS drain) is ramping up, the gate (NMOS source) cannot be enabled and the power supply to it cannot be de-loaded. Otherwise, it will trigger a State of Arrival (SOA) within the NMOS transistor, damaging the gate or burning out the entire NMOS transistor.

[0003] Currently, the method relies solely on software code to ensure that the gate of the NMOS transistor inside the fast charging protocol chip receives the probe pin signal before enabling the gate switch, thus delaying the switch turn-on time and avoiding the external power supply ramp-up time.

[0004] However, this method carries certain risks. If the software code is not set up properly, or if the signal timing is not specifically measured to check whether the SOA specification is truly being avoided, there is a risk of directly burning out the chip or damaging the chip, resulting in losses. Summary of the Invention

[0005] If the software code is not set properly, and if the signal timing is not specifically measured, it is impossible to check whether the SOA specification is truly avoided, which may directly burn out the chip or damage the chip, causing losses. This invention provides a hardware interface overcurrent protection device, method, server, and electronic device.

[0006] In a first aspect, the technical solution of the present invention provides a hardware interface overcurrent protection device, including a hardware interface, a fast charging protocol chip, a logic chip and a charging chip;

[0007] The hardware interface connects to the charging chip via a fast charging protocol chip.

[0008] The hardware interface is equipped with a DC power detection module to detect whether the external power supply is active;

[0009] The fast charging protocol chip and the DC power detection module are respectively connected to the logic chip;

[0010] When the hardware interface is connected to an external power source, the external power source charges the charging chip through the fast charging protocol chip; the logic chip is connected to the charging chip and is used to control the signal delay of the external power source charging the charging chip according to the on / off state of the DC power detection module and the internal path of the fast charging protocol chip.

[0011] As a further limitation of this technical solution, the fast charging protocol chip is provided with a voltage output terminal and a control indication terminal;

[0012] The voltage output terminal is used to output the voltage for charging the charging chip.

[0013] The control indicator terminal is used to indicate the on / off status of the charging path inside the fast charging protocol chip;

[0014] The control indicator terminal is connected to the logic chip and is used to input the on / off status of the charging path inside the fast charging protocol chip to the logic chip.

[0015] As a further limitation of this technical solution, the device also includes a first voltage conversion module; the DC power supply detection module includes a detection output terminal and a detection input terminal;

[0016] The voltage output terminal of the fast charging protocol chip is connected to the detection input terminal of the DC power detection module through the first voltage conversion module, which is used to convert the voltage output terminal of the fast charging protocol chip and input it to the DC power detection module.

[0017] The detection output terminal of the DC power supply detection module is connected to the logic chip to input the detected voltage state, which represents the operation of the external power supply, into the logic chip.

[0018] As a further limitation of this technical solution, the charging chip is provided with an ILIM_HIZ terminal; the logic chip includes a first input terminal, a second input terminal, and an output terminal;

[0019] The first input terminal of the logic chip is connected to the control indicator terminal of the fast charging protocol chip to receive the on / off status of the charging path inside the fast charging protocol chip;

[0020] The second input terminal of the logic chip is connected to the detection output terminal of the DC power supply detection module to receive the voltage state characterizing the operation of the external power supply.

[0021] The output of the logic chip is connected to the ILIM_HIZ terminal of the charging chip, and is used to output control signals to the ILIM_HIZ terminal of the charging chip according to the received status information.

[0022] As a further limitation of this technical solution, the fast charging protocol chip is internally equipped with a first switch module, a control module, and a detection module for detecting the current input to the fast charging protocol chip; the control module is connected to the logic chip and is used to output the state of the control first switch module to the logic chip;

[0023] The first switch module and the detection module are respectively connected to the control module and are used to control the on and off of the first switch module according to the current detected by the detection module, thereby controlling the path of the external power supply to charge the charging chip.

[0024] The first switching module includes a first NMOS transistor and a second NMOS transistor;

[0025] The source of the first NMOS transistor is connected to the hardware interface, the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the charging chip.

[0026] The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the control module.

[0027] As a further limitation of this technical solution, the hardware interface is connected to the voltage output terminal through the first switch module, and the voltage output terminal of the fast charging protocol chip is connected to the charging chip to provide charging power to the charging chip.

[0028] The control module is connected to the control indicator terminal and is used to output the status of the first switch module.

[0029] The control indicator terminal is connected to the logic chip and is used to input the control state of the first switch module to the logic chip.

[0030] As a further limitation of this technical solution, the device also includes a second voltage conversion module; the fast charging protocol chip has a second switch module connected to the control module;

[0031] The charging chip converts its voltage through the second voltage conversion module, and outputs the converted voltage to the hardware interface through the second switching module to provide power to the devices connected to the hardware interface.

[0032] Secondly, the present invention provides a hardware interface overcurrent protection method based on the device described in the first aspect, comprising the following steps:

[0033] After an external power supply is plugged into the hardware interface, the DC power supply detection module detects the power level.

[0034] When a low-to-high level transition is detected, the port level state used by the fast charging protocol chip to characterize the internal path state is determined.

[0035] If the level changes from low to high, the logic chip will pull the ILIM_HIZ signal connected to the charging chip low;

[0036] After setting the time threshold, the logic chip will restore the ILIM_HIZ signal connected to the charging chip.

[0037] Thirdly, the present invention also provides a server, the server including the hardware interface overcurrent protection device as described in the first aspect.

[0038] Fourthly, the present invention also provides an electronic device, which includes a hardware interface overcurrent protection device as described in the first aspect.

[0039] As can be seen from the above technical solutions, the present invention has the following advantages: it can automatically eliminate situations where damage to devices or chips is caused by abnormal / corrupted software code based on the current boot configuration, preventing the risk of component burnout and replacing the problem of manual verification. The logic chip controls the start time of the delayed charging chip by pulling the ILIM_HIZ pin low from its original high level for a set time, thus meeting the SOA specification that prohibits the charging chip from starting charging during voltage ramp-up. After the set time is reached, the ILIM_HIZ pin level is restored, and the system resumes the charging process. This achieves the effect of protecting the internal NMOS transistor of the fast charging protocol chip.

[0040] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects.

[0041] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic block diagram of an apparatus according to an embodiment of the present invention. Detailed Implementation

[0044] Currently, the method relies solely on software code to ensure that the gate (G) of the NMOS transistor inside the fast charging protocol chip receives a probe pin signal before enabling the G switch, thus delaying the switch turn-on time and avoiding the external power supply rise time. However, this method carries certain risks. If the software code is not properly configured, or if the signal timing is not specifically measured to verify whether the SOA specification is truly being avoided, it could directly burn out the chip or cause damage. To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0045] like Figure 1 As shown, this embodiment of the invention provides a hardware interface overcurrent protection device, including a hardware interface, a fast charging protocol chip, a logic chip, and a charging chip;

[0046] The hardware interface connects to the charging chip via a fast charging protocol chip.

[0047] The hardware interface is equipped with a DC power detection module to detect whether the external power supply is active;

[0048] The fast charging protocol chip and the DC power detection module are respectively connected to the logic chip;

[0049] When the hardware interface is connected to an external power source, the external power source charges the charging chip through the fast charging protocol chip; the logic chip is connected to the charging chip and is used to control the signal delay of the external power source charging the charging chip according to the on / off state of the DC power detection module and the internal path of the fast charging protocol chip.

[0050] In existing technical solutions, when the hardware interface is connected to an external power supply (20V), if the 20V voltage entering the PD chip has not yet fully reached its peak stable value, the internal switching path of the PD chip will be activated because the detection module inside the PD has already detected the voltage signal, and the charging chip will begin charging. This behavior violates SOA regulations and poses a risk of burning out the PD chip. In this application, after the hardware interface is connected to an external power supply, the DC power detection module detects the voltage level. When a low-to-high voltage level is detected, the port voltage level used by the fast charging protocol chip to characterize the internal path is determined. If the voltage level changes from low to high, charging has actually begun. The ILIM_HIZ signal bit of the charging chip is at a high level. To achieve protection, the logic chip pulls the ILIM_HIZ signal connected to the charging chip low. In other words, the logic chip sets a time limit for pulling the ILIM_HIZ pin low from its original high level. In effect, the charging chip reduces its original charging current to 0, meaning it stops charging. This controls and delays the start time of the charging chip to meet the SOA specification that prohibits the charging chip from starting charging during voltage ramp-up. After the set time is reached, the ILIM_HIZ pin level is restored, and the system resumes the charging process. This achieves the effect of protecting the internal NMOS transistor of the fast charging protocol chip.

[0051] In some embodiments, the fast charging protocol chip is provided with a voltage output terminal and a control indication terminal;

[0052] The voltage output terminal is used to output the voltage for charging the charging chip.

[0053] The control indicator terminal is used to indicate the on / off status of the charging path inside the fast charging protocol chip;

[0054] The control indicator terminal is connected to the logic chip and is used to input the on / off status of the charging path inside the fast charging protocol chip to the logic chip.

[0055] In some embodiments, the device further includes a first voltage conversion module; the DC power supply detection module includes a detection output terminal and a detection input terminal;

[0056] The voltage output terminal of the fast charging protocol chip is connected to the detection input terminal of the DC power detection module through the first voltage conversion module, which is used to convert the voltage output terminal of the fast charging protocol chip and input it to the DC power detection module.

[0057] The DC power supply detection module's output terminal is connected to the logic chip, used to input the detected voltage state, representing the operation of the external power supply, into the logic chip. The 20V voltage output by the PD chip is converted into 3V by the first voltage conversion module and input to the DC power supply detection module. After detecting the 3V voltage signal, the DC power supply detection module outputs a DC_DET signal to the logic chip.

[0058] In some embodiments, the charging chip is provided with an ILIM_HIZ terminal; the logic chip includes a first input terminal, a second input terminal, and an output terminal;

[0059] The first input terminal of the logic chip is connected to the control indicator terminal of the fast charging protocol chip to receive the on / off status of the charging path inside the fast charging protocol chip;

[0060] The second input terminal of the logic chip is connected to the detection output terminal of the DC power supply detection module to receive the voltage state characterizing the operation of the external power supply.

[0061] The output of the logic chip is connected to the ILIM_HIZ terminal of the charging chip, and is used to output control signals to the ILIM_HIZ terminal of the charging chip according to the received status information.

[0062] It can automatically eliminate situations where software code anomalies / corruptions could damage devices or chips based on the current boot configuration, preventing the risk of component burnout and replacing manual verification. The logic chip controls the start time of the delayed charging chip by pulling the ILIM_HIZ pin low from its original high level for a set time, thus complying with the SOA specification that prohibits the charging chip from starting charging during voltage ramp-up. After the set time is reached, the ILIM_HIZ pin level is restored, and the system resumes the charging process. This effectively protects the internal NMOS transistor of the fast charging protocol chip.

[0063] The fast charging protocol chip has a first switch module, a control module, and a detection module for detecting the current input to the fast charging protocol chip; the control module is connected to the logic chip and is used to output the state of the first switch module to the logic chip.

[0064] The first switch module and the detection module are respectively connected to the control module, and are used to control the on and off of the first switch module according to the current detected by the detection module, thereby controlling the path of the external power supply to charge the charging chip.

[0065] The first switching module includes a first NMOS transistor and a second NMOS transistor;

[0066] The source of the first NMOS transistor is connected to the hardware interface, the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the charging chip.

[0067] The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the control module.

[0068] As a further limitation of this technical solution, the hardware interface is connected to the voltage output terminal through the first switch module, and the voltage output terminal of the fast charging protocol chip is connected to the charging chip to provide charging power to the charging chip.

[0069] The control module is connected to the control indicator terminal and is used to output the status of the first switch module.

[0070] The control indicator terminal is connected to the logic chip and is used to input the control status of the first switch module to the logic chip.

[0071] It can automatically eliminate situations where software code anomalies / corruptions could damage devices or chips based on the current boot configuration, preventing the risk of component burnout and replacing manual verification. The logic chip controls the start time of the delayed charging chip by pulling the ILIM_HIZ pin low from its original high level for a set time, thus complying with the SOA specification that prohibits the charging chip from starting charging during voltage ramp-up. After the set time is reached, the ILIM_HIZ pin level is restored, and the system resumes the charging process. This effectively protects the internal NMOS transistor of the fast charging protocol chip.

[0072] In some embodiments, the device further includes a second voltage conversion module; the fast charging protocol chip has a second switch module connected to the control module;

[0073] The charging chip converts its voltage through a second voltage conversion module, and then outputs the converted voltage to the hardware interface through a second switching module to provide power to the devices connected to the hardware interface. In other words, the charging chip's 20V voltage is converted into 5V or other voltages by the second voltage conversion module to power the devices connected to the hardware interface.

[0074] It should be noted that in this embodiment of the invention, the logic chip is a programmable mixed-signal matrix, and the SLG46108 chip can be selected. The hardware interface is actually a Type-C interface.

[0075] In this embodiment of the invention, a logic chip is added to the connection line of the PD chip (fast charging protocol chip). Here, a preset condition value needs to be written in the logic chip so that the system has a basic condition setting value at the beginning. This value must be set to the default value at the beginning of the system startup.

[0076] Next, the PD chip on the system has a GPIO interface to connect the relevant timing pins to the pins in the logic chip. That is, conditional startup can be performed through these pins.

[0077] When it is known that an external power supply (20V) is connected through a hardware interface, a logic IC is used to ensure that the external power supply will not risk burning or damaging the PD chip due to software code issues that violate SOA specifications.

[0078] Connect the GPIO 4 of the PD chip and the DC_DET of the DC power detection module to the input of the logic chip, and connect the output of the logic chip to the ILIM_HIZ of the charging chip.

[0079] The function of the ILIM_HIZ pin of the charging chip is to ensure the magnitude of the charging current. Pulling the ILIM_HIZ pin of the charging chip from its original high level to low level actually changes the originally set charging current to 0, that is, the charging chip stops charging.

[0080] This invention provides a hardware interface overcurrent protection method, which is based on a hardware interface overcurrent protection device. The device includes a hardware interface, a fast charging protocol chip, a logic chip, and a charging chip.

[0081] The hardware interface connects to the charging chip via a fast charging protocol chip.

[0082] The hardware interface is equipped with a DC power detection module to detect whether the external power supply is active;

[0083] The fast charging protocol chip and the DC power detection module are respectively connected to the logic chip;

[0084] When the hardware interface is connected to an external power source, the external power source charges the charging chip through the fast charging protocol chip; the logic chip is connected to the charging chip and is used to control the signal delay of the external power source charging the charging chip according to the on / off state of the DC power detection module and the internal path of the fast charging protocol chip.

[0085] The fast charging protocol chip is equipped with a voltage output terminal and a control indicator terminal;

[0086] The voltage output terminal is used to output the voltage for charging the charging chip.

[0087] The control indicator terminal is used to indicate the on / off status of the charging path inside the fast charging protocol chip;

[0088] The control indicator terminal is connected to the logic chip and is used to input the on / off status of the charging path inside the fast charging protocol chip to the logic chip.

[0089] In some embodiments, the device further includes a first voltage conversion module; the DC power supply detection module includes a detection output terminal and a detection input terminal;

[0090] The voltage output terminal of the fast charging protocol chip is connected to the detection input terminal of the DC power detection module through the first voltage conversion module, which is used to convert the voltage output terminal of the fast charging protocol chip and input it to the DC power detection module.

[0091] The detection output terminal of the DC power supply detection module is connected to the logic chip to input the detected voltage state, which represents the operation of the external power supply, into the logic chip.

[0092] The charging chip has an ILIM_HIZ terminal; the logic chip includes a first input terminal, a second input terminal, and an output terminal.

[0093] The first input terminal of the logic chip is connected to the control indicator terminal of the fast charging protocol chip to receive the on / off status of the charging path inside the fast charging protocol chip;

[0094] The second input terminal of the logic chip is connected to the detection output terminal of the DC power supply detection module to receive the voltage state characterizing the operation of the external power supply.

[0095] The output of the logic chip is connected to the ILIM_HIZ terminal of the charging chip, and is used to output control signals to the ILIM_HIZ terminal of the charging chip according to the received status information.

[0096] The fast charging protocol chip has a first switch module, a control module, and a detection module for detecting the current input to the fast charging protocol chip; the control module is connected to the logic chip and is used to output the state of the first switch module to the logic chip.

[0097] The first switch module and the detection module are respectively connected to the control module, and are used to control the on and off of the first switch module according to the current detected by the detection module, thereby controlling the path of the external power supply to charge the charging chip.

[0098] The first switching module includes a first NMOS transistor and a second NMOS transistor;

[0099] The source of the first NMOS transistor is connected to the hardware interface, the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the charging chip.

[0100] The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the control module.

[0101] The hardware interface is connected to the voltage output terminal through the first switch module, and the voltage output terminal of the fast charging protocol chip is connected to the charging chip to provide charging power to the charging chip.

[0102] The control module is connected to the control indicator terminal and is used to output the status of the first switch module.

[0103] The control indicator terminal is connected to the logic chip and is used to input the control status of the first switch module to the logic chip.

[0104] The device also includes a second voltage conversion module; the fast charging protocol chip has a second switch module connected to the control module.

[0105] The charging chip converts its voltage through a second voltage conversion module, and outputs the converted voltage to the hardware interface through a second switching module to provide power to the devices connected to the hardware interface; the method includes the following steps:

[0106] After an external power supply is plugged into the hardware interface, the DC power supply detection module detects the power level.

[0107] When a low-to-high level transition is detected, the port level state used by the fast charging protocol chip to characterize the internal path state is determined.

[0108] If the level changes from low to high, the logic chip will pull the ILIM_HIZ signal connected to the charging chip low;

[0109] After setting the time threshold, the logic chip will restore the ILIM_HIZ signal connected to the charging chip.

[0110] This invention also provides a server, which includes the hardware interface overcurrent protection device described in the above embodiments.

[0111] Fourthly, the present invention also provides an electronic device, which includes a hardware interface overcurrent protection device as described in the above embodiments.

[0112] It should be noted that overcurrent protection is a type of protection that activates when the system operates beyond its maximum value. When the current exceeds the set protection value, the protection device will activate, either shutting down the system directly or issuing a warning signal.

[0113] Type-C connector: It is a hardware interface form of Universal Serial Bus (USB), and its most distinctive feature in appearance is that its top and bottom ends are completely identical.

[0114] The charging chip provides the battery in the system with the correct charging current and charging voltage.

[0115] NMOS: N-type metal-oxide-semiconductor logic uses N-type MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by forming an inversion layer within the body of a p-type transistor. This inversion layer, called the n-channel, conducts electrons between the n-type "source" and "drain" terminals. The n-channel is created by applying a voltage to a third terminal called the gate.

[0116] SOA: Safe operating area is defined as the current and voltage conditions under which an IGBT can be expected to operate without self-damage or degradation.

[0117] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A hardware interface overcurrent protection device, characterized in that, This includes hardware interfaces, fast charging protocol chips, logic chips, and charging chips; The hardware interface connects to the charging chip via a fast charging protocol chip. The hardware interface is equipped with a DC power detection module to detect whether the external power supply is active; The fast charging protocol chip and the DC power detection module are respectively connected to the logic chip; When the hardware interface is connected to an external power source, the external power source charges the charging chip through the fast charging protocol chip; the logic chip is connected to the charging chip and is used to control the signal delay of the external power source charging the charging chip according to the on / off state of the DC power detection module and the internal path of the fast charging protocol chip. The fast charging protocol chip is equipped with a voltage output terminal and a control indicator terminal; The voltage output terminal is used to output the voltage for charging the charging chip. The control indicator terminal is used to indicate the on / off status of the charging path inside the fast charging protocol chip; The control indicator terminal is connected to the logic chip and is used to input the on / off status of the charging path inside the fast charging protocol chip to the logic chip; The device also includes a first voltage conversion module; the DC power detection module includes a detection output terminal and a detection input terminal; The voltage output terminal of the fast charging protocol chip is connected to the detection input terminal of the DC power detection module through the first voltage conversion module, which is used to convert the voltage output terminal of the fast charging protocol chip and input it to the DC power detection module. The detection output terminal of the DC power supply detection module is connected to the logic chip to input the detected voltage state, which represents the operation of the external power supply, into the logic chip. The charging chip has an ILIM_HIZ terminal; The logic chip includes a first input terminal, a second input terminal, and an output terminal; The first input terminal of the logic chip is connected to the control indicator terminal of the fast charging protocol chip to receive the on / off status of the charging path inside the fast charging protocol chip; The second input terminal of the logic chip is connected to the detection output terminal of the DC power supply detection module to receive the voltage state characterizing the operation of the external power supply. The output of the logic chip is connected to the ILIM_HIZ terminal of the charging chip, and is used to output control signals to the ILIM_HIZ terminal of the charging chip according to the received status information.

2. The hardware interface overcurrent protection device according to claim 1, characterized in that, The fast charging protocol chip has a first switch module, a control module, and a detection module for detecting the current input to the fast charging protocol chip; the control module is connected to the logic chip and is used to output the state of the first switch module to the logic chip. The first switch module and the detection module are respectively connected to the control module, and are used to control the on and off of the first switch module according to the current detected by the detection module, thereby controlling the path of the external power supply to charge the charging chip. The first switching module includes a first NMOS transistor and a second NMOS transistor; The source of the first NMOS transistor is connected to the hardware interface, the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the charging chip. The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the control module.

3. The hardware interface overcurrent protection device according to claim 2, characterized in that, The hardware interface is connected to the voltage output terminal through the first switch module, and the voltage output terminal of the fast charging protocol chip is connected to the charging chip to provide charging power to the charging chip. The control module is connected to the control indicator terminal and is used to output the status of the first switch module. The control indicator terminal is connected to the logic chip and is used to input the control state of the first switch module to the logic chip.

4. The hardware interface overcurrent protection device according to claim 3, characterized in that, The device also includes a second voltage conversion module; the fast charging protocol chip has a second switch module connected to the control module. The charging chip converts its voltage through the second voltage conversion module, and outputs the converted voltage to the hardware interface through the second switching module to provide power to the devices connected to the hardware interface.

5. A hardware interface overcurrent protection method based on the device according to any one of claims 1-4, characterized in that, Includes the following steps: After an external power source is plugged into the hardware interface, the port level status of the fast charging protocol chip used to characterize the internal path status is determined, and the level status of the DC power detection module is detected. When the port level changes from low to high and the DC power supply detection module level changes from low to high, the logic chip pulls the ILIM_HIZ signal connected to the charging chip low. After setting the time threshold, the logic chip will restore the ILIM_HIZ signal connected to the charging chip.

6. A server, characterized in that, The server includes a hardware interface overcurrent protection device as described in any one of claims 1-4.

7. An electronic device, characterized in that, The electronic device includes a hardware interface overcurrent protection device as described in any one of claims 1-4.

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