Step-up / down converter and control circuit and control method thereof

Abstract

This invention discloses a buck-boost converter and its control circuit and method. The control circuit includes: a current sampling circuit for detecting the current flowing through an inductor and generating a current sampling signal; an average current limiting circuit for comparing the current sampling signal with a set bias current to generate a current clamping signal; a PWM comparator for comparing the feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and a logic circuit for controlling the conduction time of a first power switch in each switching cycle based on the current clamping signal and the PWM signal. Specifically, the logic circuit controls the first power switch to conduct only when the PWM signal is in a logic high state and the current clamping signal is in a logic low state in each switching cycle. This eliminates the need for operational amplifiers and large RC networks for filtering and shaping to control the current in the inductor, resulting in a faster response speed and rapid limitation of the input average current.

Description

Technical Field

[0001] This invention relates to the field of power conversion technology, and more specifically to a buck-boost converter and its control circuit and control method. Background Technology

[0002] Modern portable electronic devices are typically powered by a battery, which serves as direct current (DC) for the various electronic components within the device. However, these components often have different voltage requirements, so such devices usually employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.

[0003] Existing DC / DC converters with wide input voltage ranges include cascaded buck-boost converters, H-bridge buck-boost converters, Cook converters, and SEPIC (Single Enable Primary Inductance Converter) structures. Among these, the H-bridge buck-boost converter (single inductor or non-inverting buck-boost converter) offers excellent performance.

[0004] Figure 1 A schematic circuit diagram of a buck-boost converter according to the prior art is shown. Figure 1 As shown, a prior art buck-boost converter includes a control circuit 100 and an external power circuit. The power circuit includes one or more switching and filter elements (e.g., inductors and capacitors), which are configured to regulate the power transfer from the input to the output of the power converter in response to one or more switching drive signals from the control circuit 100.

[0005] like Figure 1 As shown, the power circuit is configured to convert the input voltage VIN to the output voltage VOUT, and includes power switches S1-S4, an inductor L, and an output capacitor COUT. When power switches S1 and S3 are on and power switches S2 and S4 are off, the inductor L stores energy. When power switches S1 and S3 are off and power switches S2 and S4 are on, the energy stored in the inductor L is supplied to the load connected to the output terminal.

[0006] The control circuit 100 controls the switching elements S1 to S4 to turn on and off, thereby controlling the inductor L to output energy in discontinuous pulses. The control circuit 100 includes a current sampling circuit 101, an oscillator 102, an error amplifier 103, an adder circuit 104, a slope compensation circuit 105, PWM comparators 106 and 107, a loop compensation circuit 108, a voltage source 109, and a logic and drive circuit 110.

[0007] A current sampling circuit 101 samples the current flowing through inductor L to generate a current sampling signal ISENSE. An oscillator 102 provides an internal clock for the circuit's switching timing (e.g., by generating multiple narrow pulses at a constant frequency, with adjacent pulses defining a clock cycle). An error amplifier 103 compares the feedback signal VFB of the output voltage VOUT with a reference voltage VREF to generate an error amplifier output signal Vea. Optionally, the error amplifier output signal Vea is connected to a loop compensation circuit 108 and provided as input to a PWM comparator 106. The PWM comparator 106 compares the error amplifier output signal Vea with a ramp signal Vsum and generates a shutdown logic signal RST1 when they intersect. The shutdown logic signal RST1 controls the duty cycle of power switches S1 and S2 in buck mode. For example, the ramp compensation signal VSLOPE provided by the ramp compensation circuit 105 and the current sampling signal ISENSE can be superimposed by an adder circuit 104 to obtain the ramp signal Vsum. Furthermore, the error amplifier output signal Vea is connected to voltage source 109, which provides the error amplifier output signal Vea with appropriate offset to PWM comparator 107. PWM comparator 107 compares the offset signal from voltage source 109 with the ramp signal Vsum, and generates a shutdown logic signal RST2 when they intersect. The shutdown logic signal RST2 controls the duty cycle of power switches S3 and S4 in boost mode. Logic and drive circuit 110 implements the system's logic control functions, processes the logic signals of each module controlling the operating state of power switches S1 to S4, and generates switch drive signals DRV1 to DRV4 to provide to power switches S1 to S4. Logic and drive circuit 110 may include a pulse width modulator (PWM) circuit or any other suitable circuit capable of controlling the duty cycle of power switches S1 to S4.

[0008] In buck-boost converters, it is typically necessary to limit the average input current. Current methods involve passing the current sampling signal ISENSE obtained by the current sampling circuit 101 through a filter and shaping circuit 111 to obtain a current sampling voltage signal VSENSE, which is then provided to the input of the current-limiting operational amplifier 112. The current-limiting operational amplifier 112 compares the current sampling voltage signal VSENSE with the clamping voltage Vclamp. Once the current sampling voltage signal VSENSE reaches the input average current clamping voltage, the output of the clamping error amplifier 103 limits the current in the inductor L by controlling the duty cycle of the switch, thereby achieving the purpose of limiting the input current of the circuit.

[0009] However, this existing approach has certain limitations. For buck-boost converters in COT (constant on-time) control mode, since the system architecture lacks a loop error amplifier, this method cannot be used to limit the average input current. Furthermore, this method requires adding a current-limiting operational amplifier to the circuit and complex control logic to improve loop stability, which undoubtedly increases the difficulty of system design. Moreover, this method also requires the use of a large RC network for filtering and shaping, resulting in a slow response speed and inability to achieve fast average input current limiting. Summary of the Invention

[0010] In view of this, the purpose of the present invention is to provide a buck-boost converter and its control circuit and control method, which has a faster response speed and can achieve fast input average current limiting.

[0011] According to a first aspect of the present invention, a control circuit for a buck-boost converter is provided. The buck-boost converter includes a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node. The control circuit includes: a current sampling circuit for detecting current flowing through the inductor and generating a current sampling signal; an average current limiting circuit for comparing the current sampling signal with a set bias current to generate a current clamping signal; a PWM comparator for comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and a logic circuit for controlling the conduction time of the first power switch in each switching cycle according to a combination of the current clamping signal and the pulse width modulation signal, wherein the logic circuit is configured to control the first power switch to conduct when the pulse width modulation signal is in a logic high state and the current clamping signal is in a logic low state in each switching cycle.

[0012] Optionally, the average current limiting circuit includes: a capacitor, the second end of which is coupled to ground; a current source circuit, coupled to the first end of the capacitor, for providing the capacitor with a charging current equivalent to the current sampling signal; a bias current source circuit, the first end of which is coupled to the first end of the capacitor and the second end of which is coupled to ground, the bias current source circuit being used to discharge the capacitor according to the set bias current; and a comparator for comparing the voltage of the capacitor with a threshold voltage to generate the current clamping signal.

[0013] Optionally, the threshold voltage has a reference ground potential.

[0014] Optionally, the average current limiting circuit further includes: a first switch coupled between a first terminal of the capacitor and ground, the first switch being briefly turned on before the first power switch is turned on to release the charge in the capacitor.

[0015] Optionally, the bias current source circuit includes: a first transistor and a resistor coupled between the input voltage and ground; a second transistor and a third transistor coupled between the input voltage and ground; an operational amplifier whose non-inverting input is coupled to a fourth reference voltage, whose inverting input is coupled to the common terminal of the first transistor and the resistor, and whose output is coupled to the control terminals of the first transistor and the second transistor; a second switch whose first terminal is coupled to the input voltage and whose second terminal is coupled to the control terminals of the first transistor and the second transistor; a third switch whose first terminal is coupled to the control terminal and the first terminal of the third transistor; a sample-and-hold module whose input terminal is coupled to the second terminal of the third switch; and a fourth transistor whose control terminal is coupled to the output terminal of the sample-and-hold module, whose second terminal is coupled to ground, and whose first terminal is used to provide the bias current.

[0016] Optionally, the second switch and the third switch are configured to be time-divisionally complementary during a switching cycle.

[0017] Optionally, during a first time period within a switching cycle, the second switch is off and the third switch is on; during a second time period within a switching cycle other than the first time period, the second switch is on and the third switch is off.

[0018] Optionally, the first time period is a combination of the on-time of the first power switch within one switching cycle and the delay time between the first power switch and the second power switch.

[0019] Optionally, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0020] Optionally, the control circuit further includes: an on-time control circuit, used to compare the on-time of the first power switch in one switching cycle with a time threshold to generate an on-time control signal for controlling the off-time of the first power switch.

[0021] Optionally, the control circuit further includes: a first peak current comparator for comparing the voltage of the first switching node with a second reference voltage to generate a first peak signal for controlling the turn-off time of the third power switch in each switching cycle.

[0022] Optionally, the control circuit further includes: a second peak current comparator for comparing the voltage of the second switching node with a third reference voltage to generate a second peak signal for controlling the on-time of the third power switch in each switching cycle.

[0023] According to a second aspect of the present invention, a control method for a buck-boost converter is provided. The buck-boost converter includes a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node. The control method includes: detecting a current flowing through the inductor and generating a current sampling signal; comparing the current sampling signal with a set bias current to generate a current clamping signal; comparing a feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; and controlling the on-time of the first power switch in each switching cycle according to a combination of the current clamping signal and the pulse width modulation signal, wherein the first power switch is controlled to be turned on when the pulse width modulation signal is in a logic high state and the current clamping signal is in a logic low state in each switching cycle.

[0024] Optionally, the step of comparing the current sampling signal with a set bias current to generate a current clamping signal includes: providing a capacitor; providing a charging current to the capacitor with a magnitude equivalent to the current sampling signal; providing a set bias current and discharging the capacitor according to the bias current; and comparing the voltage of the capacitor with a threshold voltage to generate the current clamping signal.

[0025] Optionally, the step of comparing the current sampling signal with a set bias current to generate a current clamping signal further includes: releasing the charge in the capacitor before the first power switch is turned on in each switching cycle.

[0026] Optionally, the control method further includes: comparing the on-time of the first power switch in one switching cycle with a time threshold to generate an on-time control signal, and controlling the off-time of the first power switch in one switching cycle according to the on-time control signal.

[0027] Optionally, the control method further includes: comparing the voltage of the first switching node with a second reference voltage to generate a first peak signal, and controlling the turn-off time of the third power switch within a switching cycle according to the first peak signal.

[0028] Optionally, the control method further includes: comparing the voltage of the second switching node with a third reference voltage to generate a second peak signal, and controlling the conduction time of the third power switch within a switching cycle according to the second peak signal.

[0029] According to a third aspect of the present invention, a buck-boost converter is provided, comprising: a first power switch coupled between an input voltage and a first switching node; a second power switch coupled between the first switching node and a reference ground; a third power switch coupled between a second switching node and a reference ground; a fourth power switch coupled between the second switching node and an output voltage; an inductor coupled between the first switching node and the second switching node; and the control circuit described above.

[0030] In summary, the buck-boost converter and its control circuit and method provided in this embodiment of the invention use a combination of constant on-time control, peak current mode control, and average current limiting control to control the switching of the buck-boost converter. The control circuit includes an average current limiting circuit, which compares the current sampling signal obtained by the current sampling circuit with a set bias current, generates a current clamping signal based on the comparison result, and then the logic circuit controls the charging timing of the inductor in each switching cycle based on the combination of the PWM signal and the current clamping signal. That is, when the rising edge of the PWM signal arrives, the logic circuit first judges the level state of the current clamping signal; only when the current clamping signal is logic low will it begin charging the inductor, thereby controlling the current in the inductor and ultimately ensuring that the average current in the inductor reaches a constant value. Furthermore, the solution provided in this embodiment does not require operational amplifiers and large RC networks for filtering and shaping in the circuit, thus resulting in a faster response speed and rapid limitation of the input average current. Attached Figure Description

[0031] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0032] Figure 1 A schematic circuit diagram of a buck-boost converter according to the prior art is shown.

[0033] Figure 2 A schematic circuit diagram of a buck-boost converter according to an embodiment of the present invention is shown.

[0034] Figure 3 A schematic circuit diagram of an average current limiting circuit according to an embodiment of the present invention is shown.

[0035] Figure 4 The diagram shows the operating waveforms of the average current limiting circuit according to an embodiment of the present invention.

[0036] Figure 5 A schematic circuit diagram of a bias current source according to an embodiment of the present invention is shown.

[0037] Figure 6 A timing diagram of the operation of a buck-boost converter according to an embodiment of the present invention is shown. Detailed Implementation

[0038] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0039] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0040] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic connection. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them. Furthermore, the paired transistors involved in this invention are mutually matched transistors, and unless otherwise specified, are identical in size and / or type.

[0041] In the context of this invention, when a transistor is in an "off" state, it blocks current and / or substantially does not conduct current. Conversely, when a transistor is in an "on" state, it conducts current significantly. For example, in one embodiment, the high-voltage transistor includes an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET), wherein a high voltage is provided between a first terminal (i.e., the drain) and a second terminal (i.e., the source) of the transistor. In some embodiments, an integrated control circuit can be used to drive a power switch when regulating the energy supplied to a load. Additionally, for the purposes of this disclosure, "ground" or "ground potential" in this invention refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0042] Figure 2 A schematic circuit diagram of a buck-boost converter according to an embodiment of the present invention is shown. The buck-boost converter of this embodiment includes a control circuit 200 and an external power circuit. The power circuit includes one or more switching and filter elements (e.g., inductors and capacitors), which are configured to regulate the power transfer from the input to the output of the power converter in response to one or more switching drive signals from the control circuit 200. In some embodiments, one or more switches in the power circuit are integrated with the control circuit 200 to form an integrated circuit chip.

[0043] like Figure 2 As shown, the power circuit includes power switches S1-S4, an inductor L, and an output capacitor COUT. Power switch S1 has a first terminal, a second terminal, and a control terminal, with its first terminal coupled to the input voltage VIN. Power switch S2 has a first terminal, a second terminal, and a control terminal, with its first terminal coupled to the second terminal of power switch S1 and its second terminal coupled to a reference ground. Inductor L has a first terminal and a second terminal; the common terminal of power switches S1 and S2 forms a first switching node SW1, and the first terminal of inductor L is coupled to this first switching node SW1. Power switch S3 has a first terminal, a second terminal, and a control terminal, with its second terminal connected to the reference ground. Power switch S4 has a first terminal, a second terminal, and a control terminal; its first terminal is coupled to the first terminal of power switch S3, and its second terminal is coupled to the output voltage VOUT. The output capacitor COUT is coupled between the second terminal of power switch S4 and the reference ground. The common terminal of power switches S3 and S4 forms a second switching node SW2, and the second terminal of inductor L is coupled to this second switching node SW2. Power switches S1 to S4 can be any controllable semiconductor switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

[0044] Control circuit 200 is used to control the on and off of switching elements S1 to S4 to control inductor L to output energy in discontinuous pulses. Various examples of the present invention provide systems and methods for controlling buck-boost converters using a combination of constant on-time (COT) control and peak current mode (PCM) control. Control circuit 200 includes current sampling circuit 201, PWM comparator 202, peak current comparators 203 and 204, on-time control circuit 205, average current limiting circuit 206, logic circuit 207, and drive circuit 208.

[0045] The current sampling circuit 201 samples the current flowing through the inductor L and generates a current sampling signal ISENSE. The above sampling can be achieved by means of sampling resistors, current transformers, or current mirrors. Moreover, the current sampling circuit 201 can also estimate the current flowing through the inductor L and obtain the current sampling signal ISENSE by sampling the current flowing through each switching element (e.g., power switch S1).

[0046] The PWM comparator 202 has a non-inverting input, an inverting input, and an output. The non-inverting input receives a first reference voltage VREF1, and the inverting input receives a feedback signal VFB from the output voltage VOUT. For example, the feedback signal VFB for the output voltage VOUT is obtained through a resistor divider network consisting of resistors Ra and Rb. The resistors Ra and Rb are connected in series between the output voltage VOUT and a reference ground. At their common node, a feedback signal VFB representing the output voltage VOUT is generated and coupled to the inverting input of the PWM comparator 202. The PWM comparator 202 compares the feedback signal VFB with the first reference voltage VREF1 and generates a pulse width modulation (PWM) signal at the output.

[0047] The peak current comparator 203 has a non-inverting input, an inverting input, and an output. The non-inverting input is coupled to the first switching node SW1, and the inverting input is used to receive a second reference voltage VREF2. For example, the second reference voltage VREF2 can be generated by other circuitry. The peak current comparator 203 compares the first switching node voltage VSW1 with the second reference voltage VREF2, generating a first peak signal Ipeak1 at the output. When the first switching node voltage VSW1 is higher than the second reference voltage VREF2, the peak current comparator 203 outputs the first peak signal Ipeak1 in a first state (e.g., high level); when the first switching node voltage VSW1 is lower than the second reference voltage VREF2, the peak current comparator 203 outputs the first peak signal Ipeak1 in a second state (e.g., low level).

[0048] The peak current comparator 204 has a non-inverting input, an inverting input, and an output. The non-inverting input is coupled to the second switching node SW2, and the inverting input is used to receive a third reference voltage VREF3. For example, the third reference voltage VREF3 can be generated by other circuitry. The peak current comparator 204 compares the second switching node voltage VSW2 with the third reference voltage VREF3, generating a second peak signal Ipeak2 at the output. When the second switching node voltage VSW2 is higher than the third reference voltage VREF3, the peak current comparator 204 outputs the second peak signal Ipeak2 in a first state (e.g., high level); when the second switching node voltage VSW2 is lower than the third reference voltage VREF3, the peak current comparator 204 outputs the second peak signal Ipeak2 in a second state (e.g., low level).

[0049] The on-time control circuit 205 is configured to start timing when the power switch S1 is turned on, and is used to set the on-time of the power switch S1 in each switching cycle. For example, the on-time control circuit 205 is configured to compare the on-time of the power switch S1 in one switching cycle with a time threshold Ton, and generate an on-time control signal COT at the output. The time threshold Ton can be obtained from the input voltage VIN and the output voltage VOUT. In one embodiment, the time threshold Ton can be expressed as: Ton = Tperiod * VOUT / VIN, where Tperiod represents the desired switching cycle.

[0050] The input of the average current limiting circuit 206 is coupled to the output of the current sampling circuit 201. The average current limiting circuit 206 is configured to compare the current sampling signal ISENSE with the set bias current Ibias, generate a current clamping signal Iclamp based on the comparison result, and then adjust the on-time of power switches S1 and S3, so that the average current of the inductor reaches a constant value.

[0051] The logic circuit 207 is used to implement the logic control function of the system. It processes the logic signals of each module that controls the working state of the switching elements S1 to S4, and generates a first control signal CTRL1 for controlling the power switches S1 and S2 to turn on and off, and a second control signal CTRL2 for controlling the power switches S3 and S4 to turn on and off.

[0052] The drive circuit 208 is coupled to the output of the logic circuit 206 and is configured to generate drive signals DRV1 and DRV2 based on the first control signal CTRL1 to control power switches S1 and S2, respectively. Generally, drive signals DRV1 and DRV2 are complementary signals. To prevent shoot-through of switches S1 and S2, the drive circuit 208 typically includes a dead-time control circuit to introduce a dead time Tdelay between drive signals DRV1 and DRV2. The drive circuit 208 is also configured to generate drive signals DRV3 and DRV4 based on the second control signal CTRL2 to control power switches S3 and S4, respectively. Generally, drive signals DRV3 and DRV4 are complementary signals. Similarly, to prevent shoot-through of switches S3 and S4, the drive circuit 208 also includes a dead-time control circuit to introduce a dead time Tdelay between drive signals DRV3 and DRV4.

[0053] In some embodiments, to prevent reverse current, the control circuit 200 further includes a zero-crossing detection circuit 209, which is coupled to the drive circuit 208. The zero-crossing detection circuit 209 detects whether the current flowing through the inductor L crosses zero, and provides a zero-crossing detection signal ZCD to the drive circuit 208 when it detects that the current flowing through the inductor L has crossed zero. The drive circuit 208 then either turns off both power switches S2 and S4, or turns on both power switches S2 and S3. In practical applications, the zero-crossing detection circuit 209 can determine whether the current flowing through the inductor L has crossed zero by detecting the current flowing through switch S2 or S4.

[0054] According to the teachings of this embodiment, the control circuit 200 controls the buck-boost converter using a combination of constant on-time (COT) control and peak current mode (PCM) control. In each switching cycle, when the feedback signal VFB is lower than the first reference voltage VREF1, the pulse width modulation signal PWM output by the PWM comparator 202 flips to a high level. The logic circuit 207 sets the first control signal CTRL1 and the second control signal CTRL2 according to the high-level state of the PWM signal (e.g., the first control signal CTRL1 and the second control signal CTRL2 are set to a high level), switches S1 and S3 are turned on, and switches S2 and S4 are turned off. When the current IL in the inductor L reaches the first current threshold, the first switching node voltage VSW1 is lower than the second reference voltage VREF2. The first peak signal Ipeak1 output by the peak current comparator 203 flips to a low level. The logic circuit 207 resets the second control signal CTRL2 according to the low-level state of the first peak signal Ipeak1 (e.g., the second control signal CTRL2 is set to a low level), thereby turning off switch S3 and turning on switch S4. When the on-time of power switch S1 reaches the time threshold Ton, logic circuit 207 resets the first control signal CTRL1 (e.g., the first control signal CTRL1 flips to a low level) to turn off power switch S1 and turn on power switch S2. When the current IL in inductor L reaches the second current threshold, the second switching node voltage SW2 is higher than the third reference voltage VREF3, and the second peak signal Ipeak2 output by peak current comparator 204 flips to a high level. Logic circuit 207 sets the second control signal CTRL2 again according to the high-level second peak signal Ipeak2 to turn on switch S3 and turn off switch S4. The above process is repeated continuously to regulate the output voltage VOUT. Furthermore, the control circuit of the buck-boost converter in this embodiment is also used to control the average current in inductor L according to the current clamping signal Iclamp in each switching cycle so that the average current of the system reaches a constant value. That is, logic circuit 207 detects whether the current clamping signal Iclamp is low before the pulse width modulation signal PWM reaches a high level. If the current clamping signal Iclamp is low, power switches S1 and S3 are turned on according to the rising edge of the pulse width modulation signal PWM, and the above control process is repeated. If the current clamping signal Iclamp is high, power switches S1 and S3 are turned on only when the falling edge of the current clamping signal Iclamp is detected, and then the above control process is repeated. Thus, the ripple current can be adjusted by regulating the off-time of power switch S1 in each switching cycle, thereby making the ripple current constant and ultimately making the average current of inductor L constant.

[0055] Figure 3A schematic circuit diagram of an average current limiting circuit 206 according to an embodiment of the present invention is shown. Figure 3 As shown, the average current limiting circuit 206 includes a current source 261, a bias current source 262, a capacitor C1, a comparator 263, and a switch K1. The current source 261 is coupled to a first terminal of the capacitor C1, and the second terminal of the capacitor C1 is coupled to ground. The current source 261 provides a charging current to the capacitor C1 with a magnitude equivalent to the current sampling signal ISENSE. For example, the current source 261 can be implemented using a current mirror, providing the charging current to the capacitor C1 in a mirrored manner according to the current sampling signal ISENSE. The bias current source 262 has a first terminal and a second terminal. Its first terminal is coupled to the first terminal of the capacitor C1, and its second terminal is coupled to ground. The bias current source 262 provides a set bias current Ibias and discharges the capacitor C1 according to the set bias current Ibias, i.e., the discharge current of the capacitor C1 is equal to the bias current Ibias. Comparator 263 has a non-inverting input, an inverting input, and an output. Its non-inverting input is coupled to a first terminal of capacitor C1, and its inverting input is coupled to a comparison threshold (e.g., a reference ground voltage). Comparator 263 compares the voltage VC of capacitor C1 with a threshold voltage and provides a current clamping signal Iclamp at the output based on the comparison result. Switch K1 has a first terminal and a second terminal. Its first terminal is coupled to the first terminal of capacitor C1, and its second terminal is coupled to ground. Switch K1 is briefly turned on before each switching cycle to release the charge in capacitor C1. For example, a narrow pulse circuit can be used to generate the control signal for switch K1, which can provide a narrow pulse control signal to switch K1 before the start of each switching cycle by detecting the control signal of power switch Q1.

[0056] Figure 4 The diagram shows the operating waveforms of the average current limiting circuit according to an embodiment of the present invention. Figure 4 The waveforms of the inductor current IL, the current sampling signal ISENSE, the bias current Ibias, and the control signal of switch K1 are shown respectively. Among them, the current sampling signal ISENSE = I... VIN / n, where I VIN Let represent the magnitude of the current supplied at the input voltage VIN terminal, n be the scaling factor between the sampling transistor and the power switch S1 in the current sampling circuit 201, T be one switching cycle of the system, and Ton be the on-time of the power switch S1 in one switching cycle T. Then, the amount of charge that the current sampling signal ISENSE charges on capacitor C1 in one switching cycle is:

[0057]

[0058] The amount of charge discharged by the bias current Ibias to capacitor C1 during one switching cycle is:

[0059] Q2 = Ibias * T

[0060] If we want the average input current to remain constant, then Q1 = Q2, and the average input current ī is:

[0061]

[0062] As can be seen from the above formula, the average circuit error of the buck-boost converter comes from two aspects: the accuracy of current sampling and the accuracy of the bias current source. These two aspects can be designed to meet the high accuracy requirements. Therefore, the average current limiting circuit in this embodiment can achieve the high accuracy requirements.

[0063] Figure 5 A schematic circuit diagram of a bias current source 262 according to an embodiment of the present invention is shown. Figure 5 As shown, the bias current source 262 in this embodiment includes an operational amplifier 2621, PMOS transistors M1 and M2, a resistor R1, NMOS transistors M3 and M4, switches K2 and K3, and a sample-and-hold module 2622.

[0064] PMOS transistors M1 and M2 have a source, a gate, and a drain. The sources of PMOS transistors M1 and M2 are coupled to the input voltage VIN, and the gates of PMOS transistors M1 and M2 are coupled to each other. Resistor R1 has a first terminal and a second terminal. The first terminal of resistor R1 is coupled to the drain of PMOS transistor M1, and the second terminal of resistor R1 is coupled to ground. Operational amplifier 2621 has a non-inverting input, an inverting input, and an output. The non-inverting input receives a fourth reference voltage VREF4, the inverting input is coupled to the drain of PMOS transistor M1 and the first terminal of resistor R1, and its output is coupled to the gates of PMOS transistors M1 and M2. NMOS transistor M3 has a source, a gate, and a drain. Its drain and gate are coupled to the drain of PMOS transistor M2, and its source is coupled to ground. Switch K2 has a first terminal and a second terminal. Its first terminal is coupled to the source of PMOS transistors M1 and M2, and its second terminal is coupled to the gate of PMOS transistors M1 and M2. Switch K3 has a first terminal and a second terminal. Its first terminal is coupled to the gate and drain of NMOS transistor M3, and its second terminal is coupled to the input terminal of sample-and-hold module 2622. NMOS transistor M4 has a source, a gate, and a drain. Its gate is coupled to the output terminal of sample-and-hold module 2622, its source is coupled to ground, and its drain is used to output bias current Ibias.

[0065] In this embodiment, switches K2 and K3 are not overlapped during conduction. During the first time period of a switching cycle (i.e., Ton + Tdelay), switch K2 is off and switch K3 is on, where Ton represents the conduction time of power switch S1 in each switching cycle, and Tdelay represents the additional time for shielding the interference caused by the instant power switch S2 is turned on. During the second time period of a switching cycle (i.e., T - (Ton + Tdelay)), switch K2 is on and switch K3 is off.

[0066] In the first time period of a switching cycle, operational amplifier 2621 generates a current I1 = VREF4 / R1 across resistor R1 by clamping the gate voltage of PMOS transistor M1. In this embodiment, by designing PMOS transistors M1 and M2 to have equal dimensions, PMOS transistor M2 obtains current I2 by mirroring the current I1 on PMOS transistor M1, i.e., current I2 = I1 = VREF4 / R1. NMOS transistor M3 converts current I2 into a voltage signal and uses this voltage signal to control the gate voltage of NMOS transistor M4, converting it back into a current signal, i.e., bias current Ibias = I1 = VREF4 / R1. In the second time period, switch K2 is turned on and switch K3 is turned off. Therefore, operational amplifier 2621 and current mirror on the left side of bias current source circuit 262 in this embodiment no longer work. Thus, the power consumption drawn from the input voltage VIN by the entire circuit is 0 during this time period, which can minimize the power consumption of the circuit and improve circuit efficiency. Furthermore, since the sample-and-hold module 2622 has sampled and held the voltage signal converted by the NMOS transistor M3 in the first time period, the bias current Ibias remains at VREF4 / R1 in the second time period. Therefore, the bias current source circuit 262 in this embodiment can not only generate a higher precision bias current, but also minimize circuit power consumption by operating in a time-sharing manner, making it suitable for ultra-low power buck-boost converter circuit systems.

[0067] Figure 6 A timing diagram of the operation of a buck-boost converter according to an embodiment of the present invention is shown. Figure 6The horizontal axis in the diagram represents the time interval, where T represents one switching cycle. The first row represents the feedback signal VFB and the first reference voltage VREF1 fed into the PWM comparator 202. The second row represents the inductor current IL in the inductor L. The third row represents the pulse width modulation signal PWM generated by the PWM comparator 202. The fourth row represents the current clamping signal Iclamp generated by the comparator 263 in the average current limiting circuit 206. The fifth row represents the voltage VC on the capacitor C1 in the average current limiting circuit 206. The sixth and seventh rows represent the first peak signal Ipeak1 and the second peak signal Ipeak2 generated by the peak current comparators 203 and 204, respectively. The eighth and ninth rows represent the first control signal CTRL1 and the second control signal CTRL2 generated by the logic circuit 207, respectively. The tenth to thirteenth rows represent the drive signals DRV1 to DRV4 generated by the drive circuit 208, respectively.

[0068] Combination Figure 2 , Figure 3 and Figure 6 The operating principle of the buck-boost converter in this embodiment will be explained. At time t0, the feedback signal VFB is lower than the first reference voltage VREF1. (Return to reference) Figure 2 The output of PWM comparator 202 generates a logic level "1" and provides this logic level "1" to logic circuit 207. Simultaneously, at time t0, the voltage VC on capacitor C1 is not higher than the reference ground potential GND. Therefore, the output of comparator 263 generates a current clamping signal Iclamp with a logic level of "0". Logic circuit 207 outputs a first control signal CTRL1 with a logic level of "1" based on the current clamping signal Iclamp with a logic level of "0" and the PWM signal with a logic level of "1". Drive circuit 208 turns off power switch S2 based on the first control signal CTRL1 with a logic level of "1" and turns on power switch S1 after a suitable delay. Furthermore, since the second control signal CTRL2 is also at a logic level of "1" at time t0, power switch S3 is turned on and power switch S4 is turned off. Therefore, from time t0 to time t1, power switches S2 and S4 are turned off, and power switches S1 and S3 are turned on. As a result of turning on power switches S1 and S3, the current IL in inductor L increases linearly with a first slope from time t0 to time t1. From time t0 to time t1, the current sampling signal ISENSE charges capacitor C1, so the voltage VC on capacitor C1 increases linearly, and the current clamping signal Iclamp output by comparator 263 is in a logic high state.

[0069] At time t1, the current IL in inductor L reaches the first current threshold. The first peak signal Ipeak1 output by peak current comparator 203 exhibits a downward-flipping pulse signal, which is provided to logic circuit 207. Logic circuit 207 resets the second control signal CTRL2 to logic level "0" based on the pulse signal appearing on the first peak signal Ipeak1. Drive circuit 208 turns off power switch S3 based on the second control signal CTRL2 at logic level "0", and turns on power switch S4 after a suitable delay. Therefore, from time t1 to time t2, power switches S1 and S4 are on, while power switches S2 and S3 are off. As a result of turning off power switch S3, from time t1 to time t2, the current IL in inductor L changes linearly with a second slope less than the first slope.

[0070] At time t2, the on-time of power switch S1 reaches the time threshold Ton. Logic circuit 207 resets the first control signal CTRL1 to logic level "0". Drive circuit 208 turns off power switch S1 according to the first control signal CTRL1 at logic level "0" and turns on power switch S2 after a suitable delay. Therefore, from time t2 to time t3, power switches S1 and S3 are off, and power switches S2 and S4 are on. As a result of power switch S2 being on, the current IL in inductor L decreases linearly. From time t2 to time t3, due to the shutdown of current sampling circuit 201, capacitor C1 is discharged by bias current source 262, and the voltage VC on capacitor C1 decreases linearly.

[0071] At time t3, the current IL in inductor L reaches the second current threshold. An upward-flipping pulse signal appears in the second peak signal Ipeak2 output by peak current comparator 204, and this pulse signal is provided to logic circuit 207. Logic circuit 207 again sets the second control signal CTRL2 to logic level "1". Drive circuit 208 turns off power switch S4 according to the logic level "1" second control signal CTRL2, and after a suitable delay, turns on power switch S3. Therefore, from time t3 to time t4, power switches S1 and S4 are off, and power switches S2 and S3 are on.

[0072] At time t4, the feedback signal VFB falls below the first reference voltage VREF1 again. The output of PWM comparator 202 generates a logic level "1" and provides this logic level "1" to logic circuit 207. Logic circuit 207 simultaneously detects whether the current clamping signal Iclamp is in a logic low state. As shown in the figure, the current clamping signal Iclamp is still in a logic level "0" at time t4. Therefore, logic circuit 207 sets the first control signal CTRL1 to a logic high state according to the PWM signal with a logic level of "1" to turn on power switch S1 and turn off power switch S2. It can be understood that there is a certain delay time between the switching of the two. Then, another switching cycle begins, and the circuit repeats the process from time t0 to t3.

[0073] If the current clamping signal Iclamp is in a logic high state when the rising edge of the output signal of the PWM comparator 202 arrives, it means that the average input current of the circuit has reached the current limit value. Therefore, the logic circuit 207 will not immediately turn on the power switch S1 to charge the circuit. Figure 6 As shown at time t5, at time t5, the output of PWM comparator 202 generates a logic level "1", and the current clamping signal Iclamp is also at a logic level "1". Logic circuit 207 continues to maintain the first control signal CTRL1 at a logic level "0". At this time, power switches S1 and S4 remain off, while power switches S2 and S3 remain on. Until time t6, when the current clamping signal Iclamp flips to a logic level "0", logic circuit 207 sets the first control signal CTRL1 to a logic level "1", then turns off power switch S2 and turns on power switch S1, after which the circuit switching cycle begins.

[0074] If the feedback signal VFB remains below the first reference voltage VREF1 after the charging process ends, that is, if the pulse width modulation signal PWM output by the PWM comparator 202 remains in a logic high state after the charging process ends, then the logic circuit 207 controls the charging time of the next switching cycle according to the state of the current clamping signal Iclamp. If the current clamping signal Iclamp is in a logic high state, it means that the average input current of the circuit is higher than the current limit value. The switching element S1 is turned on again when the falling edge of the current clamping signal Iclamp arrives, so as to start the charging process of the next switching cycle.

[0075] In summary, the buck-boost converter and its control circuit and method provided in this embodiment of the invention use a combination of constant on-time control, peak current mode control, and average current limiting control to control the switching of the buck-boost converter. The control circuit includes an average current limiting circuit, which compares the current sampling signal obtained by the current sampling circuit with a set bias current, generates a current clamping signal based on the comparison result, and then the logic circuit controls the charging timing of the inductor in each switching cycle based on the combination of the PWM signal and the current clamping signal. That is, when the rising edge of the PWM signal arrives, the logic circuit first judges the level state of the current clamping signal; only when the current clamping signal is logic low will it begin charging the inductor, thereby controlling the current in the inductor and ultimately ensuring that the average current in the inductor reaches a constant value. Furthermore, the solution provided in this embodiment does not require operational amplifiers and large RC networks for filtering and shaping in the circuit, thus resulting in a faster response speed and rapid limitation of the input average current.

[0076] Furthermore, this embodiment of the invention also provides a bias current source circuit for an average current limiting circuit. This bias current source circuit generates bias current by using a time-sharing operation combined with a sample-and-hold method. This not only generates a higher precision bias current, but also minimizes circuit power consumption by using a time-sharing operation method, making it suitable for ultra-low power buck-boost converter circuit systems.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a buck-boost converter, the buck-boost converter comprising a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control circuit comprising: A current sampling circuit is used to detect the current flowing through the inductor and generate a current sampling signal; An average current limiting circuit is used to compare the current sampling signal with a set bias current to generate a current clamping signal; A PWM comparator is used to compare the feedback signal of the output voltage with a first reference voltage to generate a pulse width modulation signal; as well as A logic circuit is configured to control the on-time of the first power switch in each switching cycle based on a combination of the current clamping signal and the pulse width modulation signal. The logic circuit is configured to control the first power switch to turn on when the pulse width modulation signal is in a logic high state and the current clamping signal is in a logic low state during each switching cycle.

2. The control circuit according to claim 1, wherein, The average current limiting circuit includes: A capacitor, wherein the second terminal of the capacitor is coupled to ground; A current source circuit, coupled to the first terminal of the capacitor, is used to provide the capacitor with a charging current of an amount equivalent to the current sampling signal; A bias current source circuit, having a first terminal coupled to a first terminal of the capacitor and a second terminal coupled to ground, is used to discharge the capacitor according to a set bias current; and A comparator is used to compare the voltage of the capacitor with a threshold voltage to generate the current clamping signal.

3. The control circuit according to claim 2, wherein the threshold voltage has a reference ground potential.

4. The control circuit according to claim 2, wherein, The average current limiting circuit also includes: A first switch, coupled between a first terminal of the capacitor and ground, is used to briefly turn on the capacitor before the first power switch turns on, in order to release the charge within the capacitor.

5. The control circuit according to claim 2, wherein, The bias current source circuit includes: A first transistor and a resistor are coupled between the input voltage and ground; A second transistor and a third transistor are coupled between the input voltage and ground; An operational amplifier, wherein the non-inverting input is coupled to a fourth reference voltage, the inverting input is coupled to the common terminal of the first transistor and the resistor, and the output is coupled to the control terminals of the first transistor and the second transistor; The second switch has a first terminal coupled to the input voltage and a second terminal coupled to the control terminals of the first transistor and the second transistor. The third switch has its first terminal coupled to the control terminal and the first terminal of the third transistor; The sample-and-hold module has its input terminal coupled to the second terminal of the third switch; and The fourth transistor has its control terminal coupled to the output terminal of the sample-and-hold module, its second terminal coupled to ground, and its first terminal used to provide the bias current.

6. The control circuit according to claim 5, wherein, The second switch and the third switch are configured to be time-division complementary during a switching cycle.

7. The control circuit according to claim 6, wherein, In a first time period within a switching cycle, the second switch is off and the third switch is on; in a second time period within a switching cycle other than the first time period, the second switch is on and the third switch is off.

8. The control circuit according to claim 7, wherein, The first time period is a combination of the conduction time of the first power switch within one switching cycle and the delay time between the first power switch and the second power switch.

9. The control circuit according to claim 5, wherein, The first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

10. The control circuit according to claim 1, further comprising: The on-time control circuit is used to compare the on-time of the first power switch in one switching cycle with a time threshold to generate an on-time control signal for controlling the off-time of the first power switch.

11. The control circuit according to claim 1, further comprising: A first peak current comparator is used to compare the voltage of the first switching node with a second reference voltage to generate a first peak signal for controlling the turn-off time of the third power switch in each switching cycle.

12. The control circuit according to claim 1, further comprising: A second peak current comparator is used to compare the voltage of the second switching node with a third reference voltage to generate a second peak signal for controlling the on-time of the third power switch in each switching cycle.

13. A control method for a buck-boost converter, the buck-boost converter comprising a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control method comprising: The current flowing through the inductor is detected, and a current sampling signal is generated; The current sampling signal is compared with a set bias current to generate a current clamping signal; The feedback signal of the output voltage is compared with the first reference voltage to generate a pulse width modulation signal; as well as The on-time of the first power switch in each switching cycle is controlled by a combination of the current clamping signal and the pulse width modulation signal. Specifically, in each switching cycle, when the pulse width modulation signal is in a logic high state and the current clamping signal is in a logic low state, the first power switch is controlled to turn on.

14. The control method according to claim 13, wherein, The step of comparing the current sampling signal with a set bias current to generate a current clamping signal includes: Provide a capacitor; A charging current equivalent to the current sampling signal is provided to the capacitor; Provide a set bias current, and discharge the capacitor according to the bias current; and The voltage of the capacitor is compared with a threshold voltage to generate the current clamping signal.

15. The control method according to claim 14, wherein, The step of comparing the current sampling signal with a set bias current to generate a current clamping signal further includes: The charge in the capacitor is released before the first power switch is turned on in each switching cycle.

16. The control method according to claim 13, further comprising: The on-time of the first power switch within one switching cycle is compared with a time threshold to generate an on-time control signal, and the off-time of the first power switch within one switching cycle is controlled according to the on-time control signal.

17. The control method according to claim 13, further comprising: The voltage of the first switching node is compared with the second reference voltage to generate a first peak signal, and the turn-off time of the third power switch is controlled according to the first peak signal in a switching cycle.

18. The control method according to claim 13, further comprising: The voltage of the second switching node is compared with a third reference voltage to generate a second peak signal, and the conduction time of the third power switch is controlled according to the second peak signal within a switching cycle.

19. A buck-boost converter, comprising: A first power switch coupled between the input voltage and the first switching node; A second power switch coupled between the first switching node and reference ground; A third power switch coupled between the second switching node and reference ground; A fourth power switch coupled between the second switching node and the output voltage; as well as An inductor coupled between the first switching node and the second switching node; as well as The control circuit according to any one of claims 1-12.

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