A method and apparatus for detecting and protecting against hybrid converter valve triggering faults

Abstract

The application belongs to the technical field of direct current transmission, and particularly relates to a detection method and protection method and device for trigger faults of a hybrid converter valve, trigger signals of thyristors and IGBTs are detected, trigger fault signals of mis-triggering, non-triggering of the thyristor valve, mis-triggering, non-triggering and mis-shutoff and non-shutoff of the IGBT valve are output, trigger fault protection signals of the bridge arm are generated according to the trigger fault signals, and then the switching of the fault bridge arm or the system working mode and the protection of the whole system are carried out. The application solves the problem of over-high energy of the lightning arrester caused by the trigger faults of the thyristors and IGBTs, and effectively reduces the over-high electrical stress of the valve caused by the trigger faults of the valve.

Description

Technical Field

[0001] This invention belongs to the field of DC power transmission technology, specifically relating to a method and device for detecting and protecting valve-triggered faults in a hybrid converter. Background Technology

[0002] Conventional high-voltage direct current (LCC-HVDC) transmission technology has advantages such as mature application, low cost, and low loss. However, LCC-HVDC is prone to commutation failure, thus leading to the development of hybrid converter topologies with active commutation. Existing CLCC topologies include... Figure 1 As shown, each bridge arm consists of a main branch and an auxiliary branch connected in parallel. The main branch is composed of a V11 thyristor sub-valve and a V12 IGBT sub-valve connected in series, while the auxiliary branch is composed of a V13 IGBT sub-valve and a V14 thyristor valve connected in series. A thyristor bypass branch is connected in parallel across the two ends of the V12 IGBT sub-valve of the main branch, serving as part of the thyristor valve for exiting CLCC operation and returning to LCC operation.

[0003] While existing CLCC topologies address commutation failure during AC / DC line faults, they do not consider scenarios involving abnormal drive pulses. During natural commutation, if a sub-valve experiences a false triggering or non-triggering fault, commutation will fail. For example, if sub-valve V11 fails to trigger or is falsely triggered, more severe cases will lead to excessive surge arrester energy in parallel with sub-valves V12 and V13, resulting in thermal damage to the corresponding arresters. For instance, if sub-valve V12 fails to trigger or is falsely shut off, the surge arrester in parallel with sub-valve V12 will exceed its energy limit; similarly, if sub-valve V11 is falsely triggered or fails to trigger, the surge arresters in both sub-valve V12 and V13 will exceed their energy limits. Therefore, a systematic detection and protection solution is needed to address issues such as excessive surge arrester energy in parallel across valves due to abnormal sub-valve trigger pulses, and excessive electrical stress on valves caused by triggering faults.

[0004] Previously, conventional high-voltage direct current transmission (LCC-HVDC) mainly detected triggering faults at the bridge arm level, but did not detect triggering faults at the valve level. However, the CLCC topology is a new topology recently proposed to solve the problem of commutation failure. It has not yet been applied in engineering, and its sub-valve level triggering faults are a unique problem. There is currently no relevant research content. Therefore, it is necessary to detect triggering faults and provide corresponding protection for the sub-valves of the CLCC topology. Summary of the Invention

[0005] The purpose of this invention is to provide a method and apparatus for detecting hybrid converter valve triggering faults, so as to accurately identify hybrid converter valve triggering faults; this invention also provides a method and apparatus for protecting against hybrid converter valve triggering faults, so as to solve the problems of excessive surge arrester energy and excessive valve electrical stress caused by the inability to accurately identify hybrid converter valve triggering faults.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for detecting valve triggering faults in a hybrid converter. The hybrid converter includes six bridge arms, each bridge arm including a main branch and an auxiliary branch connected in parallel. A thyristor and an IGBT are connected in series on the main branch, and an IGBT and a thyristor are connected in series on the auxiliary branch. The method for detecting valve triggering faults includes detecting valve triggering faults in the thyristors and / or IGBTs.

[0007] The following method is used to detect valve triggering faults in thyristors:

[0008] If the pulse width of each cycle of the trigger signal is greater than the first preset time, it is determined to be a thyristor false triggering fault;

[0009] If the low-level time of each cycle of the trigger signal is greater than the second preset time, it is determined that the thyristor is not triggering.

[0010] Use at least one of the following methods to detect valve triggering faults in IGBTs:

[0011] Option 1: If the pulse width of each cycle of the trigger signal is greater than the third preset time, it is determined to be an IGBT false triggering fault;

[0012] Option 2: If the low-level time of each cycle of the trigger signal is greater than the fourth preset time, it is determined that the IGBT is not triggering.

[0013] Option 3: If the pulse width of each cycle of the trigger signal is less than the fifth preset time, it is determined to be an IGBT false turn-off fault;

[0014] Option 4: If the low-level time of each cycle of the trigger signal is less than the sixth preset time, it is determined to be an IGBT non-turn-off fault.

[0015] The first preset time is shorter than the second preset time.

[0016] Its beneficial effects are as follows: This invention detects the triggering signals of the thyristor and IGBT by detecting the triggering signals of the output thyristor valve (false triggering, no triggering) and the IGBT valve (false triggering, no triggering, false turn-off, and no turn-off). By accurately detecting the pulse width and low-level time of each cycle of the triggering signal, the method is simple, can accurately determine the fault type, improves detection efficiency, facilitates protection against valve triggering faults, improves system stability, and effectively avoids the problems of excessive surge arrester energy and excessive valve electrical stress caused by the inability to detect valve triggering faults in time.

[0017] Furthermore, if a valve triggering fault is determined to have occurred in the hybrid converter, the triggering fault signal state is changed to indicate that a valve triggering fault has occurred.

[0018] Its beneficial effects are: changing the state of the trigger fault signal, making it easier to protect against valve trigger faults, and improving system stability.

[0019] To address the aforementioned technical problems, the present invention also provides a hybrid converter valve triggering fault detection device, comprising a processor and a memory. The processor is used to execute program instructions stored in the memory to implement the hybrid converter valve triggering fault detection method described above.

[0020] Its beneficial effects are as follows: The present invention adopts a hybrid converter valve triggering fault detection device, which detects the triggering signals of the thyristor and IGBT by detecting the triggering signals of the output thyristor valve (false triggering, no triggering) and the IGBT valve (false triggering, no triggering, false shut-off, and no shut-off). This facilitates protection against valve triggering faults, improves system stability, and effectively avoids problems such as excessive surge arrester energy and excessive valve electrical stress.

[0021] To address the aforementioned technical problems, this invention also provides a method for protecting against valve-triggered faults in a hybrid converter. The hybrid converter includes six arms, each arm comprising a main branch and an auxiliary branch connected in parallel. A thyristor and an IGBT are connected in series on the main branch, and an IGBT and a thyristor are connected in series on the auxiliary branch. The method for protecting against valve-triggered faults in the hybrid converter includes:

[0022] 1) The following method is used to detect valve triggering faults in hybrid converters, including valve triggering fault detection of thyristors and / or IGBTs;

[0023] The following method is used to detect valve triggering faults in thyristors:

[0024] If the pulse width of each cycle of the trigger signal is greater than the first preset time, it is determined to be a thyristor false triggering fault;

[0025] If the low-level time of each cycle of the trigger signal is greater than the second preset time, it is determined that the thyristor is not triggering.

[0026] Use at least one of the following methods to detect valve triggering faults in IGBTs:

[0027] Option 1: If the pulse width of each cycle of the trigger signal is greater than the third preset time, it is determined to be an IGBT false triggering fault;

[0028] Option 2: If the low-level time of each cycle of the trigger signal is greater than the fourth preset time, it is determined that the IGBT is not triggering.

[0029] Option 3: If the pulse width of each cycle of the trigger signal is less than the fifth preset time, it is determined to be an IGBT false turn-off fault;

[0030] Option 4: If the low-level time of each cycle of the trigger signal is less than the sixth preset time, it is determined to be an IGBT non-turn-off fault.

[0031] The first preset time is shorter than the second preset time.

[0032] 2) If any thyristor or IGBT experiences a valve-triggered fault, fault protection will be implemented, and the operating mode of the bridge arm containing the faulty thyristor or IGBT will be switched from CLCC mode to LCC mode.

[0033] Its beneficial effects are as follows: This invention detects the trigger signals of thyristors and IGBTs, outputs trigger fault signals for thyristor valve mis-triggering, non-triggering, and IGBT valve mis-triggering, non-triggering, mis-shutdown, and non-shutdown, and generates a trigger fault protection signal for the bridge arm based on the trigger fault signal, thereby switching the working mode of the faulty bridge arm or the system, and protecting the entire system. This solves the problem of excessive surge arrester energy caused by thyristor and IGBT trigger faults, and effectively reduces the excessive electrical stress on the valve caused by valve trigger faults.

[0034] Furthermore, if a valve-triggered fault occurs in the thyristor of the main branch, after fault protection is implemented, the bridge arm containing the thyristor of the main branch where the valve-triggered fault occurred is immediately switched from CLCC mode to LCC mode, or the entire bridge arm is switched from CLCC mode to LCC mode.

[0035] Its beneficial effects are as follows: by detecting the trigger signals of thyristors and IGBTs, it outputs trigger fault signals for thyristor valves that are falsely triggered or not triggered, as well as for IGBT valves that are falsely triggered, not triggered, falsely turned off, or not turned off. Based on the trigger fault signals, it generates trigger fault protection signals for bridge arms, thereby switching the working mode of the faulty bridge arm or the system, and protecting the entire system. This solves the problem of excessive surge arrester energy caused by trigger faults of thyristors and IGBTs, and effectively reduces the excessive electrical stress on valves caused by valve trigger faults.

[0036] Furthermore, after switching to LCC mode, if the fault duration is greater than or equal to the seventh preset time or the number of times the fault signal is triggered is greater than or equal to the first preset number, it is determined to be a serious valve triggering fault of the main branch thyristor; if the fault duration is less than the seventh preset time or the number of times the fault signal is triggered is less than the first preset number, and a valve-less triggering fault of the main branch thyristor is detected, the bridge arm where the main branch thyristor is located is controlled to be restored from LCC mode to CLCC mode or the whole is restored from LCC mode to CLCC mode.

[0037] The beneficial effect is that the fault trigger signal generates a fault protection signal for the bridge arm, thereby switching the working mode of the faulty bridge arm or the system to protect the entire system.

[0038] Furthermore, if a valve-triggered fault is detected in any of the main branch IGBTs, auxiliary branch thyristors, or auxiliary branch IGBTs, then after the eighth preset time for fault protection, the bridge arm containing the thyristor or IGBT that caused the valve-triggered fault is switched from CLCC mode to LCC mode, or the entire bridge arm is switched from CLCC mode to LCC mode.

[0039] Its beneficial effects are: based on the trigger fault signal, a trigger fault protection signal for the bridge arm is generated, thereby switching the working mode of the faulty bridge arm or the system to protect the entire system.

[0040] Furthermore, after switching to LCC mode, if the number of times the fault signal is triggered is greater than or equal to the second set number, it is determined that the corresponding IGBT or thyristor has a serious valve triggering fault; if the number of times the fault signal is triggered is less than the second set number, and a valve-less triggering fault is detected in the corresponding IGBT or thyristor, the bridge arm containing the corresponding IGBT or thyristor is controlled to return from LCC mode to CLCC mode or the entire bridge arm is controlled to return from LCC mode to CLCC mode.

[0041] Its beneficial effects are: based on the trigger fault signal, a trigger fault protection signal for the bridge arm is generated, thereby switching the working mode of the faulty bridge arm or the system to protect the entire system.

[0042] To address the aforementioned technical problems, the present invention also provides a hybrid converter valve triggering fault protection device, comprising a processor and a memory, wherein the processor is used to execute program instructions stored in the memory to implement the hybrid converter valve triggering fault protection method described above.

[0043] Its beneficial effects are as follows: The present invention adopts a hybrid converter valve triggering fault detection device, which detects the triggering signals of thyristors and IGBTs, and outputs triggering fault signals of thyristor valve mis-triggering, non-triggering, and IGBT valve mis-triggering, non-triggering, mis-shutdown, and non-shutdown. Based on the triggering fault signals, a triggering fault protection signal for the bridge arm is generated, thereby switching the working mode of the faulty bridge arm or the system, and protecting the entire system. This solves the problem of excessive surge arrester energy caused by thyristor and IGBT triggering faults, and effectively reduces the excessive electrical stress on the valve caused by valve triggering faults. Attached Figure Description

[0044] Figure 1 A schematic diagram of the existing active commutation hybrid converter topology;

[0045] Figure 2 This is a schematic diagram of the thyristor triggering fault detection method of the present invention;

[0046] Figure 3 This is a schematic diagram of the IGBT triggering fault detection method of the present invention;

[0047] Figure 4 This is a schematic diagram of the V11 sub-valve false triggering fault detection of the present invention;

[0048] Figure 5 This is a schematic diagram of the V11 sub-valve non-triggering fault detection of the present invention;

[0049] Figure 6 This is a schematic diagram of the V12 sub-valve false triggering fault detection of the present invention;

[0050] Figure 7 This is a schematic diagram of the V12 sub-valve non-triggering fault detection of the present invention;

[0051] Figure 8 This is a schematic diagram of the fault detection for the V12 sub-valve erroneous shut-off of the present invention;

[0052] Figure 9 This is a schematic diagram of the fault detection method for the V12 sub-valve not shutting off in this invention;

[0053] Figure 10 This is a flowchart of the fault protection method of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0055] This invention is aimed at such as Figure 1 The hybrid converter shown is an actively commutated converter composed of six identical bridge arms: V1, V2, V3, V4, V5, and V6. Each bridge arm consists of a main branch and an auxiliary branch connected in parallel. Taking bridge arm V1 as an example, the main branch consists of a V11 thyristor sub-valve and a V12 IGBT sub-valve connected in series, while the auxiliary branch consists of a V13 IGBT sub-valve and a V14 thyristor sub-valve connected in series. The thyristor sub-valve, like conventional valves, is equipped with a series saturated reactor, a parallel damping circuit, and a DC voltage equalization circuit. The IGBT sub-valve uses IGBTs in direct series connection, with an RCD buffer circuit connected in parallel across the IGBTs. Sub-converters V12, V13, and V14 also have surge arresters connected in parallel to limit overvoltage across them. Additionally, a thyristor bypass branch is connected in parallel across the V12 IGBT sub-valve in the main branch, serving as part of the thyristor valve's operation when exiting CLCC mode and returning to LCC mode.

[0056] For the thyristor (V11), the trigger pulse is triggered once every 20ms, with a pulse width of 120°, or 6.67ms. For the IGBT (V12) in the main branch, it is triggered once every 20ms, with a pulse width of 7.2ms. For the IGBT (V13) in the auxiliary branch, the pulse width is 8.7ms. For the thyristor (V14) in the auxiliary branch, the pulse is triggered once every 20ms, with a pulse width of 600µs. The trigger signals of the V11, V12, V13, and V14 sub-valves are detected using this method.

[0057] In this embodiment of the invention, the first preset time to the eighth preset time are T1-T8 respectively; the first set number of times is N1; and the second set number of times is N2.

[0058] Example of a method for detecting valve triggering faults in a hybrid converter:

[0059] against Figure 1 The present invention provides a method for detecting valve triggering faults in hybrid converters, as follows: Figures 2-9 As shown, it includes:

[0060] like Figure 2 As shown, the triggering faults of thyristors V11 and V14 include false triggering fault detection and non-triggering fault detection. The specific method for detecting false triggering faults is to detect the pulse width of each cycle of the thyristor trigger signal. If the pulse width is greater than T1 (e.g., 7ms), it indicates a false triggering fault. The non-triggering fault detection involves detecting the low-level duration of each cycle of the thyristor trigger signal. If the low-level duration is greater than T2 (e.g., 14ms), it indicates a non-triggering fault. If there is a false triggering or non-triggering fault, the triggering fault signal changes from low to high. In this embodiment, only the non-triggering and false triggering of sub-valve V11 and the non-triggering of sub-valve V14 are detected.

[0061] like Figure 3As shown, the triggering faults of IGBT sub-valve V12 and V13 include false triggering fault detection, no-triggering fault detection, false turn-off fault detection, and no-turn-off fault detection. The false triggering fault detection method specifically involves detecting the pulse width of each cycle of the IGBT trigger signal. If the pulse width is greater than T3 (e.g., 7ms), it indicates a false triggering fault. The no-triggering fault detection method involves detecting the low-level duration of each cycle of the IGBT trigger signal. If the low-level duration is greater than T4 (e.g., 15ms), it indicates a no-triggering fault. The IGBT false turn-off fault detection method involves detecting the pulse width of each cycle of the IGBT trigger signal. If the pulse width is less than T5 (e.g., 6ms), it indicates a false turn-off fault. The IGBT no-turn-off fault detection method involves detecting the low-level duration of each cycle of the IGBT trigger signal. If the low-level duration is less than T6 (e.g., 12ms), it indicates a no-turn-off fault. If there is a false triggering, no-triggering, false turn-off, or no-turn-off fault, the IGBT triggering fault signal changes from low to high. In this implementation case, only the non-triggering and false shut-off faults of the V12 sub-valve and the V13 sub-valve are detected.

[0062] like Figure 4 As shown, when zifaJC is high, the valve trigger fault detection and protection system of the hybrid converter is activated. In this embodiment, after 1.5s, zifaJC changes from low to high, indicating that the trigger fault detection of each sub-valve has started.

[0063] like Figure 4 As shown, for the false triggering of the V11 trigger signal, time integration is performed on 1, the V11 trigger signal T11 is inverted and then used as a clear signal. If the integration time exceeds 7ms, it indicates that the V11 trigger signal has a false triggering situation. At this time, the V11 trigger fault signal is output, and the level changes from low level to high level, indicating that V11 has a false triggering fault.

[0064] like Figure 5 As shown, for the non-triggering of the V11 trigger signal, the integral is performed with 1 in time. The V11 trigger signal T11 is used as a reset signal. If the integration time exceeds 15ms, it indicates that the V11 trigger signal has a non-triggering situation. At this time, the V11 trigger fault signal is output, and the level changes from low level to high level, indicating that V11 has a non-triggering fault.

[0065] like Figure 6 As shown, for the false triggering of the V12 trigger signal, the same time integration is performed on 1, the V12 trigger signal Tig12 is inverted and then used as the clear signal. If the integration time exceeds 7ms, it indicates that the V12 trigger signal has a false triggering situation. At this time, the V12 trigger fault signal is output, and the level changes from low level to high level, indicating that V12 has a false triggering fault.

[0066] like Figure 7 As shown, for the non-triggering of the V12 trigger signal, the integral is performed with 1 in time. The V12 trigger signal Tig12 is used as a clear signal. If the integration time exceeds 14ms, it indicates that the V12 trigger signal has a non-triggering fault. At this time, the V12 trigger fault signal is output, and the level changes from low level to high level, indicating that V12 has a non-triggering fault.

[0067] like Figure 8 As shown, for the erroneous shut-off of the V12 sub-valve, the V12 trigger signal Tig12 is inverted and used as the integration signal, which is integrated over time. At the same time, a pulse is sent to clear the signal once every 20ms. If the integration time exceeds 14ms, it indicates that the V12 trigger signal has erroneously shut off. At this time, the V12 trigger fault signal is output, and the level changes from low level to high level, indicating that there is an erroneous shut-off fault in V12.

[0068] like Figure 9 As shown, for the non-closing of the V12 sub-valve, the V12 trigger signal Tig12 is directly used as the integration signal and integrated over time. At the same time, a pulse is sent to clear the signal once every 20ms. If the integration time exceeds 8ms, it indicates that the V12 trigger signal is not closed. At this time, the V12 trigger fault signal is output, and the level changes from low level to high level, indicating that V12 has a faulty shutdown.

[0069] The fault detection method for non-triggering / false triggering of the V13 trigger signal is the same as that for the V12 sub-valve.

[0070] For the erroneous shutdown of the V13 trigger signal, the V13 trigger signal is inverted and used as an integral signal, which is integrated over time. At the same time, a pulse is sent to clear the signal once every 20ms. If the integration time exceeds 15ms, it indicates that the V13 trigger signal has an erroneous shutdown fault. At this time, the V13 trigger fault signal is output, and the level changes from low level to high level, indicating that the V13 has an erroneous shutdown fault.

[0071] If the V14 trigger signal fails to trigger, the integral is performed with 1 in time. The V14 trigger signal is used as a reset signal. If the integration time exceeds 21ms, it indicates that the V14 trigger signal has a failure to trigger. At this time, the V14 trigger fault signal is output, indicating that V14 has a failure to trigger.

[0072] Example of a hybrid converter valve trigger fault detection device:

[0073] The present invention includes a processor and a memory, including a processor, a memory and an internal bus, wherein the processor and the memory are connected through the internal bus, and the processor is used to execute computer program instructions stored in the memory to implement a valve triggering fault detection method described in the above embodiments of the hybrid converter valve triggering fault detection method.

[0074] The processor can be a microprocessor (MCU), a programmable logic device (FPGA), or other processing devices. The memory can be any type of memory that uses electrical energy to store information, such as RAM or ROM.

[0075] The specific method for detecting hybrid converter valve triggering faults has been described in detail in the embodiments of the method for detecting hybrid converter valve triggering faults, and will not be repeated here.

[0076] Example of a protection method for valve-triggered faults in a hybrid converter:

[0077] The method for protecting against valve-triggered faults in a hybrid converter according to the present invention includes the following steps:

[0078] 1) The following valve trigger fault detection method is adopted:

[0079] Detect valve triggering faults in thyristors and / or IGBTs;

[0080] The following method is used to detect valve triggering faults in thyristors:

[0081] If the pulse width of each cycle of the trigger signal is greater than the first preset time, it is determined to be a thyristor false triggering fault;

[0082] And / or if the low-level time of each cycle of the trigger signal is greater than the second preset time, it is determined that the thyristor does not trigger.

[0083] Use at least one of the following methods to detect valve triggering faults in IGBTs:

[0084] Option 1: If the pulse width of each cycle of the trigger signal is greater than the third preset time, it is determined to be an IGBT false triggering fault;

[0085] Option 2: If the low-level time of each cycle of the trigger signal is greater than the fourth preset time, it is determined that the IGBT is not triggering.

[0086] Option 3: If the pulse width of each cycle of the trigger signal is less than the fifth preset time, it is determined to be an IGBT false turn-off fault;

[0087] Option 4: If the low-level time of each cycle of the trigger signal is less than the sixth preset time, it is determined to be an IGBT non-turn-off fault;

[0088] The hybrid converter includes six bridge arms, each of which includes a main branch and an auxiliary branch connected in parallel. Thyristors and IGBTs are connected in series on the main branch, and IGBTs and thyristors are connected in series on the auxiliary branch.

[0089] 2) If a valve triggering fault occurs in the IGBT of the main branch, after fault protection is performed, the bridge arm where the IGBT of the main branch is located will be immediately switched from CLCC mode to LCC mode.

[0090] In CLCC mode, both the main and auxiliary branches of the bridge arm participate in system operation. In LCC mode, the thyristor bypass branch connected in parallel to both ends of the V12 sub-valve of the main branch is triggered. At this time, the auxiliary branch and the V12 sub-valve are out of operation. Only the V11 sub-valve of the main branch and the thyristor bypass branch connected in parallel to the V12 sub-valve are operational. When operating in CLCC mode, if a triggering fault occurs in V11, V12, V13, or V14, the surge arrester connected in parallel with V12, V13, or V14 will experience a surge in energy. Over time, this energy may exceed its limit, damaging the surge arrester. Therefore, it is necessary to switch from CLCC mode to LCC mode. When operating in LCC mode, the surge arrester of the V12, V13, or V14 sub-valve will not overvoltage and cause damage.

[0091] After switching to LCC mode, if the fault duration is greater than or equal to the seventh preset time or the number of times the fault signal is triggered is greater than or equal to the first set number, it is determined that the main branch thyristor has a serious triggering fault; if the fault duration is less than the seventh preset time or the number of times the fault signal is triggered is less than the first set number, and if a valveless triggering fault of the main branch thyristor is detected, the bridge arm where the main branch thyristor is located is controlled to return from LCC mode to CLCC mode.

[0092] If a valve triggering fault is detected in any of the main branch IGBTs, auxiliary branch thyristors, or auxiliary branch IGBTs, then after fault protection is implemented, for a preset period of eight hours, the bridge arm containing the thyristor or IGBT will be controlled to switch from CLCC mode to LCC mode, or the entire bridge arm will be switched from CLCC mode to LCC mode (where "the entire bridge arm" refers to all bridge arms).

[0093] After switching to LCC mode, if the number of times the fault signal is triggered is greater than or equal to the second set number, it is determined that any thyristor or IGBT in the main branch IGBT, auxiliary branch thyristor, or auxiliary branch IGBT has a serious triggering fault. If the number of times the fault signal is triggered is less than the second set number, and a valveless triggering fault is detected in any thyristor or IGBT in the main branch IGBT, auxiliary branch thyristor, or auxiliary branch IGBT, the bridge arm containing any thyristor or IGBT in the main branch IGBT, auxiliary branch thyristor, or auxiliary branch IGBT is controlled to revert from LCC mode to CLCC mode or switch the entire bridge arm from LCC mode to CLCC mode.

[0094] Specifically:

[0095] like Figure 10 As shown, the system detects the rising edge of the fault trigger signals for sub-valves V11, V12, V13, and V14, as well as the falling edge of the fault trigger signal for sub-valve V11. When a rising edge of the V11 signal is detected, the fault trigger protection signal of the bridge arm changes from low to high, and the bridge arm switches from CLCC operating mode to LCC operating mode. When a falling edge of the V11 signal is detected, the fault trigger protection signal of the bridge arm changes from high to low, and the bridge arm switches from LCC operating mode to CLCC operating mode, and then the detection continues. If the high level of the V11 sub-valve fault trigger signal lasts for more than 100ms, a serious fault triggering fault is reported for sub-valve V11 of the bridge arm, and a fault shutdown is initiated.

[0096] like Figure 10 As shown, when a rising edge of the trigger fault signal of V12, V13, or V14 is detected, the trigger fault protection signal of the corresponding bridge arm changes from low to high, with a duration of 80ms. This bridge arm exits CLCC operating mode and operates in LCC mode. When the trigger fault protection signal of this bridge arm changes from high to low, the bridge arm returns to CLCC operating mode. If the number of rising edges of the trigger fault signal of sub-valve V12, V13, or V14 exceeds three, a serious trigger fault is reported for the corresponding sub-valve, the active commutation function is disabled, and it switches to LCC mode for continuous operation.

[0097] This invention detects the trigger signals of thyristors and IGBTs, outputting trigger fault signals for thyristor valve mis-triggering, non-triggering, and IGBT valve mis-triggering, non-triggering, mis-shutdown, and non-shutdown. Based on these trigger fault signals, a bridge arm trigger fault protection signal is generated to switch the operating mode of the faulty bridge arm or the system, and to protect the entire system. This invention solves the problem of excessive surge arrester energy caused by thyristor and IGBT trigger faults, and effectively reduces excessive electrical stress on valves caused by valve trigger faults.

[0098] Example of a valve-triggered fault protection device for hybrid converter:

[0099] The present invention includes a processor and a memory, the processor, the memory and an internal bus, the processor and the memory being connected via the internal bus, the processor being used to execute computer program instructions stored in the memory to implement the above-mentioned protection method for valve triggering faults in hybrid converters.

[0100] The processor can be a microprocessor (MCU), a programmable logic device (FPGA), or other processing devices. The memory can be any type of memory that uses electrical energy to store information, such as RAM or ROM.

[0101] The specific method for protecting against valve-triggered faults in hybrid converters has been described in detail in the embodiments of the protection method for valve-triggered faults in hybrid converters, and will not be repeated here.

[0102] Specific implementation methods have been given above, but the present invention is not limited to the described implementation methods. The basic idea of ​​the present invention lies in the above basic scheme. For those skilled in the art, designing various modified models, formulas, and parameters based on the teachings of the present invention does not require creative effort. Changes, modifications, substitutions, and variations made to the implementation methods without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for detecting valve triggering faults in a hybrid converter, characterized in that, The hybrid converter includes six bridge arms, each bridge arm including a main branch and an auxiliary branch connected in parallel. Thyristors and IGBTs are connected in series on the main branch, and IGBTs and thyristors are connected in series on the auxiliary branch. The valve triggering fault detection method includes valve triggering fault detection of thyristors and IGBTs. The following method is used to detect valve triggering faults in thyristors: If the pulse width of each cycle of the trigger signal is greater than the first preset time, it is determined to be a thyristor false triggering fault; If the low-level time of each cycle of the trigger signal is greater than the second preset time, it is determined that the thyristor is not triggering. The following method is used to detect valve triggering faults in IGBTs: If the pulse width of each cycle of the trigger signal is greater than the third preset time, it is determined to be an IGBT false triggering fault. If the low-level time of each cycle of the trigger signal is greater than the fourth preset time, it is determined that the IGBT does not trigger. If the pulse width of each cycle of the trigger signal is less than the fifth preset time, it is determined to be an IGBT erroneous turn-off fault. If the low-level time of each cycle of the trigger signal is less than the sixth preset time, it is determined to be an IGBT non-turn-off fault. The first preset time is shorter than the second preset time.

2. The method for detecting valve triggering faults in a hybrid converter according to claim 1, characterized in that, If a valve triggering fault is detected in the hybrid converter, the triggering fault signal state is changed to indicate that a valve triggering fault has occurred.

3. A hybrid converter valve triggering fault detection device, characterized in that, It includes a processor and a memory, the processor being used to execute program instructions stored in the memory to implement the method for detecting valve triggering faults in a hybrid converter as described in any one of claims 1-2.

4. A protection method for valve-triggered faults in a hybrid converter, characterized in that, The hybrid converter includes six bridge arms, each including a main branch and an auxiliary branch connected in parallel. Thyristors and IGBTs are connected in series on the main branch, and IGBTs and thyristors are connected in series on the auxiliary branch. The protection method for valve-triggered faults in the hybrid converter includes: 1) Valve triggering fault detection of hybrid converter is performed using the following method, wherein valve triggering fault detection includes valve triggering fault detection of thyristors and IGBTs; The following method is used to detect valve triggering faults in thyristors: If the pulse width of each cycle of the trigger signal is greater than the first preset time, it is determined to be a thyristor false triggering fault; If the low-level time of each cycle of the trigger signal is greater than the second preset time, it is determined that the thyristor is not triggering. The following method is used to detect valve triggering faults in IGBTs: If the pulse width of each cycle of the trigger signal is greater than the third preset time, it is determined to be an IGBT false triggering fault. If the low-level time of each cycle of the trigger signal is greater than the fourth preset time, it is determined that the IGBT does not trigger. If the pulse width of each cycle of the trigger signal is less than the fifth preset time, it is determined to be an IGBT erroneous turn-off fault. If the low-level time of each cycle of the trigger signal is less than the sixth preset time, it is determined to be an IGBT non-turn-off fault. The first preset time is shorter than the second preset time; 2) If any thyristor or IGBT experiences a valve-triggered fault, fault protection will be implemented, and the operating mode of the bridge arm containing the thyristor or IGBT that experienced the valve-triggered fault will be switched from CLCC mode to LCC mode, or the entire bridge arm will be switched from CLCC mode to LCC mode.

5. The protection method for valve-triggered faults in a hybrid converter according to claim 4, characterized in that, If a thyristor in the main branch experiences a valve-triggered fault, after fault protection is implemented, the bridge arm containing the thyristor in the main branch experiencing the valve-triggered fault will be immediately switched from CLCC mode to LCC mode, or the entire bridge arm will be switched from CLCC mode to LCC mode.

6. The protection method for valve-triggered faults in a hybrid converter according to claim 5, characterized in that, After switching to LCC mode, if the fault duration is greater than or equal to the seventh preset time or the number of times the fault signal is triggered is greater than or equal to the first preset number, it is determined to be a serious valve triggering fault of the main branch thyristor; if the fault duration is less than the seventh preset time and the number of times the fault signal is triggered is less than the first preset number, and a valve-less triggering fault of the main branch thyristor is detected, the main branch thyristor bridge arm is controlled to be restored from LCC mode to CLCC mode or the whole is restored from LCC mode to CLCC mode.

7. The protection method for valve-triggered faults in a hybrid converter according to claim 6, characterized in that, If a valve-triggered fault is detected in any of the main branch IGBTs, auxiliary branch thyristors, or auxiliary branch IGBTs, then after the eighth preset time for fault protection, the bridge arm containing the thyristor or IGBT that caused the valve-triggered fault will be switched from CLCC mode to LCC mode, or the entire bridge arm will be switched from CLCC mode to LCC mode.

8. The protection method for valve-triggered faults in a hybrid converter according to claim 7, characterized in that, After switching to LCC mode, if the number of times the fault signal is triggered is greater than or equal to the second set number, it is determined that the corresponding IGBT or thyristor is in serious valve triggering fault; if the number of times the fault signal is triggered is less than the second set number, and the corresponding IGBT or thyristor is detected to be in valve-less triggering fault, the bridge arm containing the corresponding IGBT or thyristor is controlled to return from LCC mode to CLCC mode or the entire bridge arm is controlled to return from LCC mode to CLCC mode.

9. A valve-triggered fault protection device for a hybrid converter, characterized in that, It includes a processor and a memory, the processor being used to execute program instructions stored in the memory to implement the protection method for valve-triggered faults of a hybrid converter as described in any one of claims 4-8.

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