Duty cycle limiting circuit and dc switching power supply with constant output

Abstract

Embodiments of the present disclosure relate to a duty cycle limiting circuit comprising a DC switching power supply. The duty cycle limiting circuit comprises a timing module and a switch control module. The timing module is connected to the DC switching power supply to output a variable output voltage, and is configured to cause the variable output voltage to increase to a voltage threshold within a first level of time shorter than a certain period of a pulse signal, in response to a loop calculated duty cycle within the period being greater than a maximum limited duty cycle. The switch control module is configured to output a signal to enable a switch to be turned on before the variable output voltage increases to the voltage threshold, and to output a signal to enable the switch to be turned off independently of the pulse signal after the variable output voltage increases to the voltage threshold, within the period in which the loop calculated duty cycle is greater than the maximum limited duty cycle. The duty cycle limiting circuit according to the present disclosure can prevent the duty cycle of the switch from being too large during a transition period, to protect core components of the DC switching power supply.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a duty cycle limiting circuit for a DC switching power supply, and a DC switching power supply including the duty cycle limiting circuit. Background Technology

[0002] The background description provided herein is intended to generally present the context of this disclosure. The inventors’ work is neither expressly nor impliedly acknowledged as prior art to the subject matter of this disclosure, to the extent that it is described in this background section and in aspects that may not otherwise be described as prior art at the time of filing.

[0003] Pulse-width modulation (PWM) DC / DC power supplies are widely used in industrial and commercial applications. The duty cycle in a PWM-DC / DC power supply is related to the output voltage, input voltage, and transformer turns ratio. When the input voltage or output load changes, the duty cycle is adjusted to keep the output voltage constant. The feedback loop adjusts the duty cycle based on changes in the input voltage and load. A larger duty cycle is required for larger loads, and a correspondingly smaller duty cycle is required for smaller loads.

[0004] During the high-level period of the signal waveform emitted by the PWM modulator, the switches (e.g., MOSFETs) in the PWM-DC / DC power supply are turned on, thereby transferring energy to the load. During the low-level period of the signal waveform emitted by the PWM modulator, the switches (e.g., MOSFETs) in the PWM-DC / DC power supply are turned off, thereby preventing energy transfer to the load.

[0005] When the load switches from a light load (e.g., zero load) to a full load, the duty cycle needs to increase sharply for the feedback signal in the feedback loop, for example, from 1% to 60%, or from 10% to 60%. However, during the transition from a small to a large duty cycle, overshoot occurs, with the duty cycle reaching 85% or higher, before gradually decreasing to reach a stable operating duty cycle of 60%. The large duty cycle (85% or higher) during this transition will cause core components of the PWM-DC / DC power supply (such as the transformer) to saturate and will lead to significant sudden stress on the switches (e.g., voltage spikes). This sudden stress affects the reliability of switches (e.g., MOSFETs) in the PWM-DC / DC power supply and can even cause irreversible damage by breaking down the MOSFETs.

[0006] Some traditional PWM control chips have a maximum duty cycle limit function, such as limiting it to 85%. However, this value is fixed and cannot change according to variations in the input voltage. In dynamic situations, an excessively high duty cycle can still lead to transformer saturation and switch overstress. Summary of the Invention

[0007] According to a first aspect of this disclosure, a duty cycle limiting circuit for a DC switching power supply is provided. The DC switching power supply includes a switch and a pulse signal generation unit. The pulse signal generation unit is configured to generate a pulse signal having a duty cycle, which is the ratio of the time of a first level of the pulse signal to its period. The duty cycle, in response to an increase in load, transitions from a first current duty cycle to a second target duty cycle greater than the first current duty cycle over multiple periods. The duty cycle limiting circuit includes a timing module and a switch control module. The timing module is electrically connected to the input voltage of the DC switching power supply to output a variable output voltage. The timing module is configured to: in each period of the pulse signal, gradually increase the variable output voltage from the same initial value, and in response to a duty cycle greater than a maximum limited duty cycle within a certain period of the pulse signal, increase the variable output voltage to a voltage threshold within a time shorter than the first level within that period, wherein the maximum limited duty cycle is greater than the second target duty cycle, and the voltage threshold corresponds to the maximum limited duty cycle. The switch control module is electrically connected to the timing module, the pulse signal generation unit, and the switch, and is configured to: during the period when the duty cycle of the pulse signal is greater than the maximum limit duty cycle, before the variable output voltage increases to the voltage threshold, output a first control signal that enables the switch to turn on; and after the variable output voltage increases to the voltage threshold, output a second control signal that enables the switch to turn off independently of the pulse signal.

[0008] The variable output voltage is achieved through a timing module. By setting a reasonable voltage threshold and through the coordinated action of the timing module and the switch control module, the required maximum duty cycle can be achieved (this maximum duty cycle corresponds to the voltage threshold, for example, slightly larger than the second target duty cycle and much smaller than the maximum duty cycle during the transition period). This ensures that the maximum duration of the first level (e.g., high level) of the control signal received by the switch is shorter than the duration of the first level (e.g., high level) of the pulse signal with the maximum duty cycle reached during the transition period. Therefore, according to the duty cycle limiting circuit of this embodiment, the duty cycle of the switch control signal can be made less than the maximum limit duty cycle during the transition period, thereby protecting the switch and preventing transformer saturation.

[0009] In some embodiments, the switch control module includes: a first input terminal configured to receive a pulse signal from a pulse signal generation unit; a second input terminal configured to be connected to a timing module to receive a signal associated with a variable output voltage of the timing module, wherein, in response to the variable output voltage being less than a voltage threshold, the associated signal is a first signal enabling the switch control module to amplify the received pulse signal, and in response to the variable output voltage being greater than or equal to the voltage threshold, the associated signal is a second signal enabling the switch control module not to amplify the received pulse signal; and a control module output terminal configured to: in each cycle of the pulse signal, in response to the second input terminal receiving the first signal, output a third control signal enabling the switch to be turned on according to a first level of the pulse signal and turned off according to a second level of the pulse signal opposite to the first level, and in response to the second input terminal receiving the second signal, output a second control signal.

[0010] In this embodiment, the switch control module includes an enable pin (i.e., a second input terminal) that can amplify and stop amplification according to an enable signal and an disable signal, respectively, thereby controlling the switch. Furthermore, by associating the signal received by the enable pin with the magnitude of the variable output voltage, the duty cycle of the switch control signal output by the switch control module can be correlated with a voltage threshold, thereby controlling the duty cycle of the switch control signal below a maximum limited duty cycle. In one example, the switch is turned on when a sufficient positive voltage is applied to its gate; the first level can be high, and the second level can be low. In another example, the first level can be low, and the second level can be high. Since the switch is turned on when a sufficient positive voltage is applied to its gate, the duty cycle limiting circuit according to this example also includes an inverting circuit that causes the low first level to switch to high, and the high second level to switch to low.

[0011] In some embodiments, the switch control module may further include a comparison unit connected between the timing module and the second input terminal of the switch control module, and the comparison unit includes: a non-inverting input terminal configured to be connected to a reference voltage source, wherein the reference voltage source outputs a reference voltage V. ref The voltage value is related to the voltage threshold; the inverting input is configured to receive the variable output voltage of the timing module; and the comparator output is electrically connected to the second input of the switch control module, wherein the comparator is configured to: respond to the variable output voltage V received at the inverting input. A If the voltage exceeds the reference voltage, a second signal is output to the second input terminal through the output terminal of the comparator unit. This comparator unit enables the variable output voltage of the timing module to be correlated with the enable signal received by the enable pin of the switch control module.

[0012] In some embodiments, the timing module includes: a capacitor, the first plate of which is connected to the input voltage V of a DC switching power supply. in The capacitor's second plate is grounded; and a first switch is connected in parallel with the capacitor, wherein the first switch is configured to: turn on at the rising edge of each cycle of the pulse signal to discharge the capacitor, and is configured to turn off after the rising edge of each cycle of the pulse signal to utilize the input voltage V of the DC switching power supply. in The capacitor is charged so that the variable output voltage V of the timing module is increased. A The voltage gradually increases from the same initial value. This embodiment allows the capacitor to be controlled using a first switch, enabling the voltage to increase from the same initial value in each cycle during the transition period.

[0013] In some embodiments, the timing module further includes a first resistor connected in series between the first plate of the capacitor and the DC switching power supply, the variable output voltage being the voltage at the opposite end of the first resistor to the DC switching power supply, and the time required for the variable output voltage to increase to a voltage threshold being determined at least in part based on the resistance of the first resistor and the capacitance of the capacitor.

[0014] In some embodiments, the first switch includes a transistor connected in parallel with a capacitor and a transistor control circuit. The transistor is configured to turn on on the rising edge of a pulse signal and turn off after the rising edge. The transistor control circuit is configured to receive the pulse signal and output a control signal based on the pulse signal to control the transistor to turn on and off. By configuring the transistor and transistor control circuit, the capacitor can be discharged synchronously with the rising edge of the pulse signal and charged after the rising edge, thus achieving better synchronization between the charging and discharging of the capacitor and the pulse signal.

[0015] In some embodiments, the transistor includes: a gate electrically connected to a transistor control circuit; a source configured to be grounded; and a drain configured to be connected to a first plate of the capacitor. The transistor control circuit includes: another capacitor connected to the gate and configured to receive a pulse signal; and a second resistor, a first terminal of which is connected at a node between the other capacitor and the gate, and a second terminal of which is grounded. The other capacitor is configured to charge at the rising edge of each cycle of the pulse signal to turn the transistor on, and to be fully charged after the rising edge to turn the transistor off. By configuring this type of transistor control circuit, the transistor of the first switch can be controlled in a simple way to perform its function of turning on at the rising edge of the pulse signal and turning off after the rising edge.

[0016] In some embodiments, the input voltage V of the DC switching power supply inThis includes multiple input voltages within a range, wherein the multiple input voltages include at least: a first input voltage, and the variable output voltage V of the timing module. A The voltage rises to a voltage threshold at a first time corresponding to the first input voltage; and at the second input voltage, the variable output voltage V of the timing module. A The voltage rises to the voltage threshold at a second time corresponding to the second input voltage; wherein the first input voltage is less than the second input voltage, and the first time is longer than the second time. In this embodiment, the time required for the variable output voltage to rise to the voltage threshold varies depending on the input voltage, thus enabling the DC switch to be applicable to a wide range of input voltages while still achieving duty cycle limiting. In other words, the maximum limited duty cycle achievable by the control signal for the switch varies depending on the input voltage.

[0017] In some embodiments, the comparator unit further includes a clamping diode configured to clamp the highest voltage at the inverting input terminal to a specific voltage value. By providing the clamping diode, the voltage at the inverting input terminal of the comparator can be clamped to a specific value, preventing it from becoming too high, thereby protecting the comparator.

[0018] According to a second aspect of this disclosure, a DC switching power supply with constant output is provided, comprising: a duty cycle limiting circuit as claimed in claim 1; a switch connected between the input and output terminals of the DC switching power supply; and a pulse signal generating unit configured to generate pulse signals for controlling the switching on and off, wherein the duty cycle limiting circuit is electrically connected between the pulse signal generating unit and the switch. By limiting the duty cycle during duty cycle transitions through the duty cycle limiting circuit, preventing it from becoming excessive, core components of the DC switching power supply, such as the switch and transformer, can be protected.

[0019] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0021] Figure 1 A schematic diagram illustrating an example of an environment to which some embodiments of the present disclosure are applicable is shown;

[0022] Figure 2 A schematic diagram of a duty cycle limiting circuit according to an embodiment of the present disclosure is shown;

[0023] Figure 3A A schematic diagram showing test results during the duty cycle transition without a duty cycle limiting circuit is illustrated; and

[0024] Figure 3B A schematic diagram of test results during the duty cycle transition is shown using the duty cycle limiting circuit according to this disclosure. Detailed Implementation

[0025] Various embodiments will now be described with reference to the accompanying drawings, wherein similar reference numerals are used throughout to denote similar elements. In the following description, numerous specific details are set forth for purposes of explanation in order to facilitate a thorough understanding of one or more embodiments. However, it may be apparent in some or all cases that any of the embodiments described below can be practiced without employing the specific design details described below. In other instances, well-known structures and devices are illustrated in block diagram form to facilitate the description of one or more embodiments. A simplified overview of one or more embodiments is given below to provide a basic understanding of the embodiments. This overview is not an exhaustive summary of all contemplated embodiments, is not intended to identify key or essential elements of all embodiments, nor is it intended to define the scope of any or all embodiments.

[0026] References to “embodiment” or “one embodiment” within the framework of this description are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear at one or more points in this description do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular constructions, structures, or features may be combined in any suitable manner.

[0027] Unless otherwise indicated, when referring to two elements connected together, it means a direct connection without any intermediate element other than a conductor; and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0028] In the following disclosure, unless otherwise indicated, references to absolute positional modifiers (such as the terms "front," "back," "top," "bottom," "left," "right," etc.) or relative positional modifiers (such as the terms "above," "below," "higher," "lower," etc.), or references to orientational modifiers (such as "horizontal," "vertical," etc.), refer to the orientation shown in the figure. Unless otherwise specified, the expressions "about," "approximately," "basically," and "approximately" indicate within 10%, preferably within 5%.

[0029] Throughout the accompanying drawings, the same parts or elements are indicated by the same reference numerals, and corresponding descriptions will not be repeated for the sake of brevity. The reference numerals used herein are provided solely for convenience and therefore do not define the extent of protection or the scope of the embodiments.

[0030] As mentioned above, some traditional PWM control chips have a maximum duty cycle limit function, such as limiting it to 85%. However, this value is fixed and cannot change according to variations in the input voltage. In dynamic situations, an excessively high duty cycle can still lead to transformer saturation and switch overstress. This overstress affects the switches (such as MOSFETs) in the PWM-DC / DC power supply, and may even cause irreversible damage by breaking down the MOSFETs.

[0031] The PWM-DC / DC power supply according to this disclosure is equipped with a duty cycle limiting circuit that is capable of limiting the duty cycle to only slightly larger than the target duty cycle, for example, by only 3% to 8% above the target duty cycle, based on the input voltage of the power supply and the signal fed back by the modulation module, during the transition from a small duty cycle required for a light load to a large duty cycle required for a heavy load.

[0032] Figure 1 A schematic diagram illustrating an example of an environment to which some embodiments of this disclosure are applicable is shown.

[0033] like Figure 1 As shown, the PWM-DC / DC power supply 1000 includes a power processing circuit 200, an error amplifier / compensator 300, and a PWM modulator 400 (which can also be referred to as a pulse signal generation unit). The error amplifier / compensator 300 forms a feedback circuit that detects the load condition and feeds this back to the PWM modulator 400, which generates a pulse signal with an appropriate duty cycle based on the load condition.

[0034] like Figure 1 As shown, the power processing circuit 200 includes a switch 201 and a transformer (not shown). The topology of the power processing circuit 200 is not limited to forward, half-bridge, full-bridge, push-pull, etc. The switch 201 responds to the input voltage V. in The process is performed, and then the required voltage V is output to the load 500. out Within each cycle of the pulse signal, the ratio of the on-time to the off-time of switch 201 corresponds to the duty cycle of the pulse signal PWM generated by modulator 400. For example, during the high-level period of the pulse signal, the switch is on, causing the input voltage V to... in It supplies energy to the load, and during the low voltage period of the pulse signal, the switch opens, thus providing the input voltage V. in Stop supplying power to the load.

[0035] In one embodiment, switch 201 can be a MOSFET. The voltage that a MOSFET can withstand between its drain and source is limited. If the voltage is too high, it will break down the metal oxide, resulting in irreversible damage.

[0036] The modulator 400 generates a pulse signal with a relatively high frequency, typically between tens of kHz and hundreds of kHz; in one example, it is around 125 kHz, and one period of the pulse signal is 8 μs. In one embodiment, the input voltage V... in For example, the voltage can be maintained at 35V, while the output voltage remains at 12V and the output current remains at 25A. Alternatively, the input voltage V... in For example, it can maintain a voltage of 75V, while the output voltage remains at 12V and the output current at 25A. Since the output voltage or load is constant, then at the input voltage V... in When the voltage is small, the duty cycle of the pulse signal needs to be large, and the input voltage V... in When the voltage is large, the duty cycle of the pulse signal needs to be small. The input voltage according to this disclosure can be any voltage within a certain range, not limited to the 35V and 75V mentioned above.

[0037] As described above, when the load changes from light to heavy, for example, from zero load to full load, the desired duty cycle of the pulse signal is, for example, changing from 1% to 59%. However, when the duty cycle of the pulse signal is unrestricted, due to the influence of feedback components in the circuit, the duty cycle of the pulse signal may overshoot during the transition from a small to a large duty cycle, for example, suddenly increasing from 1% to 75% or even higher. Thus, during some cycles of the transition period, the duty cycle of the pulse signal (e.g., 75%) is greater than the maximum restricted duty cycle (e.g., 65%), which in one example is greater than the second target duty cycle (e.g., 59%). During some cycles of the transition period, the duty cycle of the pulse signal may also be less than the maximum restricted duty cycle. After several cycles, the duty cycle of the pulse signal stabilizes to the target duty cycle in a damped oscillating manner.

[0038] The DC switching power supply according to this application also includes a duty cycle limiting circuit 100, which is capable of limiting the duty cycle to only slightly larger than the desired target duty cycle, such as 3% to 8% larger than the target duty cycle, during the transition from light to heavy load.

[0039] The following will refer to Figure 2 This describes a duty cycle limiting circuit according to an embodiment of the present disclosure.

[0040] like Figure 2 As shown, the duty cycle limiting circuit 100 includes a timing module 1, which is connected to the input voltage V of the DC switching power supply. inAnd it outputs a variable output voltage V A During the transition of the pulse signal's duty cycle from a first current duty cycle (e.g., 1% for zero load at a 35V input voltage) to a second target duty cycle greater than the first current duty cycle (e.g., 59% for full load at a 35V input voltage), the variable output voltage gradually increases from the same initial value in each cycle of the pulse signal, which may be close to 0V.

[0041] When the duty cycle of the pulse signal is greater than the maximum duty cycle limit during a certain period (which typically occurs during the transition period), the timing module 1 is also configured to: for a period of high level shorter than that period, cause the variable output voltage V to... A Increase to a voltage threshold V _threshold The maximum duty cycle is greater than the second target duty cycle, and the voltage threshold corresponds to the maximum duty cycle.

[0042] In one example, for a pulse signal with a target duty cycle of 59%, during the transition period, for a pulse signal with a duty cycle of, for example, 75%, at the time corresponding to 65% of that period, the variable output voltage V... A Increase to voltage threshold V _threshold Furthermore, within the period of the pulse signal with a duty cycle of, for example, 50%, the variable output voltage V is also adjusted at the 65th percentile of that period. A Increase to voltage threshold V _threshold Because timing module 1 is connected to the input voltage, the variable output voltage can increase continuously from an initial value close to 0V.

[0043] like Figure 2 As shown, the duty cycle limiting circuit 100 also includes a switch control module 2, which includes a first input terminal 21, a second input terminal 22, and an output terminal 23. In one example, the driver of the switch control module 2 amplifies the received pulse signal when it receives an enable signal to generate a drive signal capable of driving a switch (e.g., a MOSFET switch). The first input terminal 21 is configured to receive the pulse signal generated by the PWM modulator 400. The first input terminal 21 may, for example, be an input pin of the switch driver.

[0044] The second input terminal 22 (i.e., the enable pin of the driver) of the switch control module 2 is configured to receive the variable output voltage V associated with the timing module 1. AThe signal. In one example, the second input terminal 22 is, for example, the enable pin of the switch driver. When the second input terminal 22 receives a high level, the pulse signal input to the first input terminal 21 can be amplified by the internal structure of the driver to generate a suitable drive signal for driving the gate of the switch 201, and output to the switch 201 through the output terminal 23. When the second input terminal 22 receives a low level, the driver no longer operates, that is, the pulse signal is not amplified, and the pulse signal received by the first input terminal 21 cannot be transmitted to the output terminal 23. If the variable output voltage V A Less than a voltage threshold V _threshold Then, it is related to the variable output voltage V of timing module 1. A The associated signal is a high-level signal (i.e., the second input terminal 22 receives a high-level signal), thereby enabling the driver to control the switch 201 to turn on according to a high level of the pulse signal and turn off according to a low level of the pulse signal. If the variable output voltage V A Increase to a voltage threshold V _threshold Then, it is related to the variable output voltage V of timing module 1. A The associated signal is a low-level signal (i.e., the second input terminal 22 receives a low-level signal), which prevents the driver from working, and thus the switch 201 also does not receive the drive signal and is turned off.

[0045] The output terminal 23 of the switch control module 2 is configured to: when the second input terminal 22 receives a high-level signal, output signals to control the switch 201 to turn on and off respectively based on the high-level and low-level signals of the pulse signal received by the first input terminal 21; and when the second input terminal 22 receives a low-level signal, output a control signal that forces the switch 201 to turn off.

[0046] In the duty cycle limiting circuit according to this disclosure, the variable output voltage V of timing module 1... A Increase to threshold voltage V _threshold Previously, the second input terminal 22 received the first signal (i.e., the driver's enable signal), enabling the driver of the switch control module to operate. Consequently, the output terminal 23 of the switch control module outputs signals that turn the switch on and off based on the high or low level of the pulse signal; that is, a high pulse signal turns the switch on, and a low pulse signal turns the switch off. The variable output voltage V of the timing module 1... A Increase to threshold voltage V _threshold Subsequently, the second input terminal 22 receives the second signal (i.e., the driver's disable signal), the driver stops working, and thus the output terminal 23 does not output a drive signal, thereby opening the switch 201.

[0047] During a period when the duty cycle of the pulse signal (e.g., 59%) is less than the maximum duty cycle limit (e.g., 65%), before the time corresponding to 65% of that period, the variable output voltage has not yet increased to the threshold voltage, and the second input terminal 22 receives the first signal (i.e., the enable signal). During the time corresponding to the time after 65% of that period, the variable output voltage increases above the threshold voltage, and therefore the second input terminal 22 receives the second signal (i.e., the disable signal). Therefore, during a period less than 59% of the period when the pulse signal's duty cycle is, for example, 59%, the pulse signal is at a high level, the second input terminal 22 receives the enable signal, and thus switch 201 is turned on. During the time from 59% to 65% of that period, the second input terminal 22 still receives the enable signal, but at this time the pulse signal is at a low level, and therefore switch 201 is turned off according to the low drive signal. During 65% of the cycle and beyond, the second input terminal 22 receives a disable signal, which also causes switch 201 to open. Since switch 201 is already open at this point, receiving a disable signal will not affect the open state of switch 201. In other words, during cycles with a duty cycle less than the maximum limit duty cycle, the duty cycle limiting circuit will not affect the switch control module 2's control of switch 201 based on pulse signals.

[0048] During a period in which the duty cycle of the pulse signal (e.g., 75%) is greater than the maximum duty cycle limit (e.g., 65%), before the time corresponding to 65% of that period, the variable output voltage has not yet increased to the threshold voltage, and the second input terminal 22 receives the first signal (i.e., the enable signal). During the time corresponding to 65% and thereafter of that period, the variable output voltage increases above the threshold voltage, and therefore the second input terminal 22 receives the second signal (i.e., the disable signal). During less than 65% of the period in which the duty cycle of the pulse signal is, for example, 75%, the second input terminal 22 receives the enable signal, the pulse signal is at a high level, and therefore the switch 201 is turned on; during the time from 65% to 75% of that period, the pulse signal is still at a high level, but the second input terminal 22 receives the disable signal, the driver no longer works and therefore cannot output a high drive signal, so the switch 201 is turned off, even though the pulse signal is still at a high level. During 75% to 100% of this cycle (i.e., when the pulse signal is at a low level), because the variable output voltage continues to increase and reaches a level greater than the threshold voltage, the second input terminal 22 continues to receive an inhibit signal, and therefore the switch 201 remains open. Thus, during cycles with a duty cycle greater than the maximum limit duty cycle, the duty cycle limiting circuit of this disclosure can limit the maximum duty cycle of the switch control signal to the maximum limit duty cycle without exceeding it, thereby preventing overstress on the switch and saturation of the transformer.

[0049] At the beginning of the next cycle of the pulse signal, since the variable output voltage returns to its initial value (close to 0V), the second input terminal 22 starts receiving the enable signal again from the beginning of the next cycle.

[0050] During the transition period (e.g., over several cycles), the duty cycle of the pulse signal can reach, for example, 77%, or even more, occupying the majority of each cycle. In the duty cycle limiting circuit 100 according to this disclosure, the timing module 1 is connected to the input voltage V of the DC switching power supply. in This allows the voltage to gradually increase from the same initial value (e.g., 0V) in each cycle during the transition period. By setting a reasonable voltage threshold, the variable output voltage of timing module 1 can reach the voltage threshold within a period with a large duty cycle, for a period shorter than the high-level duration of the pulse signal within that period. Switch control module 2 can generate a corresponding control signal by receiving a signal associated with the gradually increasing output voltage. For example, when the voltage of timing module 1 reaches the voltage threshold, the second input terminal 22 (e.g., the enable pin) of switch control module 2 begins to receive a low level, thereby disabling its driver. As a result, the gate of switch 201 does not receive a high-level signal, and switch 201 cannot be turned on. The transformer in power processing circuit 200 is thus de-energized and does not enter a saturation state.

[0051] During a period with a large duty cycle, after the voltage of timing module 1 reaches the voltage threshold, the first input terminal 21 still receives a high-level pulse signal. However, the low-level signal received by the enable pin of the driver of switch control module 2 has already caused the driver of switch control module 2 to stop working. Therefore, switch 201 cannot be turned on according to the high level of the pulse signal. Thus, the core components in the DC switching power supply will not be in a saturated state and will not generate significant stress. Therefore, by using the duty cycle limiting circuit according to this disclosure, the core components in the power processing circuit of the DC switching power supply, such as MOSFET-type switches and transformers in the circuit, can be protected.

[0052] In one example of the DC switching power supply according to this disclosure, the transition period may include multiple cycles. After the transition period, as the output voltage returns to the target value, the duty cycle of the pulse signal changes to the desired duty cycle, such as 59% for a 35V input voltage as described above. During the steady-state period following the transition period, the switch control module 2 is able to generate a control signal to control the switching on and off of the switch 201 based on the received pulse signal having a second target duty cycle (e.g., 59%), for example, the switch 201 is turned on when the pulse signal is high and turned off when the pulse signal is low.

[0053] like Figure 2As shown, the switch control module 2 includes a comparison unit 24. This comparison unit 24 is connected between the timing module 1 and the second input terminal 22 of the switch control module 2. By configuring this comparison unit, the signal received by the second input terminal 22 (e.g., the enable pin) of the switch control module 2 can be correlated with the voltage of the timing module 1.

[0054] like Figure 2 As shown, the comparison unit 24 includes a non-inverting input terminal 241, which is configured to receive a reference voltage V. ref The reference voltage is equal to the aforementioned voltage threshold; the inverting input 242 is configured to receive the variable output voltage V from the timing module 1. A ; and output terminal 243, electrically connected to the second input terminal 22 of the switch control module 2. The comparison unit 24 is configured to respond to the variable output voltage V of the timing module 1. A Exceeding the reference voltage V ref The output terminal 243 outputs a low level, thereby outputting a low-voltage signal to the second input terminal 22. In other words, a low-voltage signal is input to the enable pin of the switch control module 2 to disable the driver of the switch control module 2, preventing the output terminal 23 from outputting a high level to switch 201 to turn it on, thus causing switch 201 to open. Therefore, the comparison unit 24 can correlate the variable output voltage V of the timing module 1. A The enable pin of the driver of the switch control module 2 is connected to the variable output voltage V. A When the voltage threshold is exceeded, the driver of switch control module 2 cannot work, so switch 201 cannot be turned on.

[0055] like Figure 2 As shown, the timing module 1 according to this disclosure includes a capacitor C1 and a first switch 12. The first plate 111 of the capacitor C1 is connected to the input voltage V. in The second plate 112 of capacitor C1 is grounded. Figure 2 As shown, the first plate 111 of the capacitor C1 is connected to the input voltage V, for example, through resistor R3. in Thus, from the input voltage V in The current flows through resistor R3 and charges capacitor C1. In a preferred example, such as... Figure 2 As shown, timing module 1 also includes resistors R1 and R2, and the input voltage of timing module 1 is the voltage at node A between resistors R3 and R1. By appropriately setting the resistance values ​​of resistors R3, R1, and R2, as well as the capacitance of capacitor C1, a variable output voltage V can be obtained. AA reasonable threshold is established so that the time to rise to the voltage threshold is shorter than the high-level duration of the duty cycle within each cycle during the transition period. In a preferred example, the resistance of resistor R1 is much smaller than that of resistors R3 and R2, and the resistance of resistor R2 is much larger than that of resistor R3. Therefore, the voltage at node A is equivalent to the voltage on the first plate 111 of capacitor C1. Due to the charging effect of capacitor C1, the voltage on the first plate 111 of capacitor C1 gradually increases, thereby gradually increasing the voltage at node A, which can then increase to the aforementioned voltage threshold.

[0056] like Figure 2 As shown, the first switch 12 is connected in parallel with capacitor C1. The first switch 12 is configured to turn on at the rising edge of each cycle of the pulse signal, so that the charge on capacitor C1 is discharged through the conducting first switch 12, causing capacitor C1 to discharge and reducing the voltage on the first plate of the capacitor to an initial value close to 0V. This allows capacitor C1 to gradually increase from the same initial value during each cycle of the pulse signal transition. The second switch 12 is further configured to turn off after the rising edge of each cycle of the pulse signal, so that capacitor C1 is no longer short-circuited with switch 12, and the input voltage V of the DC switching power supply can be utilized. in The capacitor C1 is charged so that the voltage on the first plate 111 of the capacitor C1 gradually increases, thereby increasing the output voltage V of the timing module 1. A It also gradually increased.

[0057] In V A Increase to the voltage threshold V _threshold At that time, the voltage threshold V _threshold It can be set to be equal to the reference voltage V of comparator unit 24. ref The comparison unit 23 outputs a low-voltage signal, which is then input to the second input terminal 22 (i.e., the enable pin) of the switch control module 2, thereby causing the driver of the switch control module 2 to stop working.

[0058] like Figure 2 As shown, the comparison unit 24 also includes a reference power supply 25, the voltage of which is, for example, 5V. The comparison unit 24 also includes resistors R5 and R6. Through the circuit of resistors R5 and R6 and the reference power supply 25, a reasonable reference voltage V can be obtained. ref The non-inverting input 241 of the comparator unit 24 is connected at node B between resistors R5 and R6, so that the voltage at node B is used as the reference voltage V. ref In one example, the reference voltage V ref It is approximately 1.853V. Therefore, the aforementioned voltage threshold V _thresholdThe voltage can be 1.853V. Although the reference voltage is achieved here using reference power supply 25 and the voltage divider of resistors R5 and R6, those skilled in the art will realize that other alternative methods can be used to achieve the reference voltage, such as using a voltage regulator chip, and all these alternative methods fall within the protection scope of this application.

[0059] like Figure 2 As shown, in one example, the first switch 12 includes an NMOS transistor 13 and a transistor control circuit 14. The transistor control circuit 14 controls the gate of the NMOS transistor 13 such that at the rising edge of each cycle of the pulse signal, the voltage difference between the gate and source of the NMOS is greater than the turn-on voltage threshold, thereby turning on the NMOS transistor to form a short circuit with the capacitor C1 and discharge the capacitor, causing the voltage on its first plate 111 to drop to 0V.

[0060] like Figure 2 As shown, the NMOS transistor 13 includes: a gate configured to receive a high-voltage signal at the rising edge of a pulse signal and return to a low-voltage signal after the rising edge; a source configured to be grounded; and a drain configured to be connected to a first plate 111 of a capacitor C1. The first switch 12 may include a transistor control circuit 14 to control the voltage input to the gate. By configuring the transistor control circuit 14, the gate can receive a high level at the rising edge of the pulse signal and return to a low level after the rising edge of the pulse signal. Figure 2 As shown, the transistor control circuit 14 includes another capacitor C2 and a resistor R4. The capacitor C2 is connected to the gate of the NMOS transistor 13 and is configured to receive pulse signals. The first end of the resistor R4 is connected at node C between the capacitor C2 and the gate of the NMOS transistor 13, and the second end of the resistor R4 is grounded.

[0061] At the rising edge of each pulse signal cycle, through the path formed with resistor R4, due to the characteristics of the capacitor, the voltage jump at the rising edge causes capacitor C2 to conduct, thereby charging capacitor C2. In one example, capacitor C2 takes 200ns to fully charge, meaning that capacitor C2 conducts for 200ns. During this time period, the voltage on the gate of NMOS transistor 13 is equivalent to the voltage at the first terminal of resistor R4. Therefore, the voltage difference between the gate and source of NMOS transistor 13 is greater than the turn-on voltage threshold, causing NMOS transistor 13 to conduct and short-circuit capacitor C1, thus discharging capacitor C1. After the rising edge of the pulse signal, for example, after 200ns, capacitor C2 is fully charged, and its voltage is equivalent to the high level of the pulse signal. Capacitor C2 no longer conducts, causing the voltage at the first terminal of resistor R4 to decrease, for example, to ground. This causes the voltage difference between the gate and source of NMOS transistor 13 to approach 0, thus falling below the turn-on voltage threshold, and NMOS transistor 13 turns off. When NMOS transistor 13 is off, the input voltage V... in Capacitor C1 is charged through resistors R3 and R1. The aforementioned 200ns is merely a fleeting moment in the 8μs cycle; for most of the cycle, capacitor C1 can be charged, causing its voltage to gradually increase.

[0062] Although the above embodiments describe the implementation of an NMOS transistor that turns on on the rising edge and turns off after the rising edge using an NMOS transistor and a gate control circuit including a capacitor and a resistor, those skilled in the art will conceive of other alternative implementations, such as using a PMOS transistor or a bipolar transistor, as long as the circuit enables the capacitor to be discharged on the rising edge and charged after the rising edge, it falls within the scope of protection of this application.

[0063] In one example, by properly designing the resistance values ​​of resistors R3, R1, and R2, the capacitance of capacitor C1, and the voltage threshold, it is possible to ensure that V during the transition period... A The time it takes for the voltage at the point to reach the threshold voltage is less than the duration of the high level of the pulse signal.

[0064] In one example, for the aforementioned DC switching power supply with an input voltage of 35V and the aforementioned DC switching power supply with an input voltage of 75V, the resistance of R3 is approximately 100k ohms, the resistance of R1 is approximately 402 ohms, the resistance of R2 is approximately 825k ohms, and the capacitance of capacitor C1 is approximately 1000pF. By designing these capacitance and resistance values, the following reference can be achieved. Figure 3BThe effect is shown. Although only 35V and 75V input voltages are listed in the examples of this disclosure, the input voltage of this disclosure can vary within a range, including multiple input voltages. For different input voltages, the time it takes for the variable output voltage of timing module 1 to reach the voltage threshold is different.

[0065] For an input voltage of 35V, the second target duty cycle is 59%. Using the duty cycle limiting circuit of this disclosure, the maximum duty cycle of the switch control signal during the transition period can be limited to approximately 65%. For an input voltage of 75V, the second target duty cycle is 25%. Using the duty cycle limiting circuit of this disclosure, the maximum duty cycle of the switch control signal during the transition period can be limited to approximately 29%. The higher the input voltage, the shorter the time it takes for the capacitor of timing module 1 to charge to the threshold voltage; therefore, compared to a smaller input voltage, the maximum achievable limited duty cycle is also smaller. Therefore, different maximum limited duty cycles can be achieved during the transition period for different input voltages.

[0066] Figure 3A A schematic diagram of the test results during the duty cycle transition is shown without a duty cycle limiting circuit. Figure 3B A schematic diagram of test results during the duty cycle transition is shown using the duty cycle limiting circuit according to this disclosure.

[0067] Figure 3A and Figure 3B The test results shown are for a DC switching power supply with a pulse signal frequency of 125kHz (i.e., each pulse signal cycle is 8μs), an input voltage of 35V, and an output current of 25A. The high-level pulse signal duration required for this DC switching power supply at full load is approximately 4.72μs, meaning the required duty cycle is 4.72 / 8 = 59%.

[0068] like Figure 3A The test results shown are without using a duty cycle limiting circuit. Curve 301A represents the pulse signal received at the gate of switch 201, curve 302A represents the current flowing through the primary coil of the transformer, and curve 303A represents the voltage difference V between the drain and source of switch 201. ds .

[0069] like Figure 3A As shown, during the transition period, Δt on curve 301A A The high-level pulse signal duration in each cycle can reach 6.17 μs, meaning the duty cycle reaches 6.17 / 8 = 77.1%. Referring to curve 303A, the V0 of the MOSFET switch can be seen... ds_maxAIt can even reach 167V. This voltage is too high. If the MOSFET is subjected to this high voltage repeatedly, it may break down and be damaged.

[0070] like Figure 3B The test results shown are from a duty cycle limiting circuit. Curve 301B represents the pulse signal received at the gate of switch 201, curve 302B represents the current flowing through the primary coil of the transformer, and curve 303B represents the voltage difference V between the drain and source of switch 201. ds .

[0071] like Figure 3B As shown, during the transition period, Δt on curve 301B B The indicated high-level pulse signal duration in each cycle is approximately 5.12 μs, meaning a duty cycle of 64%, only 5% higher than the required 59%, and significantly smaller than the 77.1% duty cycle without a duty cycle limiting circuit. Referring to curve 303B, the V0 of the MOSFET switch can be seen... ds_maxB The voltage is 150V, which is lower than the 167V without the duty cycle limiting circuit, so the MOSFET switch will not be subjected to excessive voltage.

[0072] In one example, such as Figure 2 The comparator unit 24 further includes a diode D1. The cathode of diode D1 is connected to the reference power supply 25, and the anode of diode D1 is connected to node A and the inverting input terminal 242 of comparator unit 24. The function of this diode will be described in detail below. When operating normally according to a pulse signal, capacitor C1 is recharged by discharging on the rising edge of the pulse signal, so capacitor C1 is not continuously charged, and the voltage does not become excessively high. However, after the pulse signal disappears, the capacitor is not discharged and remains in a charging state, causing the voltage to increase to a higher level. When the voltage is too high, the output voltage V... A The voltage could become too high, causing the inverting input 242 of comparator 24 to receive an excessively high voltage, potentially damaging comparator 24. In one example, the forward voltage of diode D1 is 0.7V, which clamps the voltage at the inverting input of comparator 24 to 5.7V, preventing it from increasing further and thus protecting the circuit. While this embodiment describes the use of a diode to limit the voltage at the inverting input 242 of comparator 24, other alternative embodiments will be apparent to those skilled in the art, and all such alternative embodiments capable of clamping the voltage at the inverting input of the comparator fall within the scope of this invention.

[0073] like Figure 2As shown, the non-inverting input terminal 241 of the comparator unit 24 is also grounded through capacitor C3, thereby filtering out interference signals through capacitor C3, so that the voltage of the non-inverting input terminal 241 of the comparator unit 24 remains constant.

[0074] Comparator 24 flips when the voltage at the inverting input 242 is greater than the reference voltage, outputting a low level. If the voltage at the inverting input 242 decreases slightly due to fluctuations and becomes less than the reference voltage, comparator 24 will flip again and output a high level. To prevent this from happening, as follows: Figure 2 As shown, the non-inverting input terminal 241 of the comparator unit 24 is also connected to the output terminal 243 of the comparator unit 24 through a resistor R7, thereby performing hysteresis control on the comparator unit 24. Through the resistor R7, when the comparator unit 24 outputs a low level, the voltage of the non-inverting input terminal 241 is pulled low, so that even if the voltage of the inverting input terminal 242 decreases slightly, the comparator unit 24 will still output a low level and will not flip.

[0075] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of protection. The various embodiments described above may be combined to provide other embodiments. If it is necessary to employ concepts from various patents, applications, and publications to provide further embodiments, aspects of the embodiments may be modified.

[0076] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are given. Therefore, the claims are not limited by the disclosure.

Claims

1. A duty cycle limiting circuit (100) for a DC switching power supply, the DC switching power supply including a switch (201) and a pulse signal generation unit (400), the pulse signal generation unit (400) being configured to generate a pulse signal having a duty cycle, the duty cycle being the ratio of the time to the period of a first level of the pulse signal, the duty cycle being responsive to load increase and capable of transitioning from a first current duty cycle to a second target duty cycle greater than the first current duty cycle over multiple periods, the duty cycle limiting circuit (100) comprising: The timing module (1) is electrically connected to the input voltage (V) of the DC switching power supply. in ) to output a variable output voltage (V A The timing module (1) is configured to, in each cycle of the pulse signal generated by the pulse signal generation unit (400), cause the variable output voltage (V) to... A The variable output voltage (V) gradually increases from the same initial value, and the duty cycle in response to a certain period of the pulse signal is greater than the maximum limited duty cycle, causing the variable output voltage (V) to increase within a time period shorter than the first level within that period. A The voltage is increased to a voltage threshold, wherein the maximum limited duty cycle is greater than the second target duty cycle, and the voltage threshold corresponds to the maximum limited duty cycle; as well as The switch control module (2), electrically connected to the timing module (1), the pulse signal generation unit (400), and the switch (201), is configured to: during the period when the duty cycle of the pulse signal is greater than the maximum limit duty cycle, the variable output voltage (V) A Before the voltage increases to the threshold voltage, a first control signal is output that enables the switch (201) to turn on, at which point the variable output voltage (V) is increased. A After the voltage is increased to the voltage threshold, a second control signal is output that enables the switch (201) to open independently of the pulse signal, wherein the timing module (1) includes: Capacitor (C1), the first plate (111) of which is connected to the input voltage (V) of the DC switching power supply. in ), and the second plate (112) of the capacitor is grounded; and The first switch (12) is connected in parallel with the capacitor (C1). The first switch (12) is configured to turn on at the rising edge of each cycle of the pulse signal to discharge the capacitor (C1), and is configured to turn off after the rising edge of each cycle of the pulse signal to utilize the input voltage (V) of the DC switching power supply. in The capacitor (C1) is charged so that the variable output voltage (V) of the timing module (1) is increased. A The value gradually increases from the initial value. The timing module (1) further includes a first resistor (R3) connected in series between the first plate (111) of the capacitor (C1) and the DC switching power supply, and the variable output voltage (V A ) is the voltage at the end of the first resistor (R3) opposite to the DC switching power supply.

2. The duty cycle limiting circuit according to claim 1, wherein the switch control module (2) comprises: The first input terminal (21) is configured to receive the pulse signal from the pulse signal generation unit (400); The second input terminal (22) is configured to be connected to the timing module (1) to receive the variable output voltage (V) of the timing module (1). A The associated signal, wherein the variable output voltage (V) is responsive to the variable output voltage (V) A If the voltage is less than the voltage threshold, the associated signal is a first signal that enables the switch control module (2) to amplify the received pulse signal, and is responsive to the variable output voltage (V). A If the voltage is greater than or equal to the voltage threshold, the associated signal is a second signal that causes the switch control module (2) not to amplify the received pulse signal; as well as The control module output terminal (23) is configured to: in each cycle of the pulse signal, in response to the second input terminal (22) receiving the first signal, output a third control signal that enables the switch to be turned on according to the first level of the pulse signal and turned off according to the second level of the pulse signal opposite to the first level, and in response to the second input terminal (22) receiving the second signal, output the second control signal.

3. The duty cycle limiting circuit (100) according to claim 2, wherein the switch control module (2) further includes a comparison unit (24), the comparison unit (24) being connected between the timing module (1) and the second input terminal (22) of the switch control module (2) and comprising: The non-inverting input (241) is configured to be connected to a reference voltage source, the reference voltage source outputting a reference voltage (V ref The voltage value is related to the voltage threshold. The inverting input terminal (242) is configured to receive the variable output voltage of the timing module (1); and The output terminal (243) of the comparison unit is electrically connected to the second input terminal (22) of the switch control module (2). The comparator unit (24) is configured to respond to the variable output voltage (V) received at the inverting input (242). A If the voltage exceeds the reference voltage, the second signal is output to the second input terminal (22) through the output terminal (243) of the comparison unit.

4. The duty cycle limiting circuit (100) according to claim 1, wherein the variable output voltage (V) A The time required to increase to the voltage threshold is determined at least in part based on the resistance of the first resistor (R3) and the capacitance of the capacitor (C1).

5. The duty cycle limiting circuit (100) according to claim 1, wherein the first switch (12) includes a transistor (13) connected in parallel with the capacitor (C1) and a transistor control circuit (14). The transistor (13) is configured to: turn on at the rising edge of the pulse signal and turn off after the rising edge; and The transistor control circuit (14) is configured to receive the pulse signal and output a control signal based on the pulse signal to control the transistor (13) to turn on and off.

6. The duty cycle limiting circuit (100) according to claim 5, wherein, The transistor (13) includes: The gate is electrically connected to the transistor control circuit (14). The source is configured to be grounded; and The drain is configured to be connected to the first plate (111) of the capacitor (C1), and The transistor control circuit (14) includes: Another capacitor (C2), connected to the gate and configured to receive the pulse signal; and The second resistor (R4) has its first end connected to the node between the other capacitor (C2) and the gate, and its second end grounded. The other capacitor (C2) is configured to be charged at the rising edge of each cycle of the pulse signal to turn on the transistor (13), and fully charged after the rising edge to turn off the transistor (13).

7. The duty cycle limiting circuit (100) according to claim 1, wherein the input voltage (V) of the DC switching power supply in This includes a plurality of input voltages within a range, wherein the plurality of input voltages includes at least: The first input voltage, the variable output voltage (V) of the timing module (1) A The voltage rises to the voltage threshold at a first time corresponding to the first input voltage; as well as The second input voltage, the variable output voltage (V) of the timing module (1) A The voltage rises to the voltage threshold at a second time corresponding to the second input voltage; The first input voltage is less than the second input voltage, and the first time is longer than the second time.

8. The duty cycle limiting circuit (100) according to claim 3, wherein the comparison unit (24) further includes a clamping diode (D1) configured to clamp the highest voltage of the inverting input (242) at a specific voltage value.

9. A DC switching power supply with constant output, comprising: Duty cycle limiting circuit (100) according to claim 1; A switch (201) is connected between the input and output terminals of a DC switching power supply; as well as The pulse signal generation unit (400) is configured to generate pulse signals for controlling the on and off of the switch (201). The duty cycle limiting circuit (100) is electrically connected between the pulse signal generation unit (400) and the switch (201).

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