A 40-octave ultra-wideband high power amplifier internal matching circuit

Abstract

The application provides a 40-fold frequency range ultra-wideband high-power inner matching circuit, which comprises an input matching circuit, an output matching circuit, a gate bias circuit and a drain bias circuit.The input matching circuit and the output matching circuit of the application are both reactive matching networks, which are composed of multiple-stage gradually-changing microstrip lines loaded with decoupling and matching capacitors, and the working bandwidth is expanded by increasing the gradually-changing stage number of the microstrip line structure of the matching circuit, so that the limitation of relatively narrow wideband of the reactive matching is solved.The application is adapted to a 7.2mm-10mm large-gate-width GaN die, and the recommended die size is 5*0.8mm, so as to meet the high heat dissipation requirement of a high-power amplifier.The application loads a large-line-width on-chip spiral inductor made of quartz material in the gate bias circuit, so as to realize wideband inductance while meeting the requirements of high power and large current.The application uses a ceramic substrate processing technology, uses a high dielectric constant die plate to realize miniaturization, has a simple circuit structure, adopts gold wire bonding, is convenient to realize, and is easy to produce at low cost.

Description

Technical fields: This invention relates to the field of matching circuit technology for broadband amplifiers, and in particular to a matching circuit for a high-power broadband amplifier. Background technology: In order to enable wireless systems of different frequency bands and modes to communicate with each other and be integrated into the same wireless equipment, integrated and miniaturized communication front-end equipment has been developed. Among them, the power amplifier, as a key component of wireless communication system, has been extensively studied for its ultra-wideband characteristics.

[0001] Ultra-wideband power amplifiers are widely used in mobile communications, GPS navigation, satellite communications, broadband radar, and electromagnetic compatibility. High power performance is particularly important to provide better detection range and communication coverage.

[0002] GaN HEMTs, as third-generation semiconductor devices, have numerous advantages such as wide bandgap, high cutoff frequency, high electron mobility and electron saturation drift velocity, and high breakdown field strength. Furthermore, the SiC substrate provides excellent heat dissipation performance, making them ideal for the fabrication of ultra-wideband high-power amplifiers.

[0003] In designing matching circuits for ultra-wideband power amplifiers, it is necessary to address the transistor gain roll-off issue across the wide bandwidth. Simultaneously, it is crucial to consider the large variations in input and output impedance over the wide bandwidth, the significant difference between the die output impedance and the standard impedance, and the poor low-frequency VSWR. Common solutions include balanced, active matching, distributed, lossy matching, and negative feedback wideband circuit structures. However, these still suffer from narrow bandwidth and low output power. Distributed matching networks can achieve bandwidths of tens of octaves and obtain higher output power, but suffer from high power loss and low efficiency. Lossy matching networks extend bandwidth by adding lossy components, but suffer from increased losses and low output power. Reactive matching networks offer advantages such as low loss, simple structure, and large power capacity, but the bandwidth is relatively narrow; this can be extended by adding wider matching structures.

[0004] Traditional monolithic power amplifiers cannot achieve high power output within a 40-octave bandwidth. Using power combining methods would lead to increased power consumption, increased size and cost, and increased technical complexity. Traditional high-power devices cannot achieve a 40-octave operating bandwidth. Summary of the Invention: Purpose of the invention: To address the aforementioned shortcomings in the prior art, the power amplifier internal matching circuit provided by this invention, combined with the recommended large-grid-width die, enables the power amplifier to simultaneously achieve both 40-octave ultra-wideband and high-power output.

[0005] Technical solution: The present invention provides an internal matching circuit for a 40-octave ultra-wideband high-power amplifier, including an input matching circuit, an output matching circuit, a gate bias circuit, and a drain bias circuit; wherein the die connected to the internal matching circuit needs to be adapted to a large gate width GaN die.

[0006] The output matching circuit includes a single-stage LC structure, five segments of gradually zigzag microstrip lines, and a DC blocking capacitor. It is a reactive matching structure. The zigzag microstrip lines connected to the die represent the inductance in the single-stage LC structure, and the capacitor in the single-stage LC structure is a grounded capacitor. All components are bonded to the microstrip lines using gold wire bonding.

[0007] The input matching circuit includes a single-stage LC structure, three segments of gradually zigzagging microstrip lines, and a DC blocking capacitor. It is a multi-stage reactive matching structure. The inductance in the single-stage LC structure is implemented by the microstrip line, and the capacitor is a grounded capacitor. All components are bonded to the microstrip line using gold wire bonding.

[0008] The beneficial effects of this invention are as follows: both the input and output circuits use reactive matching circuits, which have the advantages of low loss, large power capacity, and simple circuit structure. Furthermore, by loading a multi-stage tapered structure (multi-stage tapered microstrip line) to extend the bandwidth, 40-octave ultra-wideband matching is achieved. Adding DC blocking (matching) capacitors to the ports of the input and output matching circuits achieves wideband matching and improved drain efficiency.

[0009] Furthermore, the gate bias circuit is an RC series network, wherein resistors R are loaded between microstrip lines connected to the die and bonded to capacitors with gold wires, and connected to the control circuit port using DC feed lines; the drain bias circuit is an LC series network, consisting of DC feed lines, decoupling capacitors and inductors, wherein the inductor is a large-linewidth on-chip spiral inductor wound with quartz material.

[0010] The beneficial effects of the above-mentioned further solutions are as follows: the bias circuit not only provides voltage and current to the power amplifier, but also isolates AC signals and filters out high-frequency noise in DC signals; the large inductor in the gate bias circuit can eliminate low-frequency oscillations and achieve RF isolation, reducing the impact of the bias circuit on bandwidth; the decoupling capacitor can filter out interference signals in a wide bandwidth, enhancing circuit stability. The drain bias circuit... LC The inductor of the resonant circuit is implemented using a spiral inductor made of quartz material. This inductor has high efficiency and low insertion loss characteristics, and its large linewidth design can carry high power and high current. Furthermore, the large inductor design has no radio frequency blocking in the ultra-wideband.

[0011] Furthermore, the die of the 40-octave ultrawideband high-power amplifier is adapted to GaN HEMT technology and is compatible with 7.2mm~10mm large grid width dies, with a recommended die size of 5×0.8mm.

[0012] The beneficial effects of the above-mentioned further solutions are: the large gate width GaN HEMT die has the performance to meet the high heat dissipation requirements of high power amplifiers, and its output impedance is greater, which is more conducive to ultra-wideband matching. Attached image description: Figure 1 This invention proposes an internal matching circuit topology for a 40-octave ultrawideband high-power amplifier. Figure 2 This invention presents a layout of an internal matching circuit for a 40-octave ultrawideband high-power amplifier. Figure 3 The output power and efficiency of the 40-octave ultra-wideband high-power amplifier in a specific embodiment of the present invention; Figure 4 This refers to the gain of the 40-octave ultra-wideband high-power amplifier in a specific embodiment of the present invention. Detailed implementation method: The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0013] This invention provides a 40-octave ultra-wideband high-power amplifier, the circuit topology of which is as follows: Figure 1 As shown, it includes: an input matching circuit (A), an output matching circuit (B), a gate bias circuit (C), and a drain bias circuit (D). The die connected to the internal matching circuit must be compatible with a large gate width GaN die.

[0014] like Figure 1 As shown, the input matching network in this embodiment of the invention includes a DC blocking capacitor C1, three progressive microstrip lines TL1, TL2, and TL3, a grounding capacitor C2, and a short-circuited microstrip line TL4 representing inductance; the output matching network includes a DC blocking capacitor C6, five progressive microstrip lines TL6, TL7, TL8, TL9, and TL10, a grounding capacitor C5, and a zigzag microstrip line TL5 representing inductance; the gate bias circuit includes a decoupling capacitor C3 and a large resistor R; the drain bias circuit includes a large inductor L2 and a decoupling capacitor C4.

[0015] like Figure 2 The diagram shows the layout of the internal matching circuit of a 40-octave ultra-wideband high-power amplifier proposed in this invention. Its overall layout is similar to... Figure 1 The topology corresponds to that.

[0016] For the input matching circuit, a first DC blocking capacitor (3) is bonded to a three-segment asymmetric microstrip line (4) via a gold wire (1) using a 50Ω microstrip line (2) connected to the pin of the housing. Then, a first grounding capacitor (5) and a short-circuit microstrip line (6) representing inductance are connected sequentially using gold wire. The lengths and widths of the three-segment asymmetric microstrip lines are 8800um / 320um, 10800um / 870um, and 10000um / 2600um (with a dimensional tolerance of 5%), respectively, and they are loaded onto a 254um (±10um) thick 99.6% alumina ceramic substrate. The DC blocking capacitor (3) is sintered on an 800*800um pad with a capacitance of 10pF. The first grounding capacitor (5) is loaded on a ceramic substrate with a thickness of 180 μm (±10 μm) and a dielectric constant of 85. The substrate dimensions are 1000 μm wide and 3600 μm long (with a 5% allowable dimensional error), and the capacitance value is 15 pF. The shorting microstrip line (6) characterizing the inductance is loaded on a 99.6% alumina ceramic substrate with a thickness of 380 μm (±10 μm). The microstrip line has a width of 400 μm and a length of 3600 μm (with a 5% allowable dimensional error).

[0017] For the output circuit, starting from the zigzag microstrip line (8) connecting the die (6) to the die using gold wire bonding, the second grounding capacitor (9), the five-level gradient zigzag microstrip line (10), and the second DC blocking capacitor (11) are connected in sequence. The zigzag microstrip line (8), which characterizes the inductance, is loaded on a quartz ceramic substrate with a thickness of 380um (±10um). The specific parameters of this microstrip line are 300um in length / 3600um in width, 3200um in length / 60um in width, and 200um in length / 1200um in width (with a 5% allowable dimensional error). The second grounding capacitor (11) is loaded on a ceramic substrate with a thickness of 180um (±10um) and a dielectric constant of 38. Its dimensions are 600um in width and 1200um in length (with a 5% allowable dimensional error). A five-level gradient zigzag microstrip line (10) is loaded onto a 380um (±10um) thick 99.6% alumina ceramic substrate. The specific dimensions of the five gradient lines are: length 10900um / width 1180um, length 10960um / width 1040um, length 16325um / width 700um, length 13900um / width 560um, and length 8445um / width 440um, respectively. The second DC blocking capacitor (11) is sintered on an 800*800 pad with a capacitance of 1000pF.

[0018] For the gate bias circuit, a first decoupling capacitor (13) and a large-resistance thin-film resistor (14) are connected sequentially from the case lead using a gold-bonded DC feed line (12). The resistor has a sheet resistance of 25 ohms, a width of 300 μm, and a length of 600 μm (with a 5% tolerance for size). It is loaded on the same alumina ceramic substrate as the shorted microstrip line (6) that characterizes the inductance. For the drain bias circuit, a second decoupling capacitor (16) and an on-chip spiral inductor (17) are connected sequentially from the case lead using a metal-bonded DC feed line (15). The second decoupling capacitor (16) is loaded on a quartz ceramic substrate with a thickness of 380 μm (±10 μm). The circuit board size is 889 μm × 889 μm. The on-chip spiral inductor (17) is made of quartz material and has a large linewidth of 0.1 mm.

[0019] The following is combined with Figure 2 The specific working principle and process of this invention will be described below: In this invention, the radio frequency signal enters the input matching network of the amplifier from the input terminal. After impedance matching by the input matching network, the signal enters the GaN HEMT die for signal amplification. The amplified signal then enters the output matching network for signal output matching, and finally forms the radio frequency output signal that reaches the output terminal.

[0020] The specific implementation of this invention uses a 0.35μm GaN HEMT process, with a die breakdown voltage greater than 200V, a saturation current exceeding 1A / mm, a saturated output power density of 8W / mm at a 48V operating voltage, and a die saturated output power of 55W. The output impedance of the die in this specific implementation is obtained using a load pulling method, and the die's output impedance is a 21Ω resistor connected in parallel with a 2.88pF capacitor.

[0021] The output matching circuit uses a reactive matching network with one stage. LC The system consists of a matching network, a DC blocking capacitor, and a three-stage tapered microstrip line. The tapered microstrip line is used to extend the bandwidth. This matching network is simple to implement, has a large power capacity, and low losses. The input matching network also uses a reactive matching network with one stage. LC It consists of a matching network, a DC blocking capacitor, and a five-stage tapered microstrip line, with the tapered microstrip line used to extend the bandwidth.

[0022] In the specific implementation of this invention, the gate bias uses an RC series network, which is connected to the shorted microstrip line in the input matching network. The loading of a large-value resistor can not only eliminate low-frequency oscillations but also achieve radio frequency isolation, reducing the impact of the bias circuit on the bandwidth. The series connection of decoupling capacitors can filter out interference signals in a wide frequency band and enhance stability.

[0023] The drain bias circuit is an LC series network, consisting of a DC feed line, a decoupling capacitor, and an inductor. The inductor is a large-linewidth on-chip spiral inductor made of quartz material. The low dielectric constant of quartz material is beneficial for achieving high efficiency and low insertion loss, and the large linewidth design can better carry high power and high current. The large inductance value ensures no RF blocking in the ultra-wideband.

[0024] The matching circuit is fabricated using a high dielectric constant substrate and combined with GaN technology to achieve miniaturization and high performance of the amplifier.

[0025] In the specific implementation of this invention, the ultra-wideband high-power amplifier uses continuous wave mode, which has a large heat dissipation and obvious heat deposition effect. Considering that the performance of the die is closely related to temperature, and that excessively high temperature will seriously affect its reliability, a heat-bearing shell made of molybdenum copper CPC material with a thermal conductivity of 260 K / m (18) is used to achieve this.

[0026] In the specific implementation of the present invention, Figure 3 and Figure 4 The figures show the test results of the ultra-wideband high-power internal matching circuit after assembly with GaN chips, including test curves for output power, drain efficiency, and gain. In the 0.1-4.2 GHz frequency range, with a saturated input power of 35 dBm, the typical saturated output power is 46 dBm (40 W), power flatness is ±1 dB, gain is greater than 10.5 dB, gain flatness is less than ±1.0 dB, and saturated drain efficiency is 25%~62%. This invention's circuit is a reactive internal matching type, possessing advantages such as small size, low loss, large power capacity, and ease of mass production; moreover, it simultaneously achieves ultra-wide octave bandwidth and high power output capability, operating in a high-frequency range.

Claims

1. A 40-octave ultra-wideband high-power internal matching circuit, characterized in that, It includes an input matching circuit (2-6), an output matching circuit (8-11), a gate bias circuit (12-14), and a drain bias circuit (15-17); wherein the die connected to the internal matching circuit needs to be (7) adapted to a large gate width GaN die; The input matching circuit (2-6) uses a reactive matching network. The input matching circuit (2-6) consists of a 50Ω microstrip line (2), a first DC blocking capacitor (3), a three-stage gradually zigzag microstrip line (4), a first grounding capacitor (5), and a microstrip line (6) connecting the chip, sequentially from the signal input to the chip. The output matching circuit (8-11) uses a reactive matching network. The output matching circuit (8-11) consists of a tortuous microstrip line (8) connected to the die, a second grounding capacitor (9), a five-level tapered tortuous microstrip line (10), and a second DC blocking capacitor (11).

2. The 40-octave ultra-wideband high-power internal matching circuit according to claim 1, characterized in that: The gate bias circuit (12-14) is connected to the microstrip line (6) of the die at the input matching circuit terminal. It is an RC series network consisting of a large resistance resistor (14), a first decoupling capacitor (13) and a first DC feed line (12). The drain bias circuit (15-17) is connected to the tortuous microstrip line (8) of the connecting die at the output matching circuit terminal. It is a series LC network, which consists of an on-chip spiral inductor (17), a second decoupling capacitor (16), and a second DC feed line (15).

3. The 40-octave ultra-wideband high-power internal matching circuit according to claim 2, characterized in that, The large-linewidth on-chip spiral inductor (17) in the drain bias circuit (15-17) is made of quartz material, which realizes the wide bandwidth, high efficiency and low insertion loss of the inductor, and the large-linewidth design can carry high power and high current.

4. The 40-octave ultra-wideband high-power internal matching circuit according to claim 1, characterized in that, The compatible die is based on GaN HEMT technology and is compatible with 7.2mm~10mm large gate width dies. The die size is 5×0.8mm to meet the high heat dissipation requirements of high power amplifiers.

5. The 40-octave ultra-wideband high-power internal matching circuit according to claim 1, characterized in that, The three-level gradient tortuous microstrip line (4), the microstrip line connecting the die (6), and the three-level gradient tortuous microstrip line (10) are all loaded on an alumina ceramic substrate; the first grounding capacitor (5) is loaded on a ceramic substrate with a dielectric constant of 85; the tortuous microstrip line connecting the die (8) is loaded on a quartz ceramic substrate; and the second grounding capacitor (9) is loaded on a ceramic substrate with a dielectric constant of 38.

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