A broadband high-balance active balun circuit

Abstract

The application discloses a kind of broadband high balance degree active balun circuit, including differential signal generation circuit, voltage synthesizer negative feedback circuit and output balanced buffer circuit.Differential signal generation circuit is made of two-stage self-biased inverter cascade, and the differential signal generated by inverter is first connected with the gate of voltage synthesizer, and is connected with the input end of first-stage inverter through feedback loop after being synthesized into single-ended signal, to realize input impedance matching;Secondly, it is connected with the gate of output balanced buffer, to complete output impedance matching while outputting differential signal.The application introduces voltage synthesis negative feedback technology to replace traditional resistance negative feedback technology on the basis of self-biased inverter structure, not only expands working bandwidth, but also improves the symmetry of circuit, and improves the amplitude-phase unbalance of output differential signal and the linearity of overall circuit by connecting a transistor in diode connection mode in parallel with the output end of second-stage inverter.

Description

Technical Field

[0001] This invention relates to an integrated circuit, and more particularly to a broadband, high-balance active balun circuit. Background Technology

[0002] In wireless systems such as communication systems, differential architectures offer lower even-order nonlinearity and higher common-mode rejection ratios compared to single-ended architectures. Furthermore, designing a wireless system with single-ended inputs helps reduce pin count. To connect a single-ended input signal to a differential architecture wireless system, an additional balun structure is needed. A common approach is to use a passive balun to convert the single-ended signal to a differential signal. However, when the wireless system operates at low frequencies, passive baluns require large inductance values, resulting in large chip area and high cost. Additionally, the insertion loss of passive baluns can affect subsequent circuitry. Moreover, passive baluns struggle to meet broadband requirements. To alleviate these challenges, active baluns combine the balun function with active circuitry. They can be highly integrated with subsequent circuitry, avoiding the insertion loss associated with passive baluns and saving chip area and cost.

[0003] Currently, most active balun circuits use off-chip inductors for input matching to achieve wide bandwidth, but this reduces integration density. On the other hand, traditional resistive negative feedback matching can achieve on-chip integration, but its bandwidth is narrower. Furthermore, as the operating frequency of active balun circuits increases, the amplitude-phase imbalance of the output signal and the linearity of the circuit gradually deteriorate. Therefore, how to extend the operating bandwidth of active balun circuits and how to improve the amplitude-phase imbalance and linearity of the output differential signal have become urgent problems to be solved. Summary of the Invention

[0004] Technical problem: To address the problems of narrow bandwidth, amplitude and phase imbalance, and poor linearity of traditional active balun circuits, a broadband, high-balance active balun circuit is proposed to expand the bandwidth and improve the amplitude and phase imbalance of the output differential signal as well as the linearity of the circuit.

[0005] Technical Solution: The present invention provides a broadband high-balance active balun circuit, comprising a differential signal generation circuit, a voltage synthesis negative feedback circuit, and an output balancing buffer circuit; wherein, the input terminals of the differential signal generation circuit and the voltage synthesis negative feedback circuit are connected to the input terminals through an input DC blocking capacitor, the input terminals of the differential signal generation circuit and the first and second voltage signal terminals of the voltage synthesis negative feedback circuit are respectively connected to the input terminals of the output balancing buffer circuit, and the output terminals of the output balancing buffer circuit are the positive and negative output terminals of the broadband high-balance active balun circuit.

[0006] The differential signal generation circuit consists of two cascaded inverters. The first inverter consists of a first transistor, a second transistor, and a first resistor. The gates of the first transistor and the second transistor are connected together, and their drains are connected together. The source of the first transistor is grounded, and the source of the second transistor is connected to the power supply. One end of the first resistor is connected to the gates of the first transistor and the second transistor as the input terminal of the differential signal generation circuit, and the other end is connected to the drains of the first transistor and the second transistor, i.e., the first voltage signal terminal. The second inverter consists of a third transistor, a fourth transistor, and a second resistor. The gates of the third transistor and the fourth transistor are connected together, and their drains are connected together. The source of the third transistor is grounded, and the source of the fourth transistor is connected to the power supply. One end of the second resistor is connected to the gates of the third transistor and the fourth transistor, i.e., the first voltage signal terminal, and the other end is connected to the drains of the third transistor and the fourth transistor, i.e., the second voltage signal terminal.

[0007] The voltage synthesis negative feedback circuit consists of a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a sixth transistor, a seventh transistor, a feedback loop capacitor, and a feedback loop resistor. One end of the first DC blocking capacitor is connected to the drains of the third and fourth transistors (i.e., the second voltage signal terminal), and the other end is connected to the gate of the sixth transistor. One end of the second DC blocking capacitor is connected to the drains of the first and second transistors (i.e., the first voltage signal terminal), and the other end is connected to the gate of the seventh transistor. One end of the feedback resistor is connected to the gates of the first and second transistors as the input terminal of the voltage synthesis negative feedback circuit, and the other end is connected to the drain of the sixth transistor and the source of the seventh transistor through the feedback loop capacitor. This negative feedback structure is used to achieve input impedance matching.

[0008] The output balancing buffer circuit consists of two asymmetric voltage synthesizer structures. The first voltage synthesizer structure includes a third DC blocking capacitor, a fourth DC blocking capacitor, a seventh DC blocking capacitor, an eighth transistor, a ninth transistor, a third bias resistor, and a fourth bias resistor. The gate of the eighth transistor is connected to the first voltage signal terminal via the third DC blocking capacitor and to the bias voltage via the third bias resistor. The drain of the eighth transistor is connected to the positive output terminal via the seventh DC blocking capacitor. The gate of the ninth transistor is connected to the second voltage signal terminal via the fourth DC blocking capacitor and to the power supply via the fourth bias resistor. The source of the eighth transistor is connected to the positive output terminal via the seventh DC blocking capacitor.

[0009] The second voltage synthesizer structure includes a fifth DC blocking capacitor, a sixth DC blocking capacitor, an eighth DC blocking capacitor, a fifth bias resistor, a sixth bias resistor, a tenth transistor, and an eleventh transistor; its structure is consistent with the first voltage synthesizer structure, forming two asymmetrical voltage synthesizer structures, which are used to improve the amplitude and phase imbalance of the differential signal generated by the inverter.

[0010] The gate width selection of the eighth, ninth, tenth, and eleventh transistors in the output balancing buffer should optimize the amplitude and phase balance of the output differential signal.

[0011] The differential signal generation circuit has a second voltage signal terminal, and a fifth transistor is provided between the second voltage signal terminal and ground. The gate and drain of the fifth transistor are connected to the second voltage signal terminal, and the source of the fifth transistor is grounded. The overall linearity of the circuit is improved by connecting the transistor in parallel.

[0012] The input DC blocking capacitor and the voltage synthesis negative feedback circuit work together to achieve input impedance matching.

[0013] The bias voltage should be selected to achieve optimal amplitude and phase balance of the output differential signal.

[0014] Beneficial Effects: The advantages of this invention lie in providing a broadband, highly balanced active balun circuit, composed of a differential signal generation circuit, a voltage synthesis negative feedback circuit, and an output balancing buffer circuit. This invention introduces voltage synthesis negative feedback technology to replace traditional resistive negative feedback technology on the basis of a self-biased inverter structure. This not only expands the operating bandwidth but also improves the circuit's symmetry. By connecting a diode-connected transistor in parallel at the output of the second-stage inverter, the amplitude and phase imbalance of the output differential signal and the overall linearity of the circuit are improved. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the active balun circuit in this invention;

[0016] Figure 2 The reflection coefficients of the input and output ports of the active balun circuit in this invention;

[0017] Figure 3 The differential gain of the active balun circuit in this invention;

[0018] Figure 4 The amplitude difference and phase difference of the differential signal output by the active balun circuit in this invention;

[0019] Figure 5 This is the 1dB compression point of the active balun circuit in this invention.

[0020] The diagram shows: first transistor M1, second transistor M2, first resistor R1, third transistor M3, fourth transistor M4, fifth transistor M5, second resistor R2, first DC blocking capacitor C1, second DC blocking capacitor C2, first bias resistor Rbias1, second bias resistor Rbias2, sixth transistor M6, seventh transistor M7, feedback loop capacitor Cf, feedback loop resistor Rf, third DC blocking capacitor C3, fourth DC blocking capacitor C4, fifth DC blocking capacitor C5, sixth DC blocking capacitor C6, seventh DC blocking capacitor C7, eighth DC blocking capacitor C8, third bias resistor Rbias3, fourth bias resistor Rbias4, fifth bias resistor Rbias5, sixth bias resistor Rbias6, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11, input DC blocking capacitor Cin, power supply VDD, input port IN, positive output terminal OUT+, negative output terminal OUT-. Detailed Implementation

[0021] The present invention will be further explained below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0022] This embodiment provides a broadband, high-balance active balun circuit, such as... Figure 1 , 2 As shown, it consists of a differential signal generation circuit, a voltage synthesis negative feedback circuit, and an output balancing buffer circuit.

[0023] The differential signal generation circuit consists of two cascaded inverters. The first inverter consists of a first transistor M1, a second transistor M2, and a first resistor R1. The gates of the first transistor M1 and the second transistor M2 are connected together, and their drains are connected together. The source of the first transistor M1 is grounded, and the source of the second transistor M2 is connected to the power supply VDD. One end of the first resistor R1 is connected to the gates of the first transistor M1 and the second transistor M2, and the other end is connected to the drains Vn of the first transistor M1 and the second transistor M2. The second inverter consists of a third transistor M3, a fourth transistor M4, and a second resistor R2. The gates of the third transistor M3 and the fourth transistor M4 are connected together, and their drains are connected together. The source of the third transistor M3 is grounded, and the source of the fourth transistor M4 is connected to the power supply VDD. One end of the second resistor R2 is connected to the gates of the third transistor M3 and the fourth transistor M4, and the other end is connected to the drains Vp of the third transistor M3 and the fourth transistor M4.

[0024] The voltage synthesis negative feedback circuit consists of a first DC blocking capacitor C1, a second DC blocking capacitor C2, a first bias resistor Rbias1, a second bias resistor Rbias2, a sixth transistor M6, a seventh transistor M7, a feedback loop capacitor Cf, and a feedback loop resistor Rf. The gate of the sixth transistor M6 is connected to one end of the first DC blocking capacitor C1 and also to one end of the first bias resistor Rbias1, the other end of which is connected to the bias voltage Vbias. The gate of the seventh transistor M7 is connected to one end of the second DC blocking capacitor C2 and also to one end of the second bias resistor Rbias2, the other end of which is connected to the power supply VDD. The drain of the sixth transistor M6 is connected to the source of the seventh transistor M7, the source of the sixth transistor M6 is grounded, and the drain of the seventh transistor M7 is connected to the power supply VDD. One end of the feedback loop capacitor Cf is connected to the drain of the sixth transistor M6, and the other end is connected to one end of the feedback resistor Rf.

[0025] The output balancing buffer circuit consists of a third DC blocking capacitor C3, a fourth DC blocking capacitor C4, a fifth DC blocking capacitor C5, a sixth DC blocking capacitor C6, a seventh DC blocking capacitor C7, an eighth DC blocking capacitor C8, a third bias resistor Rbias3, a fourth bias resistor Rbias4, a fifth bias resistor Rbias5, a sixth bias resistor Rbias6, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The gate of the eighth transistor M8 is connected to one end of the third DC blocking capacitor C3 and also to one end of the third bias resistor Rbias3. The other end of the third bias resistor Rbias3 is connected to the bias voltage Vbias. The gate of the ninth transistor M9 is connected to one end of the fourth DC blocking capacitor C4 and also to one end of the fourth bias resistor Rbias4. The other end of the fourth bias resistor Rbias4 is connected to the power supply VDD. The drain of the eighth transistor M8 is connected to the source of the ninth transistor M9. The source of the eighth transistor M8 is grounded, and the drain of the ninth transistor M9 is connected to the power supply VDD. One end of the seventh DC blocking capacitor C7 is connected to the drain of the eighth transistor M8, and the other end is connected to the signal output terminal OUT+. The gate of the tenth transistor M10 is connected to one end of the fifth DC blocking capacitor C5, and also to one end of the fifth bias resistor Rbias5. The other end of the fifth bias resistor Rbias5 is connected to the bias voltage Vbias. The gate of the eleventh transistor M11 is connected to one end of the sixth DC blocking capacitor C6, and also to one end of the sixth bias resistor Rbias6. The other end of the sixth bias resistor Rbias6 is connected to the power supply VDD. The drain of the tenth transistor M10 is connected to the source of the eleventh transistor M11. The source of the tenth transistor M10 is grounded, and the drain of the eleventh transistor M11 is connected to the power supply VDD. One end of the eighth DC blocking capacitor C8 is connected to the drain of the tenth transistor M10, and the other end is connected to the signal output terminal OUT-.

[0026] In the voltage synthesis negative feedback circuit, the first DC blocking capacitor C1 is connected to the drain Vp of the third transistor M3 and the fourth transistor M4, and the second DC blocking capacitor C2 is connected to the drain Vn of the first transistor M1 and the second transistor M2. The feedback resistor Rf is connected to the gate of the first transistor M1 and the second transistor M2. This negative feedback structure is used to achieve input impedance matching.

[0027] The third DC blocking capacitor C3 and the sixth DC blocking capacitor C6 in the output balancing buffer circuit are connected to the drains Vn of the first transistor M1 and the second transistor M2, and the fourth DC blocking capacitor C4 and the fifth DC blocking capacitor C5 are connected to the drains Vp of the first transistor M3 and the second transistor M4. The output balancing buffer circuit outputs the differential signal while simultaneously performing output impedance matching.

[0028] The gate of the fifth transistor M5 is connected to its drain, and is also connected to the drains of the third transistor M3 and the fourth transistor M4. The source of the fifth transistor M5 is grounded. The overall linearity of the circuit is improved by connecting this transistor in parallel.

[0029] In terms of working principle, this invention provides a broadband, highly balanced active balun circuit. Based on a self-biased inverter structure, this invention introduces voltage synthesis negative feedback technology, which not only expands the operating bandwidth but also improves the circuit's symmetry. By connecting a diode-connected transistor in parallel at the output of the second-stage inverter, the amplitude and phase imbalance of the output differential signal and the overall linearity of the circuit are improved. More specifically:

[0030] The voltage synthesis structure used in this invention, compared to the traditional resistive negative feedback structure, enables the differential ports to participate in feedback control simultaneously, which improves the symmetry of the inverter cascade structure to a certain extent. It also increases the gain across the feedback resistor, effectively increasing the resistance value of the feedback resistor. Compared to the traditional resistive negative feedback structure, the voltage synthesis negative feedback structure requires a smaller feedback resistor value under input matching conditions. This is because the input matching bandwidth is determined by the time constant generated by the capacitance and resistance of the feedback loop. The reduction in resistance expands the bandwidth to a certain extent.

[0031] In this invention, a transistor connected in parallel with a diode is connected at the output of the second-stage inverter. Considering the large amplitude difference between the differential signals output by the two-stage inverters, the output gain of the second-stage inverter signal is adjusted by connecting this transistor in parallel, thereby reducing the amplitude difference of the final differential signal. At the same time, the transistor in parallel shunts the current of the inverter transistor, introducing additional second- and third-order nonlinear components. At the output node, the third-order nonlinear components cancel each other out, thus performing nonlinear compensation for the second-stage inverter and improving the overall linearity of the circuit.

[0032] Based on the above working principle, this embodiment uses CMOS technology to design and simulate the circuit, verifying the practicality of the present invention.

[0033] Figure 2 The reflection coefficients of each port of the designed active balun circuit are given. The reflection coefficient of the input port is less than -10dB in the frequency range of 5.89 to 14.06 GHz, with a relative bandwidth of 82%. The reflection coefficient of the output port is less than -10dB in the frequency range of 4 GHz. Figure 3 The differential gain of the designed active balun circuit is given. In the frequency range of 1.44 to 15.24 GHz, the differential gain is 2.23 dB to 5.23 dB, and the 3 dB bandwidth is 165.5%. Figure 4 The amplitude difference and phase difference of the output differential signal of the designed active balun circuit are given. The amplitude difference is -0.543dB to 0.195dB and the phase difference is 178° to 179.8° in the frequency range of 4 to 18 GHz. Figure 5 The input 1dB compression point of the designed active balun circuit is given as -9.95dBm.

[0034] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A broadband, high-balance active balun circuit, characterized in that, It includes a differential signal generation circuit, a voltage synthesis negative feedback circuit, and an output balancing buffer circuit. The input terminals of the differential signal generation circuit and the voltage synthesis negative feedback circuit are connected to the input terminal (IN) through an input DC blocking capacitor (Cin). The output terminal of the differential signal generation circuit and the first voltage signal terminal (VN) and the second voltage signal terminal (Vp) of the voltage synthesis negative feedback circuit are respectively connected to the input terminal of the output balancing buffer circuit. The output terminal of the output balancing buffer circuit is the positive output terminal (OUT+) and the negative output terminal (OUT-) of a broadband high-balance active balun circuit. The differential signal generation circuit consists of two cascaded self-biased inverters. The first self-biased inverter comprises a first transistor (M1), a second transistor (M2), and a first resistor (R1). The gates of the first transistor (M1) and the second transistor (M2) are connected to each other, and their drains are connected to each other. The source of the first transistor (M1) is grounded, and the source of the second transistor (M2) is connected to the power supply (VDD). One end of the first resistor (R1) is connected to the gates of the first transistor (M1) and the second transistor (M2) as the input terminal of the differential signal generation circuit, and the other end is connected to the drains of the first transistor (M1) and the second transistor (M2). The first voltage signal terminal (VN) and the second-stage self-biased inverter are composed of a third transistor (M3), a fourth transistor (M4) and a second resistor (R2). The gates of the third transistor (M3) and the fourth transistor (M4) are connected to each other, and their drains are connected to each other. The source of the third transistor (M3) is grounded, and the source of the fourth transistor (M4) is connected to the power supply (VDD). One end of the second resistor (R2) is connected to the gates of the third transistor (M3) and the fourth transistor (M4), which is the first voltage signal terminal (VN), and the other end is connected to the drains of the third transistor (M3) and the fourth transistor (M4), which is the second voltage signal terminal (Vp). The voltage synthesis negative feedback circuit consists of a first DC blocking capacitor (C1), a second DC blocking capacitor (C2), a first bias resistor (Rbias1), a second bias resistor (Rbias2), a sixth transistor (M6), a seventh transistor (M7), a feedback loop capacitor (Cf), and a feedback loop resistor (Rf). One end of the first DC blocking capacitor (C1) is connected to the drains of the third transistor (M3) and the fourth transistor (M4), i.e., the second voltage signal terminal (Vp), and the other end is connected to the gate of the sixth transistor (M6). One end of the second DC blocking capacitor (C2) is connected to the drains of the first transistor (M1) and the second transistor (M2), i.e., the first voltage signal terminal (VN), and the other end is connected to the gate of the seventh transistor (M7). One end of the feedback resistor (Rf) is connected to the gates of the first transistor (M1) and the second transistor (M2) as the input terminal of the voltage synthesis negative feedback circuit, and the other end is connected to the drain of the sixth transistor (M6) and the source of the seventh transistor (M7) through the feedback loop capacitor (Cf). A feedback loop is used to achieve input impedance matching without inductors. A fifth transistor (M5) is also provided between the second voltage signal terminal and ground. The gate and drain of the fifth transistor (M5) are connected to the second voltage signal terminal (VP), and the source of the fifth transistor is grounded. This is used to improve the amplitude and phase balance and linearity of the differential output signal by current shunting and canceling the third-order nonlinear components at the output node.

2. The broadband high-balance active balun circuit according to claim 1, characterized in that, The output balancing buffer circuit consists of two asymmetric voltage synthesizer structures. The first voltage synthesizer structure includes a third DC blocking capacitor (C3), a fourth DC blocking capacitor (C4), a seventh DC blocking capacitor (C7), an eighth transistor (M8), a ninth transistor (M9), a third bias resistor (Rbias3), and a fourth bias resistor (Rbias4). The gate of the eighth transistor (M8) is connected to the first voltage signal terminal (VN) through the third DC blocking capacitor (C3) and to the bias voltage (Vbias) through the third bias resistor (Rbias3). The drain of the eighth transistor (M8) is connected to the positive output terminal (OUT+) through the seventh DC blocking capacitor (C7). The gate of the ninth transistor (M9) is connected to the second voltage signal terminal (Vp) through the fourth DC blocking capacitor (C4) and to the power supply (VDD) through the fourth bias resistor (Rbias4). The source of the eighth transistor (M8) is connected to the positive output terminal (OUT+) through the seventh DC blocking capacitor (C7). The second voltage synthesizer structure includes a fifth DC blocking capacitor (C5), a sixth DC blocking capacitor (C6), an eighth DC blocking capacitor (C8), a fifth bias resistor (Rbias5), a sixth bias resistor (Rbias6), a tenth transistor (M10), and an eleventh transistor (M11). Its structure is consistent with that of the first voltage synthesizer structure, forming two asymmetrical voltage synthesizer structures. This structure is used to improve the amplitude and phase imbalance of the differential signal generated by the inverter.

3. The broadband high-balance active balun circuit according to claim 1, characterized in that, The gate width selection of the eighth transistor (M8), ninth transistor (M9), tenth transistor (M10), and eleventh transistor (M11) in the output balancing buffer should optimize the amplitude and phase balance of the output differential signal.

Images