Comparator and decision feedback equalization circuit

Abstract

This application provides a comparator and a decision feedback equalization circuit, including a first sampling circuit for generating a first differential signal based on a signal to be compared and a first reference signal under the control of a first control signal and a clock signal; a first positive feedback circuit for accelerating the difference between the first differential signals; a second sampling circuit for generating a second differential signal based on the signal to be compared and a second reference signal under the control of a second control signal and a clock signal; wherein the first reference signal is greater than the second reference signal; a second positive feedback circuit for accelerating the difference between the second differential signals; and an output circuit for amplifying and latching the voltage signal at the output of the first sampling circuit or the voltage signal at the output of the second sampling circuit, and outputting a comparison result. The first and second sampling circuits are configured to eliminate inter-symbol interference, and the first and second positive feedback circuits are configured to reduce power loss and improve response rate.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among these, the comparator is a crucial device for realizing DRAM data read and write operations, and existing comparators cannot meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to eliminate inter-symbol interference of the comparator, improve the response rate, and reduce the power consumption of the comparator.

[0005] One embodiment of this application provides a comparator, including:

[0006] The first sampling circuit has an output terminal, which is used to generate a first differential signal based on the signal to be compared and the first reference signal under the control of the first control signal and the clock signal.

[0007] The first positive feedback circuit is connected to the output of the first sampling circuit and is used to accelerate the difference between the first differential signals.

[0008] The second sampling circuit has an output terminal connected to the output terminal of the first sampling circuit. It is used to generate a second differential signal based on the signal to be compared and the second reference signal under the control of the second control signal and the clock signal. The first reference signal is greater than the second reference signal.

[0009] The second positive feedback circuit is connected to the output of the second sampling circuit and is used to accelerate the difference between the second differential signals.

[0010] The output circuit has an input terminal connected to the output terminal of the first sampling circuit. It is used to amplify and latch the voltage signal from the output terminal of the first sampling circuit or the voltage signal from the output terminal of the second sampling circuit, and output the comparison result.

[0011] Another embodiment of this application provides a decision feedback equalization circuit, including the comparators in the above embodiments, which are sequentially labeled as a first comparator, a second comparator, a third comparator, and a fourth comparator;

[0012] The first comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, a fourth and fifth input terminals connected to the output terminal of the fourth comparator for receiving the first control signal and the second control signal, and a sixth input terminal for receiving the first clock signal.

[0013] The second comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, a fourth and a fifth input terminal connected to the output terminal of the first comparator for receiving the first control signal and the second control signal, and a sixth input terminal for receiving the second clock signal.

[0014] The third comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, a fourth and a fifth input terminal connected to the output terminal of the second comparator for receiving the first control signal and the second control signal, and a sixth input terminal for receiving the third clock signal.

[0015] The fourth comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, and its fourth and fifth input terminals connected to the output terminal of the third comparator for receiving the first control signal and the second control signal. Its sixth input terminal is used to receive the fourth clock signal.

[0016] The comparator and decision feedback equalization circuit provided in this application includes a first sampling circuit, a second sampling circuit, an output circuit, a first positive feedback circuit, and a second positive feedback circuit. The first sampling circuit, under the control of a first control signal and a clock signal, outputs a first differential signal based on a first reference signal and a signal to be compared. The second sampling circuit, under the control of a second control signal and a clock signal, outputs a second differential signal based on a second reference signal and a signal to be compared. The first reference signal is set to be greater than the second reference signal. When the signal to be compared is affected by increased inter-symbol interference (ISI), the larger first reference signal is used to sample the signal to be compared. When the ISI is reduced, the smaller second reference signal is used to sample the signal to be compared. This ensures that the polarity of the differential signal generated before the signal to be compared is the same as the polarity of the differential signal generated after the signal to be compared is affected, allowing the output circuit to output a more accurate comparison result, thereby eliminating ISI. Furthermore, the first positive feedback circuit accelerates the generation of the first differential signal, and the second positive feedback circuit accelerates the generation of the second differential signal, shortening the sampling stage time, thereby improving the comparator's response rate and reducing its power consumption. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of a comparator provided in an embodiment of this application;

[0018] Figure 2 A specific circuit diagram of a comparator provided in one embodiment of this application;

[0019] Figure 3 A specific circuit diagram of a comparator provided in one embodiment of this application;

[0020] Figure 4 A block diagram of a decision feedback equalization circuit is provided for one embodiment of this application;

[0021] Figure 5 A timing diagram of a decision feedback equalization circuit is provided for one embodiment of this application. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] like Figure 1As shown, one embodiment of this application provides a comparator, which includes a first sampling circuit 101, a second sampling circuit 102, and an output circuit 103.

[0024] The first sampling circuit 101, the second sampling circuit 102, and the output circuit 103 are all provided with input terminals and output terminals. The first sampling circuit 101 and the second sampling circuit 102 are also provided with control terminals. The control terminal of the first sampling circuit 101 is used to receive a first control signal and a clock signal, and the input terminal of the first sampling circuit 101 is used to receive the signal to be compared and a first reference signal, so that the first sampling circuit 101 generates a first differential signal according to the signal to be compared and the first reference signal under the control of the first control signal and the clock signal.

[0025] The control terminal of the second sampling circuit 102 is used to receive the second control signal and the clock signal, and the input terminal of the second sampling circuit 102 is used to receive the signal to be compared and the second reference signal, so that the second sampling circuit 102 generates a second differential signal according to the signal to be compared and the second reference signal under the control of the second control signal and the clock signal.

[0026] The output terminal of the second sampling circuit 102 is connected to the output terminal of the first sampling circuit 101, and the input terminal of the output circuit 103 is also connected to the output terminal of the first sampling circuit 101, so that the output circuit 103 amplifies and latches the voltage signal at the output terminal of the first sampling circuit 101 or the voltage signal at the output terminal of the second sampling circuit 102, and outputs the comparison result.

[0027] In this configuration, the first reference signal is greater than the second reference signal. When the signal to be compared is affected and its amplitude increases, the first control signal controls the first sampling circuit 101 to sample the signal to be compared and the first reference signal to generate a first differential signal, and the second control signal controls the second sampling circuit 102 to stop sampling. When the signal to be compared is affected and its amplitude decreases, the first control signal controls the first sampling circuit 101 to stop sampling, and the second control signal controls the second sampling circuit 102 to sample the signal to be compared and the second reference signal to generate a second differential signal. By this configuration, when the amplitude of the signal to be compared decreases due to the influence of the influence, a second reference signal with a smaller amplitude is used; when the amplitude of the signal to be compared increases due to the influence of the influence, a first reference signal with a larger amplitude is used. This ensures that the polarity of the differential signal generated before the signal to be compared is the same as the polarity of the differential signal generated after the signal to be compared is influenced, so that the output circuit 103 can output a more accurate comparison result.

[0028] When the first reference signal is not properly selected, the response time of the first sampling circuit 101 becomes longer, meaning that the first sampling circuit 101 needs a longer time to present a first differential signal with a relatively large difference at the output. The first positive feedback circuit 1042 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time that the first sampling circuit 101 presents a first differential signal with a relatively large difference at the output, which shortens the time that the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing the comparator's power consumption.

[0029] Similarly, when the second reference signal is not properly selected, the response time of the second sampling circuit 102 becomes longer, meaning that the second sampling circuit 102 needs a longer time to present a second differential signal with a relatively large difference at the output. The second positive feedback circuit 1052 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time that the second sampling circuit 102 presents a second differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0030] In one embodiment, the first sampling circuit 101 includes a first sampling unit 1011 and a first control unit 1012. Both the first sampling unit 1011 and the first control unit 1012 have input terminals and output terminals. The first sampling unit 1011 also has a control terminal. The input terminal of the first control unit 1012 is used to receive a first control signal and a clock signal to control the operating mode of the first sampling unit 1011 according to the first control signal and the clock signal. The operating mode of the first sampling unit 1011 includes a sampling mode. The output terminal of the first control unit 1012 is connected to the control terminal of the first sampling unit 1011. The first sampling unit 1011, when operating in sampling mode, generates a first differential signal based on the signal to be compared and a first reference signal.

[0031] In one embodiment, the second sampling circuit 102 includes a second sampling unit 1021 and a second control unit 1022. Both the second sampling unit 1021 and the second control unit 1022 have input terminals and output terminals. The second sampling unit 1021 also has a control terminal. The input terminal of the second control unit 1022 is used to receive a second control signal and a clock signal to control the operating mode of the second sampling unit 1021 according to the second control signal and the clock signal. The operating mode of the second sampling unit 1021 includes a sampling mode. The output terminal of the second control unit 1022 is connected to the control terminal of the second sampling unit 1021. The second sampling unit 1021 is used to generate a second differential signal based on the signal to be compared and a second reference signal when operating in sampling mode.

[0032] In one embodiment, the first positive feedback circuit 104 includes a first feedback unit 1041 and a second feedback unit 1042, both of which are provided with a control terminal and a first terminal.

[0033] The control terminal of the first feedback unit 1041 is connected to the first output terminal of the first sampling circuit 101, and the first end of the first feedback unit 1041 is connected to the second output terminal of the first sampling circuit 101. The control terminal of the second feedback unit 1042 is connected to the second output terminal of the first sampling circuit 101, and the first end of the second feedback unit 1042 is connected to the first output terminal of the first sampling circuit 101.

[0034] The first feedback unit 1041 is used to pull the voltage of the second output terminal of the first sampling circuit 101 according to the voltage of the first output terminal of the first sampling circuit 101, and the second feedback unit 1042 is used to pull the voltage of the first output terminal of the first sampling circuit 101 according to the voltage of the second output terminal of the first sampling circuit 101.

[0035] The direction in which the first feedback unit 1041 pulls the voltage at the second output terminal of the first sampling circuit 101 is the same as the direction in which the second feedback unit 1042 pulls the voltage at the first output terminal of the first sampling circuit 101. When the first feedback unit 1041 pulls the voltage at the second output terminal of the first sampling circuit 101 upwards, the second feedback unit 1042 also pulls the voltage at the first output terminal of the first sampling circuit 101 upwards. When the first feedback unit 1041 pulls the voltage at the second output terminal of the first sampling circuit 101 downwards, the second feedback unit 1042 also pulls the voltage at the first output terminal of the first sampling circuit 101 downwards.

[0036] In one embodiment, the second positive feedback circuit 105 includes a third feedback unit 1051 and a fourth feedback unit 1052, both of which have a control terminal and a first terminal.

[0037] The control terminal of the third feedback unit 1051 is connected to the first output terminal of the second sampling circuit 102, and the first terminal of the third feedback unit 1051 is connected to the second output terminal of the second sampling circuit 102. The control terminal of the fourth feedback unit 1052 is connected to the second output terminal of the second sampling circuit 102, and the first terminal of the fourth feedback unit 1052 is connected to the first output terminal of the second sampling circuit 102.

[0038] The third feedback unit 1051 is used to pull the voltage of the second output terminal of the second sampling circuit 102 according to the voltage of the first output terminal of the second sampling circuit 102, and the fourth feedback unit 1052 is used to pull the voltage of the first output terminal of the second sampling circuit 102 according to the voltage of the second output terminal of the second sampling circuit 102.

[0039] The third feedback unit 1051 pulls the voltage at the second output terminal of the second sampling circuit 102 in the same direction as the fourth feedback unit 1052 pulls the voltage at the first output terminal of the second sampling circuit 102. When the third feedback unit 1051 pulls the voltage at the second output terminal of the second sampling circuit 102 upwards, the fourth feedback unit 1052 also pulls the voltage at the first output terminal of the second sampling circuit 102 upwards. When the third feedback unit 1051 pulls the voltage at the second output terminal of the second sampling circuit 102 downwards, the fourth feedback unit 1052 also pulls the voltage at the first output terminal of the second sampling circuit 102 downwards.

[0040] The following example illustrates the effect of pulling down the voltage of the two output terminals of the first sampling circuit 101: When the voltage of the first output terminal of the first sampling circuit 101 is higher than the voltage of the second output terminal of the first sampling circuit 101, the first feedback unit 1041 has a stronger ability to pull down the voltage of the second output terminal of the first sampling circuit 101, while the second feedback unit 1042 has a weaker ability to pull down the voltage of the first output terminal of the first sampling circuit 101. In other words, the voltage drop rate of the first output terminal is lower than that of the second output terminal, which in turn makes the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0041] When the voltage at the first output terminal of the first sampling circuit 101 is lower than the voltage at the second output terminal of the first sampling circuit 101, the first feedback unit 1041 has a weaker ability to pull down the voltage at the second output terminal of the first sampling circuit 101, while the second feedback unit 1042 has a stronger ability to pull down the voltage at the first output terminal of the first sampling circuit 101. In other words, the voltage drop rate at the first output terminal is higher than the voltage drop rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0042] The following example illustrates the effect of pulling up the voltage of the two output terminals of the first sampling circuit 101: When the voltage of the first output terminal of the first sampling circuit 101 is higher than the voltage of the second output terminal of the first sampling circuit 101, the first feedback unit 1041 has a weaker ability to pull up the voltage of the second output terminal of the first sampling circuit 101, while the second feedback unit 1042 has a stronger ability to pull up the voltage of the first output terminal of the first sampling circuit 101. In other words, the voltage rise rate of the first output terminal is higher than the voltage rise rate of the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0043] When the voltage at the first output terminal of the first sampling circuit 101 is lower than the voltage at the second output terminal of the first sampling circuit 101, the first feedback unit 1041 has a stronger ability to pull up the voltage at the second output terminal of the first sampling circuit 101, while the second feedback unit 1042 has a weaker ability to pull up the voltage at the first output terminal of the first sampling circuit 101. In other words, the voltage rise rate at the first output terminal is lower than the voltage rise rate at the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0044] In the above technical solution, when any one or both of the first reference signal and the second reference signal are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through the positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortens the sampling stage time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0045] In the above technical solution, the comparator includes a first sampling circuit 101, a second sampling circuit 102, and an output circuit 103. The first sampling circuit 101 is used to generate a first differential signal based on the signal to be compared and a first reference signal. The second sampling circuit 102 is used to generate a second differential signal based on the signal to be compared and the second reference signal. The first sampling circuit 101 or the second sampling circuit 102 is controlled to perform sampling according to the condition of the signal to be compared being affected, so as to ensure that the polarity of the differential signal generated before the signal to be compared is affected and the polarity of the differential signal generated after the signal to be compared is affected are the same, so that the output circuit 103 can output a more accurate comparison result, thereby eliminating inter-symbol interference.

[0046] like Figure 2 As shown, one embodiment of this application provides a comparator, which includes six input terminals and two output terminals. The comparator includes a first sampling circuit 101, a second sampling circuit 102, and an output circuit 103. The first sampling circuit 101 is further provided with a first sampling unit 1011 and a first control unit 1012, and the second sampling circuit 102 is further provided with a second sampling unit 1021 and a second control unit 1022.

[0047] The first sampling unit 1011 has two input terminals: a first input terminal and a second input terminal. The first sampling unit 1011 also has two output terminals: a first output terminal and a second output terminal. The second sampling unit 1021 has two input terminals: a first input terminal and a second input terminal. The second sampling unit 1021 also has two output terminals: a first output terminal and a second output terminal. The first control unit 1012 has two input terminals: a first input terminal and a second input terminal. The second control unit 1022 also has two input terminals: a first input terminal and a second input terminal.

[0048] The first input terminal of the first sampling unit 1011 serves as the first input terminal of the comparator, used for the first reference signal VREFP. The second input terminals of both the second sampling unit 1021 and the first sampling unit 1011 serve as the second input terminals of the comparator, used to receive the signal to be compared, DQ. The first input terminal of the second sampling unit 1021 serves as the third input terminal of the comparator, used for the second reference signal VREFN. The first input terminal of the first control unit 1012 serves as the fourth input terminal of the comparator, used to receive the first control signal D270. The first input terminal of the second control unit 1022 serves as the fifth input terminal of the comparator, used to receive the second control signal D270B. The second input terminals of both the first control unit 1012 and the second control unit 1022 serve as the sixth input terminals of the comparator, used to receive the clock signal CLK.

[0049] The output terminals of the output circuit 103 include a first output terminal and a second output terminal. The first output terminal of the output circuit 103 serves as the first output terminal of the comparator, and the second output terminal of the output circuit 103 serves as the second output terminal of the comparator.

[0050] The first sampling unit 1011 includes a first input transistor N1, a second input transistor N2, and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the first sampling unit 1011, used to receive a first reference signal VREFP. The first terminal of the first input transistor N1 serves as the first output terminal of the first sampling unit 1011. The control terminal of the second input transistor N2 serves as the second input terminal of the first sampling unit 1011, used to receive a signal to be compared, DQ. The first terminal of the second input transistor N2 serves as the second output terminal of the first sampling unit 1011. The control terminal of the third input transistor N3 serves as the control terminal of the first sampling unit 1011, used to connect to the output terminal of the first control unit 1012. The first terminal of the third input transistor N3 is connected to the second terminals of the first input transistor N1 and the second terminals of the second input transistor N2, and the second terminal of the third input transistor N3 is connected to ground.

[0051] In the above technical solution, the first sampling unit 1011 includes three transistors. Two transistors are used to receive the first reference signal VREFP and the signal to be compared DQ. The control terminal of the other transistor serves as a sampling unit, so that the first control unit 1012 controls the working mode of the first sampling unit 1011 through the control terminal of the transistor of the first sampling unit 1011. The first control unit 1012 can control the working mode of the first sampling unit 1011 according to the influence of the signal to be compared DQ, so as to ensure that the polarity of the differential signal generated by the signal to be compared DQ before it is affected is the same as the polarity of the differential signal generated by the signal to be compared DQ after it is affected, so that the output circuit 103 can output a more accurate comparison result.

[0052] The first control unit 1012 includes a first AND gate circuit, which has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first AND gate circuit serves as the first input terminal of the first control unit 1012, used to receive the first control signal D270. The second input terminal of the first AND gate circuit serves as the second input terminal of the first control unit 1012, used to receive the clock signal CLK. The output terminal of the first AND gate circuit serves as the output terminal of the first control unit 1012, used to connect to the control terminal of the first sampling unit 1011.

[0053] In the above technical solution, the first control unit 1012 includes a first AND gate circuit, which performs an AND operation on the first control signal D270 and the clock signal CLK and outputs the calculation result DSEL. The calculation result DSEL is used to control the working mode of the first sampling unit 1011, thereby realizing the control of the working mode of the first sampling unit 1011 according to the first control signal D270 and the clock signal CLK.

[0054] The second sampling unit 1021 includes a fourth input transistor N4, a fifth input transistor N5, and a sixth input transistor N6. The control terminal of the fourth input transistor N4 serves as the first input terminal of the second sampling unit 1021, used to receive the second reference signal VREFN. The first terminal of the fourth input transistor N4 serves as the first output terminal of the second sampling unit 1021. The control terminal of the fifth input transistor N5 serves as the second input terminal of the second sampling unit 1021, used to receive the signal to be compared DQ. The first terminal of the fifth input transistor N5 serves as the second output terminal of the second sampling unit 1021. The control terminal of the sixth input transistor N6 serves as the control terminal of the second sampling unit 1021, used to connect to the output terminal of the second control unit 1022. The first terminal of the sixth input transistor N6 is connected to the second terminals of the fourth input transistor N4 and the fifth input transistor N5, and the second terminal of the sixth input transistor N6 is connected to ground.

[0055] The second control unit 1022 includes a second AND gate circuit, which has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second AND gate circuit serves as the first input terminal of the second control unit 1022, used to receive the second control signal D270B. The second input terminal of the second AND gate circuit serves as the second input terminal of the second control unit 1022, used to receive the clock signal CLK. The output terminal of the second AND gate circuit serves as the output terminal of the second control unit 1022, used to connect to the control terminal of the second sampling unit 1021.

[0056] In the above technical solution, the second control unit 1022 includes a second AND gate circuit, which performs an AND operation on the second control signal D270B and the clock signal CLK and outputs the calculation result DSELB. The calculation result DSELB is used to control the working mode of the second sampling unit 1011, thereby realizing the control of the working mode of the second sampling unit 1011 according to the second control signal D270B and the clock signal CLK.

[0057] The first control signal D270 and the second control signal D270B are an inverted pair of signals. That is, when the first control signal D270 is high, the second control signal D270B is low, and vice versa. This controls either the first sampling unit 101 or the second sampling unit 102 to operate in sampling mode.

[0058] In one embodiment, the first input transistor N1 to the sixth input transistor N6 are all of the same type. When the first input transistor N1 to the sixth input transistor N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0059] When the signal to be compared, DQ, is affected and its amplitude increases, the first control signal is high and the second control signal is low. When the clock signal CLK arrives, the first AND gate outputs a high level, the second AND gate outputs a low level, the third input transistor N3 is turned on, and the sixth input transistor N6 is turned off. The first sampling unit 1011 operates in sampling mode, and the second sampling unit 1021 operates in idle mode, that is, the second sampling unit 1021 stops sampling. When the first sampling unit 1011 operates in sampling mode, the first reference signal VREFP pulls the drain voltage of the first input transistor N1, and the signal to be compared, DQ, pulls the drain voltage of the second input transistor N2. When the amplitudes of the first reference signal VREFP and the signal to be compared, DQ, are different, their pulling capabilities on the transistors are also different, generating a first differential signal at the drain of the first input transistor N1 and the drain of the second input transistor N2. For example, when the signal to be compared, DQ, is affected and its amplitude increases, since a first reference signal VREFP with a larger amplitude is selected, it can still be guaranteed that when the first reference signal VREFP is greater than the signal to be compared, DQ, the drain voltage of the first input transistor N1 is greater than the drain voltage of the second input transistor N2. This ensures that the polarity of the differential signal generated by the signal to be compared before it is affected is the same as the polarity of the differential signal generated by the signal to be compared after it is affected.

[0060] When the amplitude of the signal to be compared, DQ, is affected and becomes smaller, the first control signal is low and the second control signal is high. When the clock signal CLK arrives, the first AND gate outputs a low level, the second AND gate outputs a high level, the third input transistor N3 is cut off, and the sixth input transistor N6 is turned on. The first sampling unit 1011 operates in idle mode, and the second sampling unit 1021 operates in sampling mode. When the second sampling unit 1021 operates in sampling mode, the second reference signal VREFN pulls the drain voltage of the fourth input transistor N4, and the signal to be compared, DQ, pulls the drain voltage of the fifth input transistor N5. When the amplitudes of the second reference signal VREFN and the signal to be compared, DQ, are different, their pulling capabilities on the transistors are also different, generating a second differential signal at the drain of the fourth input transistor N4 and the drain of the fifth input transistor N5. For example, when the signal to be compared, DQ, is affected and its amplitude decreases, the second reference signal, VREFN, with a smaller amplitude, is still selected. This ensures that the second reference signal VREFN is less than the signal to be compared, DQ, and the drain voltage of the fourth input transistor N4 is less than the drain voltage of the fifth input transistor N5. This ensures that the polarity of the differential signal generated by the signal to be compared before it is affected is the same as the polarity of the differential signal generated by the signal to be compared after it is affected.

[0061] In one embodiment, the first control signal and the second control signal are determined based on the trend of the influence on the signal to be compared, DQ. When the trend of the influence on the signal to be compared, DQ, is increasing, the first control signal is high and the second control signal is low. When the trend of the influence on the signal to be compared, DQ, is decreasing, the first control signal is low and the second control signal is high.

[0062] In one embodiment, the first feedback unit 1041 includes a first feedback transistor N11. The control terminal of the first feedback transistor N11 is connected to the first terminal of the first input transistor N1, and the first terminal of the first feedback transistor N11 is connected to the first terminal of the second input transistor N2. The second terminal of the first feedback transistor N11 is connected to the second terminal of the second input transistor N2.

[0063] The second feedback unit 1042 includes a second feedback transistor N12. The control terminal of the second feedback transistor N12 is connected to the first terminal of the second input transistor N2. The first terminal of the second feedback transistor N12 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N12 is connected to the second terminal of the first input transistor N1.

[0064] In one embodiment, the first feedback transistor N11, the second feedback transistor N12, the first input transistor N1, and the second input transistor N2 are of the same type, ensuring that the direction of the voltage at the second output terminal of the first sampling circuit 101 pulled by the first feedback transistor N11 is the same as the direction of the voltage at the first output terminal of the first sampling circuit 101 pulled by the second feedback transistor N12. It is also ensured that the direction of the voltage at the output terminal of the first sampling circuit 101 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the first sampling circuit 101 pulled by the input transistor, thereby achieving positive feedback.

[0065] The greater the voltage at the first terminal of the first input transistor N1, the greater the ability of the first feedback transistor N11 to pull down the voltage at the first terminal of the second input transistor N2, and the faster the voltage at the first terminal of the second input transistor N2 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the first input transistor N1 and the second input transistor N2.

[0066] In one embodiment, the third feedback unit 1051 includes a third feedback transistor N13. The control terminal of the third feedback transistor N13 is connected to the first terminal of the fourth input transistor N4, and the first terminal of the third feedback transistor N13 is connected to the first terminal of the fifth input transistor N5. The second terminal of the third feedback transistor N13 is connected to the second terminal of the fifth input transistor N5.

[0067] The fourth feedback unit 1052 includes a fourth feedback transistor N14. The control terminal of the fourth feedback transistor N14 is connected to the first terminal of the fifth input transistor N5. The first terminal of the fourth feedback transistor N14 is connected to the first terminal of the fourth input transistor N4. The second terminal of the fourth feedback transistor N14 is connected to the second terminal of the fourth input transistor N4.

[0068] In one embodiment, the third feedback transistor N13, the fourth feedback transistor N14, the fourth input transistor N4, and the fifth input transistor N5 are of the same type, ensuring that the direction of the voltage at the second output terminal of the second sampling circuit 102 pulled by the third feedback transistor N13 is the same as the direction of the voltage at the first output terminal of the second sampling circuit 102 pulled by the fourth feedback transistor N14. It is also ensured that the direction of the voltage at the output terminal of the second sampling circuit 102 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the second sampling circuit 102 pulled by the input transistor, thereby achieving positive feedback.

[0069] The greater the voltage at the first terminal of the fourth input transistor N4, the greater the ability of the third feedback transistor N13 to pull down the voltage at the first terminal of the fifth input transistor N5, and the faster the voltage at the first terminal of the fifth input transistor N5 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the fourth input transistor N4 and the fifth input transistor N5.

[0070] In one embodiment, the first feedback transistors N11 to N14 and the first input transistors N1 to N6 are of the same type. If the first feedback transistors N11 to N14 and the first input transistors N1 to N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0071] The output circuit 103 includes a first output transistor N7, a second output transistor N8, a third output transistor N9, a fourth output transistor N10, a fifth output transistor P3, a sixth output transistor P4, and a seventh output transistor P5. The input terminals of the output circuit 103 include a first input terminal and a second input terminal, and the output terminals of the output circuit 103 include a first output terminal and a second output terminal.

[0072] The control terminal of the first output transistor N7 is the first input terminal of the output circuit 103, and is used to connect to the first output terminal of the first sampling unit 1011. The first terminal of the first output transistor N7 is the first output terminal of the output circuit 103, and the second terminal of the first output transistor N7 is connected to the ground terminal. The control terminal of the second output transistor N8 is the second input terminal of the output circuit 103, and is used to connect to the second output terminal of the first sampling unit 1011. The first terminal of the second output transistor N8 is the second output terminal of the output circuit 103, and the second terminal of the second output transistor N8 is connected to the ground terminal.

[0073] The first terminal of the third output transistor N9 is connected to the first terminal of the first output transistor N7, and the second terminal of the third output transistor N9 is connected to the second terminal of the first output transistor N7. The control terminal of the third output transistor N9 is connected to the first terminal of the fourth output transistor N10. The first terminal of the fourth output transistor N10 is connected to the first terminal of the second output transistor N8, and the second terminal of the fourth output transistor N10 is connected to the second terminal of the second output transistor N8. The control terminal of the fourth output transistor N10 is connected to the first terminal of the third output transistor N9. The second terminal of the fifth output transistor P3 is connected to the first terminal of the third output transistor N9, and the control terminal of the fifth output transistor P3 is connected to the first terminal of the fourth output transistor N10. The second terminal of the sixth output transistor P4 is connected to the first terminal of the fourth output transistor N10, and the control terminal of the sixth output transistor P4 is connected to the first terminal of the third output transistor N9.

[0074] The control terminal of the seventh output transistor P5 is used to receive the clock signal CLK. The first terminal of the seventh output transistor P5 is connected to the power supply terminal. The second terminal of the seventh output transistor P5 is connected to the first terminal of the fifth output transistor P3 and the first terminal of the sixth output transistor P4.

[0075] In one embodiment, the first output transistor N7 to the fourth output transistor N10 are all N-type transistors, and the fifth output transistor P3 to the seventh output transistor P5 are all P-type transistors. The drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. The source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0076] When a pulse arrives in the clock signal CLK, the inverted clock signal CLKB is input to the seventh output transistor P5, causing P5 to conduct. The output circuit 103 amplifies and latches the voltage signal at the output of the first sampling circuit 101 or the voltage signal at the output of the second sampling circuit 102, and outputs the comparison result. Taking the first sampling circuit 101 sampling while the second sampling circuit 102 stops sampling as an example, the control terminal of the first output transistor N7 receives one signal from the first differential signal, and the control terminal of the second output transistor N8 receives the other signal from the first differential signal. After being amplified by the first output transistor N7 and the second output transistor N8, the two differential signals are input to the control terminals of the third output transistor N9 to the sixth output transistor P4. After being amplified and latched again by the third output transistor N9 to the sixth output transistor P4, the comparison result is output.

[0077] After the drain voltages of the first output transistor N7 and the second output transistor N8 are amplified and latched by the third output transistor N9 to the sixth output transistor P4, there are two possible drain voltages for the first output transistor N7 and the second output transistor N8. In the first case, the drain voltage P0B of the first output transistor N7 is high, and the drain voltage P0 of the second output transistor N8 is low, represented by the digital "0". In the second case, the drain voltage P0B of the first output transistor N7 is low, and the drain voltage P0 of the second output transistor N8 is high, represented by the digital "1".

[0078] In the above technical solution, the first differential signal or the second differential signal is amplified by two transistors and then amplified and latched by four transistors, which can further improve the accuracy of the output result.

[0079] In one embodiment, the comparator further includes a reset circuit 06, which is connected to the first sampling circuit 101 and the second sampling circuit 102. The reset circuit 06 is used to reset the voltage of the first sampling circuit 101 before the first sampling circuit 101 enters the sampling working mode, and also to reset the voltage of the second sampling circuit 102 before the second sampling circuit 102 enters the sampling working mode.

[0080] In the above technical solution, the output voltages of the first sampling circuit 101 and the second sampling circuit 102 are reset by the reset circuit 06, which can quickly reset the output voltages of the two sampling units, thereby improving the response rate of the comparator.

[0081] In one embodiment, the reset circuit 06 includes a first clocked transistor P1 and a second clocked transistor P2. The control terminal of the first clocked transistor P1 receives a clock signal CLK. The first terminal of the first clocked transistor P1 is connected to a power supply terminal, and the second terminal of the first clocked transistor P1 is connected to the first terminal of the first input transistor N1 and the first terminal of the fourth input transistor N4. The control terminal of the second clocked transistor P2 receives the clock signal CLK. The first terminal of the second clocked transistor P2 is connected to a power supply terminal, and the second terminal of the second clocked transistor P2 is connected to the first terminal of the second input transistor N2 and the first terminal of the fifth input transistor N5.

[0082] In one embodiment, the first clocked transistor P1 and the second clocked transistor P2 are P-type transistors, with the source of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal.

[0083] Before the pulse arrives in the clock signal CLK, the control terminals of the first clock transistor P1 and the second clock transistor P2 receive a low level signal, and the first clock transistor P1 and the second clock transistor P2 are turned on. The first clock transistor P1 pulls the drain voltage of the first input transistor N1 and the drain voltage of the fourth input transistor N4 to the voltage of the power supply terminal, and the second clock transistor P2 pulls the drain voltage of the second input transistor N2 and the drain voltage of the fifth input transistor N5 to the voltage of the power supply terminal.

[0084] In the above technical solution, two AND gate circuits generate signals to control the working modes of the two sampling units based on the control signal and the clock signal CLK. When the influence trend of the signal to be compared, DQ, is decreasing, the first sampling unit 1011 is controlled to work in sampling mode. When the influence trend of the signal to be compared, DQ, is increasing, the second sampling unit 1021 is controlled to work in sampling mode. This ensures that the polarity of the differential signal generated by the signal to be compared, DQ, before being affected is the same as the polarity of the differential signal generated by the signal to be compared, DQ, after being affected. This allows the output circuit 103 to accurately output the comparison result based on the differential signal, eliminating inter-symbol interference.

[0085] like Figure 3 As shown, one embodiment of this application provides a comparator, which includes a first sampling circuit 101, a second sampling circuit 102, an output circuit 103, a first positive feedback circuit 104, and a second positive feedback circuit 105. The first sampling circuit 101 further includes a first sampling unit 1011 and a first control unit 1012, and the second sampling circuit 102 further includes a second sampling unit 1021 and a second control unit 1022. The first positive feedback circuit 104 includes a first feedback unit 1041 and a second positive feedback circuit 1042. The second positive feedback circuit 105 includes a third feedback unit 1051 and a fourth positive feedback circuit 1052.

[0086] The first sampling unit 1011 includes a first input transistor P1, a second input transistor P2, and a third input transistor P3. The connection relationship of each transistor in the first sampling unit 1011 is as follows: Figure 2 The same applies as shown, and will not be repeated here. The second sampling unit 1021 includes a fourth input transistor P4, a fifth input transistor P5, and a sixth input transistor P6.

[0087] The connection relationship of each transistor in the second sampling unit 1021 is the same as that in the second sampling unit 1021. Figure 2 The same applies as shown, and will not be repeated here. The first feedback unit 1041 includes a first feedback transistor P11, the second feedback unit includes a second feedback transistor P12, the third feedback unit 1051 includes a third feedback transistor P13, and the fourth feedback unit 1052 includes a fourth feedback transistor P14. The connection relationship of each transistor in the first feedback unit 1041 to the fourth feedback unit 1052 is the same as... Figure 2 The same configuration is shown below, and will not be repeated here. Output circuit 103 includes a first output transistor P7, a second output transistor P8, a third output transistor P9, a fourth output transistor P10, a fifth output transistor N3, a sixth output transistor N4, and a seventh output transistor N5. The connection relationship of each transistor in output circuit 103 is the same as... Figure 2 The same applies as shown, so it will not be repeated here.

[0088] It should be noted here that when the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. The first output transistor P7 to the fourth output transistor P10 are all P-type transistors, and the fifth output transistor N3 to the seventh output transistor N5 are all N-type transistors. In the latter case, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0089] It should also be noted that the second terminal of the third input transistor P3 and the second terminal of the sixth input transistor P6 are connected to the power supply terminal, and the first terminal of the seventh output transistor N5 is connected to the ground terminal.

[0090] The working principles of the first control unit 1012 and the second control unit 1022 are described below:

[0091] When the signal to be compared, DQ, is affected and its amplitude increases, the first control signal D270B is low and the second control signal D270 is high. When the clock signal CLK arrives, the first AND gate outputs a low level, the third input transistor N3 is turned on, the second AND gate outputs a high level, and the sixth input transistor N6 is turned off. The first sampling unit 1011 operates in sampling mode, the first feedback unit 1041 and the second feedback unit 1042 are used to accelerate the generation of the first differential signal, and the second sampling unit 1021 operates in idle mode.

[0092] When the signal to be compared, DQ, is affected and its amplitude decreases, the first control signal D270B goes high and the second control signal D270 goes low. When the clock signal CLK arrives, the first AND gate outputs a high level, the third input transistor N3 is cut off, the second AND gate outputs a low level, and the sixth input transistor N6 is turned on. The first sampling unit 1011 operates in sampling mode, the second sampling unit 1021 operates in idle mode, and the third feedback unit 1051 and the fourth feedback unit 1052 are used to accelerate the generation of the second differential signal.

[0093] In one embodiment, the comparator further includes a reset circuit 06, which includes a first clocked transistor P1 and a second clocked transistor P2. The transistors in the reset circuit 06 are connected in the same manner as... Figure 2 The same applies here, so it will not be repeated. The first clocked transistor P1 and the second clocked transistor P2 are N-type transistors. The source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. It should also be noted that the first terminals of the first clocked transistor P1 and the second clocked transistor P2 are connected to ground.

[0094] Before the arrival of the pulse in the clock signal, the inverted clock signal CLKB is input to the first clock transistor P1 and the second clock transistor P2 to pull the first terminals of the first input transistor N1, the second input transistor N2, the fourth input transistor N4 and the fifth input transistor N5 to a low level, thereby resetting the first sampling circuit 101 and the second sampling circuit 102.

[0095] like Figure 4 As shown, one embodiment of this application provides a decision feedback equalization circuit, which includes four comparators. Each comparator has six input terminals and two output terminals. The four comparators are sequentially labeled as first comparator 100, second comparator 200, third comparator 300, and fourth comparator 400.

[0096] The first input terminal of the first comparator 100 is used to receive the signal to be compared, DQ. The second input terminal of the first comparator 100 is used to receive the first reference signal, VREFP. The third input terminal of the first comparator 100 is used to receive the second reference signal, VREFN. The fourth and fifth input terminals of the first comparator 100 are connected to the output terminal of the fourth comparator 400 and are used to receive the first control signal and the second control signal. The sixth input terminal of the first comparator 100 is used to receive the first clock signal, CLK_0.

[0097] The first input terminal of the second comparator 200 is used to receive the signal to be compared, DQ. The second input terminal of the second comparator 200 is used to receive the first reference signal, VREFP. The third input terminal of the second comparator 200 is used to receive the second reference signal, VREFN. The fourth and fifth input terminals of the second comparator 200 are connected to the output terminal of the first comparator 100 and are used to receive the first control signal and the second control signal. The sixth input terminal of the second comparator 200 is used to receive the second clock signal, CLK_90.

[0098] The third comparator 300 has the following characteristics: its first input terminal is used to receive the signal to be compared, DQ; its second input terminal is used to receive the first reference signal, VREFP; its third input terminal is used to receive the second reference signal, VREFN; its fourth and fifth input terminals are connected to the output terminal of the second comparator 200 and are used to receive the first control signal and the second control signal; and its sixth input terminal is used to receive the third clock signal, CLK_180.

[0099] The fourth comparator 400 has the following characteristics: its first input terminal is used to receive the signal to be compared, DQ; its second input terminal is used to receive the first reference signal, VREFP; its third input terminal is used to receive the second reference signal, VREFN; its fourth and fifth input terminals are connected to the output terminal of the third comparator 300 to receive the first control signal and the second control signal; and its sixth input terminal is used to receive the fourth clock signal, CLK_D270.

[0100] In one embodiment, the comparator in the decision equalization circuit has the following structure: Figure 2 In the structure shown, the fifth input terminal of the first comparator 100 is connected to the second output terminal of the fourth comparator 400, and the sixth input terminal of the first comparator 100 is connected to the first output terminal of the fourth comparator 400.

[0101] In one embodiment, the comparator in the decision equalization circuit has the following structure: Figure 3In the structure shown, the fifth input terminal of the first comparator 100 is connected to the first output terminal of the fourth comparator 400, and the sixth input terminal of the first comparator 100 is connected to the second output terminal of the fourth comparator 400.

[0102] The working principle of the decision feedback equalization circuit is described below: When the first output signal P270B of the fourth comparator 400 is low and the second output signal P270 is high, that is, when the result of the comparator is the number "1", it means that the signal to be compared received by the fourth comparator 400 is relatively large. The trend of its influence on the signal to be compared received by the first comparator 100 is to make the signal to be compared DQ larger. The first comparator 100 generates a first differential signal based on the signal to be compared DQ and the first reference signal VREFP with a relatively large value, and generates a comparison result based on the first differential signal.

[0103] When the first output signal P270B of the fourth comparator 400 is high and the second output signal P270 is low, meaning the comparator result is "0", it indicates that the signal DQ to be compared received by the fourth comparator 400 is relatively small. Therefore, the trend of its influence on the signal DQ to be compared received by the first comparator 100 is to make the signal DQ to be compared smaller. The first comparator 100 then generates a second differential signal based on the signal DQ to be compared and the second reference signal VREFN with a relatively small value, and generates a comparison result based on the second differential signal.

[0104] The working principle of the second comparator 200 to the fourth comparator 400 is the same as that of the first comparator 100, and will not be repeated here.

[0105] In one embodiment, the phase of the first clock signal CLK_0 is 90° earlier than the phase of the second clock signal CLK_90, the phase of the first clock signal CLK_0 is 180° earlier than the phase of the third clock signal CLK_180, and the phase of the first clock signal CLK_0 is 270° earlier than the phase of the fourth clock signal CLK_D270.

[0106] In one embodiment, the voltage switching time at the output terminals of the first comparator 100 to the fourth comparator 400 is less than the time interval between the first clock signal CLK_0 and the second clock signal CLK_90. When the switching time of the output voltage of the fourth comparator 400 is less than 1UI, where 1UI represents the time interval between the first clock signal CLK_0 and the second clock signal CLK_90, it can be ensured that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, thereby allowing the first comparator 100 to eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0107] In one embodiment, the decision feedback equalization circuit further includes a first register 500, a second register 600, a third register 700, and a fourth register 800. The input of the first register 500 is connected to the output of the first comparator 100, and the first register 500 stores the comparison result generated by the first comparator 100. The input of the second register 600 is connected to the output of the second comparator 200, and the second register 600 stores the comparison result generated by the second comparator 200. The input of the third register 700 is connected to the output of the third comparator 300, and the third register 700 stores the comparison result generated by the third comparator 300. The input of the fourth register 800 is connected to the output of the fourth comparator 400.

[0108] like Figure 5 As shown, taking the first comparator 100 as an example, the signal timing is explained. When the clock signal arrives, the signal to be compared, DQ, and the output signals of the two AND gate circuits also arrive. After being processed by the first comparator 100, the output signal is output through the output terminal of the comparator to show the comparison result. Then, the first register 500 saves the data.

[0109] In the above technical solution, by cascading four comparators together, that is, connecting the output of the previous comparator to the input of the current comparator, the sampling circuit in the current comparator is controlled by the output of the previous comparator, so as to eliminate the influence of the previous signal to be compared DQ on the current signal to be compared DQ, thereby improving the accuracy of the comparator comparison result. After storing the comparison result in four registers, the data D0, D90, D180 and D270 are output, which can realize the continuous output of multiple comparison results.

[0110] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0111] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A comparator, characterized in that, include: A first sampling circuit, having an output terminal, is used to generate a first differential signal based on a signal to be compared and a first reference signal under the control of a first control signal and a clock signal. The first sampling circuit includes a first sampling unit and a first control unit. The first sampling unit has a control terminal, used to generate the first differential signal based on the signal to be compared and the first reference signal when operating in sampling mode. The output terminal of the first control unit is connected to the control terminal of the first sampling unit, used to control the operating mode of the first sampling unit according to the first control signal and the clock signal. The operating mode includes the sampling mode. The first control unit specifically includes a first AND gate circuit, whose first input terminal is used to receive the first control signal, whose second input terminal is used to receive the clock signal, and whose output terminal serves as the output terminal of the first control unit. A first positive feedback circuit is connected to the output of the first sampling circuit and is used to accelerate the difference between the first differential signals. A second sampling circuit, having an output terminal connected to the output terminal of the first sampling circuit, is used to generate a second differential signal based on the signal to be compared and a second reference signal under the control of a second control signal and a clock signal. The first reference signal is greater than the second reference signal. The second sampling circuit includes a second sampling unit and a second control unit. The second sampling unit has a control terminal for generating the second differential signal based on the signal to be compared and the second reference signal when operating in sampling mode. The output terminal of the second control unit is connected to the control terminal of the second sampling unit for controlling the operating mode of the second sampling unit based on the second control signal and the clock signal. The operating mode includes the sampling mode. The second control unit specifically includes a second AND gate circuit, whose first input terminal receives the second control signal, whose second input terminal receives the clock signal, and whose output terminal serves as the output terminal of the second control unit. The first and second control signals are determined based on the trend of the signal to be compared being affected. When the trend of the signal to be compared being affected is increasing, the first control signal is high and the second control signal is low; when the trend of the signal to be compared being affected is decreasing, the first control signal is low and the second control signal is high. The second positive feedback circuit is connected to the output of the second sampling circuit and is used to accelerate the difference between the second differential signals. The output circuit has an input terminal connected to the output terminal of the first sampling circuit. When the signal to be compared is subjected to increased inter-symbol interference, it amplifies and latches the voltage signal at the output terminal of the first sampling circuit and outputs the comparison result. When the signal to be compared is subjected to decreased inter-symbol interference, it amplifies and latches the voltage signal at the output terminal of the second sampling circuit and outputs the comparison result.

2. The comparator according to claim 1, characterized in that, The first positive feedback circuit includes: The first feedback unit has its control terminal connected to the first output terminal of the first sampling circuit, and its first terminal connected to the second output terminal of the first sampling circuit. The second feedback unit has its control terminal connected to the second output terminal of the first sampling circuit, and its first terminal connected to the first output terminal of the first sampling circuit. The second positive feedback circuit includes: The third feedback unit has its control terminal connected to the first output terminal of the second sampling circuit, and its first terminal connected to the second output terminal of the second sampling circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the second sampling circuit, and its first terminal connected to the first output terminal of the second sampling circuit.

3. The comparator according to claim 2, characterized in that, The first feedback unit includes: a first feedback transistor, whose control terminal is the control terminal of the first feedback unit, and whose first terminal is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, whose control terminal is the control terminal of the second feedback unit, and whose first terminal is the first terminal of the second feedback unit; The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

4. The comparator according to claim 3, characterized in that, The first sampling unit includes: The first input transistor has a control terminal for receiving the first reference signal, a first terminal for serving as the first output terminal of the first sampling unit, and a first terminal for being connected to the first terminal of the second feedback transistor. The second input transistor has a control terminal for receiving the signal to be compared, and its first terminal serves as the second output terminal of the first sampling unit. Its first terminal is connected to the first terminal of the first feedback transistor. The third input transistor has its control terminal serving as the control terminal of the first sampling unit. Its first terminal is connected to the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor, and the second terminal of the second feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

5. The comparator according to claim 3, characterized in that, The second sampling unit includes: The fourth input transistor has a control terminal for receiving the signal to be compared, and its first terminal serves as the first output terminal of the second sampling unit. Its first terminal is connected to the first terminal of the fourth feedback transistor. The fifth input transistor has a control terminal for receiving the second reference signal, a first terminal for serving as the second output terminal of the second sampling unit, and a first terminal connected to the first terminal of the third feedback transistor. The sixth input transistor has its control terminal as the control terminal of the second sampling unit. Its first terminal is connected to the second terminal of the fourth input transistor, the second terminal of the fifth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

6. The comparator according to claim 3, characterized in that, The first feedback transistor to the fourth feedback transistor, and the first input transistor to the sixth input transistor are all of the same type.

7. The comparator according to claim 6, characterized in that, When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal; When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal.

8. The comparator according to claim 1, characterized in that, The output circuit includes: The first output transistor has a control terminal that is the first input terminal of the output circuit, a first terminal that is the first output terminal of the output circuit, and a second terminal that is connected to ground or power supply. The second output transistor has a control terminal that is the second input terminal of the output circuit, a first terminal that is the second output terminal of the output circuit, and a second terminal that is connected to ground or power supply. The third output transistor has its first terminal connected to the first terminal of the first output transistor and its second terminal connected to the second terminal of the first output transistor. The fourth output transistor has its first terminal connected to the first terminal of the second output transistor and its second terminal connected to the second terminal of the second output transistor. The fifth output transistor has its second terminal connected to the first terminal of the third output transistor, its control terminal connected to the control terminal of the third output transistor, and its control terminal also connected to the first terminal of the fourth output transistor. The sixth output transistor has its second terminal connected to the first terminal of the fourth output transistor, its control terminal connected to the control terminal of the fourth output transistor, and its control terminal also connected to the first terminal of the third output transistor. The seventh output transistor has a control terminal for receiving the clock signal, a first terminal connected to a power supply terminal or a ground terminal, and a second terminal connected to the first terminal of the fifth output transistor and the first terminal of the sixth output transistor.

9. The comparator according to claim 8, characterized in that, The first to the fourth output transistors are all N-type transistors, and the fifth to the seventh output transistors are all P-type transistors; wherein, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. or The first to the fourth output transistors are all P-type transistors, and the fifth to the seventh output transistors are all N-type transistors; wherein, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

10. The comparator according to claim 1, characterized in that, The comparator further includes: A reset circuit, which is connected to the first sampling circuit and the second sampling circuit, is used to reset the voltages of the first sampling circuit and the second sampling circuit.

11. The comparator according to claim 10, characterized in that, The reset circuit includes: The first clock-controlled transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the first input transistor and the first terminal of the fourth input transistor. The second clock transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the second input transistor and the first terminal of the fifth input transistor.

12. A decision feedback equalization circuit, characterized in that, It includes four comparators as described in any one of claims 1 to 9, which are sequentially labeled as a first comparator, a second comparator, a third comparator, and a fourth comparator; The first comparator has a first input terminal for receiving a signal to be compared, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, a fourth and a fifth input terminal connected to the output terminal of the fourth comparator for receiving a first control signal and a second control signal, and a sixth input terminal for receiving a first clock signal. The second comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, a fourth and a fifth input terminal connected to the output terminal of the first comparator for receiving the first control signal and the second control signal, and a sixth input terminal for receiving the second clock signal. The third comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, a fourth and a fifth input terminal connected to the output terminal of the second comparator for receiving the first control signal and the second control signal, and a sixth input terminal for receiving the third clock signal. The fourth comparator has a first input terminal for receiving the signal to be compared, a second input terminal for receiving the first reference signal, a third input terminal for receiving the second reference signal, and its fourth and fifth input terminals connected to the output terminal of the third comparator for receiving the first control signal and the second control signal. Its sixth input terminal is used to receive the fourth clock signal.

13. The decision feedback equalization circuit according to claim 12, characterized in that, The phase of the first clock signal is 90° earlier than the phase of the second clock signal; The phase of the first clock signal is 180° earlier than the phase of the third clock signal; The phase of the first clock signal is 270° earlier than the phase of the fourth clock signal.

14. The decision feedback equalization circuit according to claim 12, characterized in that, The voltage switching time at the output terminals of the first comparator to the fourth comparator is less than the time interval between the first clock signal and the second clock signal.

15. The decision feedback equalization circuit according to any one of claims 12 to 14, characterized in that, The decision feedback equalization circuit also includes: The first register has its input connected to the output of the first comparator; The second register has its input connected to the output of the second comparator; The third register has its input connected to the output of the third comparator; The fourth register has its input connected to the output of the fourth comparator.

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