First-order filtering successive approximation analog-to-digital converter based on differential amplifier and its method

Abstract

This invention discloses a first-order filtered successive approximation analog-to-digital converter based on a differential amplifier, comprising a sampling circuit, a capacitor array, a transconductance amplifier, and resistors. The capacitor array is disposed on the sampling circuit. The transconductance amplifier and resistors are sequentially disposed at the signal output terminals of the sampling circuit, which is controlled by successive approximation logic. Three transconductance amplifiers are disposed in parallel, and the three transconductance amplifiers and resistors together form a three-input comparator to perform high-pass filtering on the residual voltage of the sampling circuit, reducing quantization noise in the low-frequency range. The three-input comparator constitutes a noise shaping circuit for sampling and feedback of the residual voltage, shaping and low-pass filtering the noise introduced during quantization, significantly reducing noise components in the low-frequency range and improving the accuracy of the analog-to-digital converter.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converters, and more particularly to a first-order filtered successive approximation analog-to-digital converter based on a differential amplifier and its method. Background Technology

[0002] Traditional successive approximation analog-to-digital converters (ADCs) leave a residual voltage across the comparator after each quantization step. This voltage reflects the quantization noise of the ADC. Under the same sampling conditions, the higher the accuracy of the ADC, the smaller this voltage, the lower the quantization noise, and the higher the quantization accuracy. Current successive approximation ADCs do not effectively utilize this residual voltage; the common practice is to discard it directly. Therefore, the quantization noise of traditional successive approximation ADCs is evenly distributed across the entire frequency band, limiting the accuracy of the ADC. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the shortcomings of the prior art, the present invention provides a first-order filtered successive approximation analog-to-digital converter based on a differential amplifier, which adds sampling and feedback circuits for the residual voltage, performs high-pass filtering on the noise introduced during the quantization process, significantly reduces low-frequency components, and improves the accuracy of the analog-to-digital converter.

[0004] Technical Solution: To achieve the above objectives, the present invention provides a first-order filtered successive approximation analog-to-digital converter based on a differential amplifier, comprising a sampling circuit, a capacitor array, a transconductance amplifier, and resistors; the capacitor array is disposed on the sampling circuit; the transconductance amplifiers and resistors are sequentially disposed at the signal output terminals of the sampling circuit, and the capacitor array is controlled by successive approximation logic; three transconductance amplifiers are disposed in parallel, and the three transconductance amplifiers and resistors together form a three-input comparator to perform low-pass filtering on the remaining voltage of the sampling circuit, thereby reducing quantization noise in the low-frequency range.

[0005] Furthermore, the transconductance amplifier includes a first transconductance amplifier, a second transconductance amplifier, and a third transconductance amplifier; the first transconductance amplifier corresponds to the comparison and quantization of the external signal, and the second and third transconductance amplifiers work alternately according to the clock cycle to store the remaining voltage of the capacitor array in the previous cycle and the remaining voltage of the current cycle, respectively.

[0006] Furthermore, a first storage control group and a first common-mode connection control group are connected in series on the line of the second transconductance amplifier; the first storage control group includes a third switch and a fourth switch controlled by a first storage clock; the first common-mode connection control group includes a fifth switch and a sixth switch controlled by a first common-mode clock.

[0007] Furthermore, a second storage control group and a second common-mode connection control group are connected in series on the circuit of the third transconductance amplifier; the second storage control group includes a seventh switch and an eighth switch controlled by a second storage clock; the second common-mode connection control group includes a ninth switch and a tenth switch controlled by a second common-mode clock.

[0008] Furthermore, the sampling circuit includes a first switch and a second switch, which together form a switch group, and the signal input voltage of the sampling circuit is controlled by the sampling clock.

[0009] The working method of a first-order filter successive approximation analog-to-digital converter based on a differential amplifier:

[0010] In the nth period:

[0011] Step 1: Analog-to-digital converter sampling; the sampling clock goes high, the first and second switches close, connecting the sampling circuit and capacitor array across the first transconductance amplifier to sample the input signals Vinp(n) and Vinn(n); the first common-mode clock goes high, the fifth and sixth switches close, the input of the second transconductance amplifier is shorted to the common-mode voltage, and the differential input voltage is zero; at this time, the voltage at the input of the third transconductance amplifier is the residual voltage Vres(n-1) of the previous cycle; the first, second, and third transconductance amplifiers and resistors form a three-input comparator, and the differential input voltage across the three-input comparator is:

[0012] Vin_comp(n)=(Vinp(n)-Vinn(n))+Vres(n-1)

[0013] Step 2, comparator comparison; after sampling, the three-input comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n) and Vresn(n) at both ends of the comparator, which is amplified to Vres(n) by the transconductance amplifier.

[0014] Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n). Considering that the input of the third transconductance amplifier contains the remaining voltage information, the second transconductance amplifier is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the first storage clock, the third and fourth switches are closed, and the second transconductance amplifier and the resistor are connected in a unity-gain configuration to sample the remaining voltage Vres(n) and store it at the input of the second amplifier. Before the next sampling signal arrives through the sampling clock, the first storage clock is pulled low, the third and fourth switches are opened, and the sampling of the remaining voltage is completed.

[0015] In the (n+1)th cycle, the functions of the second and third transconductance amplifiers are swapped. The input of the second transconductance amplifier stores the residual voltage Vres(n) from the previous cycle, while the third transconductance amplifier is used to sample the residual voltage Vres(n+1) generated by quantization in the current cycle. The specific working process is described as follows:

[0016] Step 1: Analog-to-digital converter sampling; the sampling clock goes high, the first and second switches close, connecting the sampling circuit and capacitor array across the first transconductance amplifier to sample the input signals Vinp(n+1) and Vinn(n+1); at this time, the input voltage of the second transconductance amplifier is the residual voltage Vres(n) of the previous cycle; the second common-mode clock goes high, the ninth and tenth switches close, the input of the third transconductance amplifier is shorted to the common-mode voltage, and the differential input voltage is zero; the first, second, and third transconductance amplifiers and the resistors form a three-input comparator, and the differential input voltage across the three-input comparator is:

[0017] Vin_comp(n+1)=(Vinp(n+1)-Vinn(n+1))+Vres(n)

[0018] Step 2, comparator comparison; after sampling, the comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n+1) and Vresn(n+1) at both ends of the comparator, which is amplified to Vres(n+1) by the transconductance amplifier.

[0019] Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n+1). Considering that the input of the second transconductance amplifier contains the remaining voltage information, the third transconductance amplifier is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the second storage clock, the seventh and eighth switches are closed, and the transconductance amplifier GM3 and the resistor are connected in a unity-gain form to sample the remaining voltage Vres(n+1) and store it at the input of the third transconductance amplifier. Before the next clock cycle arrives, the second storage clock is pulled low, the seventh and eighth switches are opened, and the sampling of the remaining voltage is completed.

[0020] This cyclical operation shapes the quantization noise to a higher frequency range and reduces the quantization noise in the low-frequency range.

[0021] Beneficial effects: (1) The first-order filter successive approximation analog-to-digital converter based on differential amplifier of the present invention includes a sampling circuit, a capacitor array, a transconductance amplifier and a resistor; the capacitor array is disposed on the sampling circuit; the transconductance amplifier and the resistor are disposed sequentially at the signal output terminal of the sampling circuit, and the sampling circuit is controlled by successive approximation logic; three transconductance amplifiers are disposed in parallel, and the three transconductance amplifiers and the resistors together form a three-input comparator to perform low-pass filtering on the remaining voltage of the sampling circuit and reduce quantization noise in the low frequency range; the three-input comparator constitutes a noise shaping circuit for sampling and feedback of the remaining voltage, and performs low-pass filtering on the noise introduced during the quantization process. (1) The noise component in the low frequency range is greatly reduced, which improves the accuracy of the analog-to-digital converter; (2) The first-order filter successive approximation analog-to-digital converter based on differential amplifier of the present invention includes a first transconductance amplifier, a second transconductance amplifier and a third transconductance amplifier; the first transconductance amplifier corresponds to the comparison quantization of the external signal, and the second transconductance amplifier and the third transconductance amplifier work alternately according to the clock cycle to store the previous residual voltage and the current residual voltage of the sampling circuit respectively; in the operation of multiple consecutive cycles, the sampling of the residual voltage and the digital output result can be performed synchronously, which significantly improves the sampling and feedback speed of the residual voltage without adding extra time. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of a first-order filter successive approximation analog-to-digital converter based on a differential amplifier, according to the present invention.

[0023] Figure 2 This is a detailed diagram of the first-order filter successive approximation analog-to-digital converter architecture based on a differential amplifier according to the present invention;

[0024] Figure 3 This is a timing diagram of the first-order filter successive approximation analog-to-digital converter based on a differential amplifier according to the present invention. Detailed Implementation

[0025] The invention will now be further described with reference to the accompanying drawings.

[0026] like Figure 1-3 As shown, a first-order filtered successive approximation analog-to-digital converter based on a differential amplifier includes a sampling circuit 1, a capacitor array 2, a transconductance amplifier 3, and a resistor 4. The capacitor array 2 is disposed on the sampling circuit 1. The transconductance amplifier 3 and the resistor 4 are sequentially disposed at the signal output terminal of the sampling circuit 1. The capacitor array 2 is controlled by successive approximation logic. Three transconductance amplifiers 3 are disposed in parallel. The three transconductance amplifiers 3 and the resistor 4 together form a three-input comparator CLKC, which performs low-pass filtering on the remaining voltage of the sampling circuit 1 to reduce quantization noise in the low-frequency range.

[0027] Capacitor array 2 is set in Figure 1 At CDAC_P and CDAC_N, three-input comparators form a sampling and feedback circuit for the residual voltage. This circuit performs high-pass filtering on the noise introduced during quantization, significantly reducing low-frequency components and improving the accuracy of the analog-to-digital converter.

[0028] The transconductance amplifier 3 includes a first transconductance amplifier GM1, a second transconductance amplifier GM2, and a third transconductance amplifier GM3. The first transconductance amplifier GM1 is used to compare and quantize external signals. The second transconductance amplifier GM2 and the third transconductance amplifier GM3 work alternately according to the clock cycle to store the remaining voltage of the capacitor array 2 in the previous cycle and the remaining voltage in the current cycle, respectively.

[0029] The alternating operation of the second transconductance amplifier GM2 and the third transconductance amplifier GM3 according to the clock cycle can significantly improve the response speed of the residual voltage sampling and feedback circuit during multiple consecutive cycles.

[0030] refer to Figure 1 The two lines of the signal input terminal of the sampling circuit 1 are respectively equipped with a first switch SW11 and a second switch SW12. The first switch SW11 and the second switch SW12 together form a switch group, which is controlled by the sampling clock CLKS0, and correspondingly controls the signal input voltage of the sampling circuit 1.

[0031] The second transconductance amplifier GM2 is connected in series with a first storage control group and a first common-mode connection control group; the first storage control group includes a third switch SW21 and a fourth switch SW22 controlled by a first storage clock CLKS1; the first common-mode connection control group includes a fifth switch SW23 and a sixth switch SW24 controlled by a first common-mode clock CLKS01.

[0032] The third transconductance amplifier GM3 is connected in series with a second storage control group and a second common-mode connection control group; the second storage control group includes a seventh switch SW31 and an eighth switch SW32 controlled by a second storage clock CLKS2; the second common-mode connection control group includes a ninth switch SW33 and a tenth switch SW34 controlled by a second common-mode clock CLKS02.

[0033] The three-input comparator CLKC, together with the matching storage control group and common-mode connection control group, forms a noise shaping circuit with simple switching control timing. It is not only easy to implement, but also allows for synchronous sampling of the residual voltage and retrieval of the digital output result without adding extra time.

[0034] The working method of a first-order filter successive approximation analog-to-digital converter based on a differential amplifier:

[0035] In the nth period:

[0036] Step 1: Analog-to-digital converter sampling; sampling clock CLKS0 is pulled high, first switch SW11 and second switch SW12 are closed, connecting the sampling circuit across the first transconductance amplifier GM1 and capacitor array 2 to sample input signals Vinp(n) and Vinn(n); first common-mode clock CLKS01 is pulled high, fifth switch SW23 and sixth switch SW24 are closed, the input terminal of the second transconductance amplifier GM2 is shorted to the common-mode voltage, and the differential input voltage is zero; at this time, the voltage at the input terminal of the third transconductance amplifier GM3 is the residual voltage Vres(n-1) of the previous cycle; the first transconductance amplifier GM1, the second transconductance amplifier GM2, the third transconductance amplifier GM3 and resistor 4 form a three-input comparator, and the differential input voltage across the three-input comparator is:

[0037] Vin_comp(n)=(Vinp(n)-Vinn(n))+Vres(n-1)

[0038] Step 2, comparator comparison; after sampling, the three-input comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n) and Vresn(n) at both ends of the comparator, which is amplified to Vres(n) by the transconductance amplifier.

[0039] Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n). Considering that the input of the third transconductance amplifier GM3 contains the remaining voltage information, the second transconductance amplifier GM2 is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the first storage clock CLKS1, the third switch SW21 and the fourth switch SW22 are closed, and the second transconductance amplifier GM2 and resistor 4 are connected in unity gain form to sample the remaining voltage Vres(n) and store it at the input of the second amplifier GM2. Before the next sampling signal arrives through the sampling clock CLKS0, the first storage clock CLKS1 is pulled low, the third switch SW21 and the fourth switch SW22 are opened, and the sampling of the remaining voltage is completed.

[0040] In the (n+1)th cycle, the functions of the second transconductance amplifier GM2 and the third transconductance amplifier GM3 are swapped. The input of the second transconductance amplifier GM2 stores the residual voltage Vres(n) from the previous cycle, while the third transconductance amplifier GM3 is used to sample the residual voltage Vres(n+1) generated by quantization in the current cycle. The specific working process is described as follows:

[0041] Step 1: Analog-to-digital converter sampling; sampling clock CLKS0 is pulled high, first switch SW11 and second switch SW12 are closed, connecting the sampling circuit across the first transconductance amplifier GM1 and capacitor array 2 to sample input signals Vinp(n+1) and Vinn(n+1); at this time, the input voltage of the second transconductance amplifier GM2 is the residual voltage Vres(n) of the previous cycle; second common-mode clock CLKS02 is pulled high, ninth switch SW33 and tenth switch SW34 are closed, the input of the third transconductance amplifier GM3 is shorted to the common-mode voltage, and the differential input voltage is zero; the first transconductance amplifier GM1, the second transconductance amplifier GM2, the third transconductance amplifier GM3 and resistor 4 form a three-input comparator, and the differential input voltage across the three-input comparator is:

[0042] Vin_comp(n+1)=(Vinp(n+1)-Vinn(n+1))+Vres(n)

[0043] Step 2, comparator comparison; after sampling, the comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n+1) and Vresn(n+1) at both ends of the comparator, which is amplified to Vres(n+1) by the transconductance amplifier.

[0044] Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n+1). Considering that the input of the second transconductance amplifier GM2 contains the remaining voltage information, the third transconductance amplifier GM3 is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the second storage clock CLKS2, the seventh switch SW31 and the eighth switch SW32 are closed, and the transconductance amplifier GM3 and the resistor are connected in a unity-gain form to sample the remaining voltage Vres(n+1) and store it at the input of the third transconductance amplifier GM3. Before the next clock cycle CLKS0 arrives, the second storage clock CLKS2 is pulled low, the seventh switch SW31 and the eighth switch SW32 are opened, and the sampling of the remaining voltage is completed.

[0045] This cyclical operation shapes the quantization noise to a higher frequency range and reduces the quantization noise in the low-frequency range.

[0046] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A first-order filter successive approximation analog-to-digital converter based on a differential amplifier, characterized in that: The system includes a sampling circuit (1), a capacitor array (2), a transconductance amplifier (3), and a resistor (4). The capacitor array (2) is disposed on the sampling circuit (1). The transconductance amplifier (3) and the resistor (4) are disposed sequentially at the signal output terminal of the sampling circuit (1). The capacitor array (2) is controlled by successive approximation logic. Three transconductance amplifiers (3) are disposed in parallel. The three transconductance amplifiers (3) and the resistor (4) together form a three-input comparator to perform low-pass filtering on the remaining voltage of the sampling circuit (1) to reduce quantization noise in the low-frequency range. The transconductance amplifier (3) includes a first transconductance amplifier (GM1), a second transconductance amplifier (GM2) and a third transconductance amplifier (GM3); the first transconductance amplifier (GM1) corresponds to the comparison and quantization of the external signal, and the second transconductance amplifier (GM2) and the third transconductance amplifier (GM3) work alternately according to the clock cycle to store the remaining voltage of the capacitor array (2) in the previous cycle and the remaining voltage of the current cycle respectively. The working method of a first-order filter successive approximation analog-to-digital converter based on a differential amplifier. In the nth period: Step 1, the analog-to-digital converter samples; the sampling clock (CLKS0) is pulled high, the first switch (SW11) and the second switch (SW12) are closed, and the sampling circuit and capacitor array (2) connected to the first transconductance amplifier (GM1) sample the input signals Vinp(n) and Vinn(n); the first common-mode clock (CLKS01) is pulled high, the fifth switch (SW23) and the sixth switch (SW24) are closed, the input terminal of the second transconductance amplifier (GM2) is shorted to the common-mode voltage, and the differential input voltage is zero; at this time, the voltage at the input terminal of the third transconductance amplifier (GM3) is the residual voltage Vres(n-1) of the previous cycle; the first transconductance amplifier (GM1), the second transconductance amplifier (GM2), the third transconductance amplifier (GM3) and the resistor (4) form a three-input comparator, and the differential input voltage across the three-input comparator is: Step 2, comparator comparison; after sampling, the three-input comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n) and Vresn(n) at both ends of the comparator, which is amplified to Vres(n) by the transconductance amplifier. Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n). Considering that the input of the third transconductance amplifier (GM3) contains the remaining voltage information, the second transconductance amplifier (GM2) is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the first storage clock (CLKS1), the third switch (SW21) and the fourth switch (SW22) are closed, and the second transconductance amplifier (GM2) and the resistor (4) are connected in a unity-gain form to sample the remaining voltage Vres(n) to the input of the second amplifier (GM2) and store it. Before the next sampling signal arrives through the sampling clock (CLKS0), the first storage clock (CLKS1) is pulled low, the third switch (SW21) and the fourth switch (SW22) are opened, and the sampling of the remaining voltage is completed. In the (n+1)th cycle: the functions of the second transconductance amplifier (GM2) and the third transconductance amplifier (GM3) are swapped. The input of the second transconductance amplifier (GM2) stores the residual voltage Vres(n) from the previous cycle, and the third transconductance amplifier (GM3) is used to sample the residual voltage Vres(n+1) generated by quantization in the current cycle. The specific working process is described as follows: Step 1, the analog-to-digital converter samples; the sampling clock (CLKS0) is pulled high, the first switch (SW11) and the second switch (SW12) are closed, and the sampling circuit and capacitor array (2) connected to the first transconductance amplifier (GM1) sample the input signals Vinp (n+1) and Vinn (n+1); at this time, the voltage at the input terminal of the second transconductance amplifier (GM2) is the residual voltage Vres (n) of the previous cycle; the second common-mode clock (CLKS02) is pulled high, the ninth switch (SW33) and the tenth switch (SW34) are closed, and the input terminal of the third transconductance amplifier (GM3) is shorted to the common-mode voltage, and the differential input voltage is zero; the first transconductance amplifier (GM1), the second transconductance amplifier (GM2), the third transconductance amplifier (GM3) and the resistor (4) form a three-input comparator, and the differential input voltage across the three-input comparator is: Step 2, comparator comparison; after sampling, the comparator starts comparison and flips the capacitor according to the comparison result each time. After all capacitor bits are compared, quantization ends. At this time, due to the logic characteristics of the successive approximation analog-to-digital converter, there will be a certain residual voltage Vresp(n+1) and Vresn(n+1) at both ends of the comparator, which is amplified to Vres(n+1) by the transconductance amplifier. Step 3: After quantization, the noise shaping circuit samples the remaining voltage Vres(n+1). Considering that the input of the second transconductance amplifier (GM2) contains the remaining voltage information, the third transconductance amplifier (GM3) is used to sample the remaining voltage generated by this quantization. The sampling signal is pulled high by the second storage clock (CLKS2), the seventh switch (SW31) and the eighth switch (SW32) are closed, and the transconductance amplifier (GM3) and the resistor are connected in a unity-gain form to sample the remaining voltage Vres(n+1) to the input of the third transconductance amplifier (GM3) and store it. Before the next clock cycle (CLKS0) arrives, the second storage clock (CLKS2) is pulled low, the seventh switch (SW31) and the eighth switch (SW32) are opened, and the sampling of the remaining voltage is completed. This cyclical operation shapes the quantization noise to a higher frequency range and reduces the quantization noise in the low-frequency range.

2. The first-order filter successive approximation sigma-delta analog-to-digital converter based on a differential amplifier according to claim 1, characterized in that: The second transconductance amplifier (GM2) has a first storage control group and a first common-mode connection control group connected in series on its circuit. The first storage control group includes a third switch (SW21) and a fourth switch (SW22) controlled by a first storage clock (CLKS1). The first common-mode connection control group includes a fifth switch (SW23) and a sixth switch (SW24) controlled by a first common-mode clock (CLKS01).

3. The first-order filter successive approximation sigma-delta analog-to-digital converter based on a differential amplifier according to claim 2, characterized in that: The third transconductance amplifier (GM3) has a second storage control group and a second common-mode connection control group connected in series on its circuit. The second storage control group includes a seventh switch (SW31) and an eighth switch (SW32) controlled by a second storage clock (CLKS2). The second common-mode connection control group includes a ninth switch (SW33) and a tenth switch (SW34) controlled by a second common-mode clock (CLKS02).

4. The first-order filtered successive approximation analog-to-digital converter based on a differential amplifier according to claim 1, characterized in that: The sampling circuit (1) includes a first switch (SW11) and a second switch (SW12). The first switch (SW11) and the second switch (SW12) together form a switch group, and the sampling clock (CLKS0) controls the signal input voltage of the sampling circuit (1).

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