12-bit digital-to-analog circuit

Abstract

The application provides a 12-bit digital-to-analog conversion circuit, which comprises a logic circuit, a transmission gate and a resistance array, the transmission gate being located between the logic circuit and the resistance array; the logic circuit comprises a clock control circuit, a decoder and a level conversion circuit, the resistance array is jointly constituted by an 8-bit R-2R type resistance array and a 4-bit binary resistance array; the clock control circuit is connected with the decoder and the level conversion circuit respectively, the level conversion circuit is connected with the transmission gate, and the transmission gate is connected with the resistance array; the input signal is output as a digital domain gate signal through the clock control circuit, then the digital domain gate signal is converted into an analog domain gate signal through the decoder and the voltage conversion circuit, and then a control signal for controlling the switches of the resistance array is output through the transmission gate, so that a digital-to-analog conversion circuit with high precision, high speed and low consumption is realized, and the performance of the digital-to-analog conversion circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to a 12-bit digital-to-analog converter circuit. Background Technology

[0002] A digital-to-analog converter (DAC) is a circuit unit that converts an input digital signal into a corresponding analog signal for output. It plays a crucial role in fields such as wireless communication and image processing. The accuracy and speed of a DAC are the core performance indicators; therefore, research on high-precision, high-speed DACs is of great significance and far-reaching impact. Summary of the Invention

[0003] In view of this, the present invention provides a 12-bit digital-to-analog converter circuit to realize a high-precision, high-speed, low-power digital-to-analog converter and improve the performance of the digital-to-analog converter.

[0004] This invention provides a 12-bit digital-to-analog converter circuit, comprising: a logic circuit, a transmission gate, and a resistor array, wherein the transmission gate is located between the logic circuit and the resistor array; the logic circuit includes a clock control circuit, a decoder, and a level conversion circuit; the resistor array is composed of an 8-bit R-2R type resistor array and a 4-bit binary resistor array; the clock control circuit is connected to the decoder and the level conversion circuit respectively; the level conversion circuit is connected to the transmission gate; and the transmission gate is connected to the resistor array.

[0005] Preferably, the 8-bit R-2R type resistor array is an R-2R ladder network structure consisting of a switch and two resistors with resistance values ​​of R and 2R respectively.

[0006] Preferably, the 4-bit binary resistor array is a 2R array structure consisting of 15 switches and 15 resistors with a resistance of 2R.

[0007] Preferably, the decoder is a 4-line to 16-line decoder.

[0008] Preferably, the transmission gate is a 12-bit low on-resistance transmission gate.

[0009] Preferably, the input signal outputs a 12-bit gating signal SEL<11:0> through the clock control circuit, wherein SEL<11:8> is decoded to output a 16-bit output signal Y<15:0>. The digital voltage domain signals Y<15:1> and SEL<7:0> are converted into analog voltage domain gating signals HVSEL_R<7:0> and HVSEL_T<15:1> through the voltage conversion circuit. The gating signals HVSEL_R<7:0> and HVSEL_T<15:1> are then transmitted through the transmission gate to output resistor control signals SR<7:0> and ST<15:1> with voltages of VREFP or VREFN.

[0010] Preferably, SR<7:0> controls the 8-bit R-2R resistor array to be connected to VREFP or VREFN, and ST<15:1> controls the 4-bit binary resistor array to be connected to VREFP or VREFN.

[0011] The 12-bit digital-to-analog converter circuit of this invention outputs a digital domain gating signal from the input signal via a clock control circuit. This signal is then converted to an analog domain gating signal via a decoder and voltage conversion circuit. Finally, a control signal for the control resistor array switch is output via a transmission gate, achieving a high-precision, high-speed, and low-power digital-to-analog converter circuit, thus improving the performance of the digital-to-analog converter circuit. The 12-bit digital-to-analog converter circuit of this invention has integral nonlinearity (INL) and differential nonlinearity (DNL) both less than 0.5 LSB. With a load capacitance of 10 pF, the data conversion rate is 25 MHz, and the power consumption is less than 600 μA. Attached Figure Description

[0012] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0013] Figure 1 The diagram shown is a structural block diagram of a 12-bit digital-to-analog converter circuit according to an embodiment of the present invention.

[0014] Figure 2 The diagram shown is a block diagram of the logic circuit according to an embodiment of the present invention.

[0015] Figure 3 The diagram shown is a structural block diagram of the transmission gate and resistor array according to an embodiment of the present invention.

[0016] Figure 4 The diagram shown is a schematic diagram of the circuit structure of the resistor array according to an embodiment of the present invention;

[0017] Figure 5 The diagram shows a schematic of the transmission gate circuit structure according to an embodiment of the present invention.

[0018] Figure 6 The diagram shows the simulation results of the parasitic resistance of the transmission gate with a width of 2u and a length of 0.7u in an embodiment of the present invention.

[0019] Figure 7 The figure shown is a simulation result diagram of the output voltage of the 12-bit digital-to-analog converter circuit according to an embodiment of the present invention;

[0020] Figure 8 The diagram shows the deviation between the actual output voltage and the ideal output voltage of the 12-bit digital-to-analog converter circuit in an embodiment of the present invention. Detailed Implementation

[0021] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0022] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0023] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0024] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0025] Digital-to-analog converters (DACs) are commonly used interface circuits between digital and analog electronic systems. Modern advanced electronic systems utilize both analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) at both the front and back ends to improve the performance of digital processing technologies. With the development of communication and multimedia technologies, increasingly higher demands are being placed on the conversion speed and resolution of DACs, leading to a growing market demand for high-speed, high-precision DACs.

[0026] Among the many conversion networks in DAC converters, trapezoidal resistor networks improve accuracy while saving chip area; at the same time, voltage-type trapezoidal resistor networks can achieve the same polarity between the output voltage and the bandgap voltage, and therefore have been widely used.

[0027] This invention designs a novel 12-bit digital-to-analog converter circuit. It meets the following requirements: high-speed design: data conversion rate of 25MHz when load capacitance = 10pF; high-precision design: INL:

[0028] + / -0.5LSB, DNL: + / -0.5LSB; Low power design: less than 600uA.

[0029] Figure 1 The diagram shown is a structural block diagram of a 12-bit digital-to-analog converter circuit according to an embodiment of the present invention. Figure 1 As shown, the 12-bit digital-to-analog converter circuit of this embodiment includes a logic circuit 101, a transmission gate 102, and a resistor array 103. The transmission gate 102 is located between the logic circuit 101 and the resistor array 103, and the input signal of the circuit is DATA_IN<11:0>.

[0030] Among them, such as Figure 2 and Figure 3 As shown, the logic circuit 101 in this embodiment of the invention includes a clock control circuit 104, a decoder 105, and a level conversion circuit 106. The clock control circuit 104 is connected to both the decoder 105 and the level conversion circuit 106, and the transmission gate 102 is connected to the resistor array 103. In this embodiment, the clock control circuit 104 is a sequential (Duff) circuit, the decoder 105 is a 4-line to 16-line decoder, and the level conversion circuit 106 is a 1.5V / 5V level conversion circuit. The input signal DATA_IN<11:0> outputs a 12-bit strobe signal SEL<11:0> through the clock control circuit 104. SEL<11:8> is then decoded by the decoder 105 to output a 16-bit output signal Y<15:0>. The digital voltage domain signals Y<15:1> and SEL<7:0> are converted into analog voltage domain strobe signals HVSEL_R<7:0> and HVSEL_T<15:1> by the voltage conversion circuit 106. The strobe signals HVSEL_R<7:0> and HVSEL_T<15:1> then pass through the transmission gate 102 to output resistor control signals SR<7:0> and ST<15:1> with voltages of VREFP or VREFN.

[0031] Figure 4 The diagram shown is a schematic representation of the circuit structure of a resistor array according to an embodiment of the present invention. Figure 4As shown, resistor array 103 is composed of an 8-bit R-2R type resistor array and a 4-bit binary resistor array. In this embodiment of the invention, the 8-bit R-2R type resistor array is an R-2R ladder network structure consisting of switches and two resistors with resistance values ​​of R and 2R respectively. The 4-bit binary resistor array is a 2R array structure consisting of 15 switches and 15 resistors with a resistance value of 2R. This embodiment of the invention proposes a DAC resistor conversion strategy of 8-bit R-2R resistor array + 4-bit binary structure resistor array through experimental calculations. The 8-bit R-2R resistor array is selected to be connected to VREFP or VREFN by the switch SR<7:0>, and the 4-bit binary structure resistor array is selected to be connected to VREFP or VREFN by ST<15:1>.

[0032] Figure 5 The diagram shown illustrates the circuit structure of the transmission gate in an embodiment of the present invention. Figure 5 As shown, in this embodiment of the invention, the transmission gate 102 is a 12-bit low on-resistance transmission gate, including a PMOS transistor PM0 and an NMOS transistor NM0 connected in series. The source terminal of PM0 is connected to VREFP, the source terminal of NM0 is connected to VREFN, the gate terminal is connected to the same signal HV_SEL, and the drain terminal outputs VREF_SEL.

[0033] The parasitic resistance of the transmission gate affects the accuracy of the DAC resistor network, and the size selection of PM0 and NM0 requires a trade-off between accuracy and area. Binary resistor arrays are sensitive to the parasitic resistance of the transmission gate; therefore, the ratio of the parasitic resistance of the transmission gate to the individual resistor R in the array needs to be less than a certain value to avoid affecting the DAC's accuracy. However, the sensitivity of R-2R resistor arrays to the parasitic resistance of the transmission gate decreases progressively, so the requirements for the parasitic resistance of the transmission gate can be relaxed, and the corresponding MOSFET sizes will also decrease progressively. For example... Figure 6 As shown, when the width of transmission gates PM0 and NM0 is 2u and the length is 0.7u, the simulation results of the parasitic resistance / resistor array resistance of different multiply (i.e., transmission gates of different sizes) are obtained. From the simulation results, it can be seen that the transmission gate size of the binary structure resistor array can be selected as TG5, and the transmission gates of the R-2R resistor array can be selected step by step as TG5, TG4, TG3, and TG2.

[0034] Figure 7 The figure shows the simulation results of the output voltage of the 12-bit digital-to-analog converter circuit according to an embodiment of the present invention. Where: VREFP = 5V, VREFN = 0V, T_CLK = 40ns. As can be seen from the figure, under the condition of a data conversion rate of 25MHz, VOUT can be output correctly and maintains single linearity, meeting the specifications of high-speed design.

[0035] Figure 8The diagram shows the deviation between the actual output voltage and the ideal output voltage of the 12-bit digital-to-analog converter circuit in this embodiment of the invention. The calculation formula is (VOUT - VOUT_ideal) / 1LSB. It can be seen that the outputs are all less than 0.1LSB, which meets the specifications of high-precision design.

[0036] The 12-bit digital-to-analog converter circuit of this embodiment consumes approximately 400uA, which meets the low-power design specifications.

[0037] In summary, simulations show that the digital-to-analog converter designed in this invention has an integral nonlinearity (INL) and a differential nonlinearity (DNL) of less than 0.5 LSB. In terms of speed, the data conversion rate is 25 MHz with a load capacitance of 10 pF. Regarding power consumption, it is less than 600 μA.

[0038] The 12-bit digital-to-analog converter circuit of the present invention includes a logic circuit, a transmission gate, and a resistor array. The transmission gate is located between the logic circuit and the resistor array. The logic circuit includes a clock control circuit, a decoder, and a level conversion circuit. The resistor array is composed of an 8-bit R-2R type resistor array and a 4-bit binary resistor array, realizing a high-precision, high-speed, and low-power digital-to-analog converter circuit and improving the performance of the digital-to-analog converter circuit.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 12-bit digital-to-analog converter circuit, characterized in that, include: A logic circuit, a transmission gate, and a resistor array, wherein the transmission gate is located between the logic circuit and the resistor array; The logic circuit includes a clock control circuit, a decoder, and a level conversion circuit. The resistor array is composed of an 8-bit R-2R type resistor array and a 4-bit binary resistor array. The 4-bit binary resistor array is a 2R array structure consisting of 15 switches and 15 resistors with a resistance of 2R. The clock control circuit is connected to the decoder and the level conversion circuit. The level conversion circuit is connected to the transmission gate, and the transmission gate is connected to the resistor array. The input signal outputs a 12-bit gating signal SEL<11:0> through the clock control circuit. SEL<11:8> is then decoded to output a 16-bit output signal Y<15:0>. The digital voltage domain signals Y<15:1> and SEL<7:0> are converted into analog voltage domain gating signals HVSEL_R<7:0> and HVSEL_T<15:1> by the level conversion circuit. The gating signals HVSEL_R<7:0> and HVSEL_T<15:1> are then transmitted through the transmission gate, outputting resistor control signals SR<7:0> and ST<15:1> with voltages of VREFP or VREFN.

2. The 12-bit digital-to-analog converter circuit according to claim 1, characterized in that, The 8-bit R-2R type resistor array is an R-2R ladder network structure consisting of a switch and two resistors with resistance values ​​of R and 2R respectively.

3. The 12-bit digital-to-analog converter circuit according to claim 1, characterized in that, The decoder is a 4-line to 16-line decoder.

4. The 12-bit digital-to-analog converter circuit according to claim 1, characterized in that, The transmission gate is a 12-bit low on-resistance transmission gate.

5. The 12-bit digital-to-analog converter circuit according to claim 1, characterized in that, The SR<7:0> controls the 8-bit R-2R resistor array to be connected to VREFP or VREFN, and the ST<15:1> controls the 4-bit binary resistor array to be connected to VREFP or VREFN.

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