Digital front-end processing apparatus, signal processing method and antenna device

Abstract

The present disclosure provides a digital front-end processing device, a signal processing method of the digital front-end processing device and an antenna device, and belongs to the technical field of integrated circuits. The digital front-end processing device is configured to process radio frequency signals transmitted by N transmission links between a baseband and an antenna unit, N is greater than or equal to 1 and is an integer; each of the N transmission links comprises at least one sub-link; wherein an equalizer and a channel assessment unit are configured on the sub-link; the digital front-end processing device further comprises a microprocessor; for any sub-link, the channel assessment unit thereon is configured to assess a transmission channel of a radio frequency signal received thereby and send an assessment result to the microprocessor, so that the microprocessor determines a filter coefficient according to the assessment result; and the equalizer is configured to filter the radio frequency signal according to the filter coefficient determined by the microprocessor.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit technology, specifically relating to a digital front-end processing device, a signal processing method for the digital front-end processing device, and an antenna device. Background Technology

[0002] In recent years, with the rapid development of integrated circuits and system-on-a-chip (SoC), high integration, ultra-wideband, and low power consumption have been the goals of continuous research and development. Among these, the conversion from analog to digital signals is of paramount importance. Due to the complexity of the environment, the conversion from analog to digital signals requires multiple processing steps. Equalizers, as electronic devices that can adjust the amplification of electrical signals of various frequency components, compensate for insufficient or saturated sampling of analog signals by adjusting electrical signals of different frequencies.

[0003] Existing analog compensation equalization schemes are only used to compensate for filter bandwidth deviations caused by process variations and temperature changes, or require complex circuits to achieve bandwidth calibration. When using analog circuits to implement equalizers, the difficulty is high and performance cannot be guaranteed; implementing equalization functions and algorithms in software is time-consuming. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a digital front-end processing device, a signal processing method of the digital front-end processing device, and an antenna device.

[0005] In a first aspect, embodiments of this disclosure provide a digital front-end processing apparatus configured to process radio frequency signals transmitted through N transmission links between a baseband and an antenna unit, where N ≥ 1 and N is an integer; each of the N transmission links includes at least one sub-link; wherein an equalizer and a channel evaluation unit are configured on the sub-link; the digital front-end processing apparatus further includes a microprocessor.

[0006] For any of the sub-links, the channel evaluation unit thereon is configured to evaluate the transmission channel of the received radio frequency signal and send the evaluation result to the microprocessor so that the microprocessor determines the filtering coefficients based on the evaluation result; the equalizer is configured to filter the radio frequency signal based on the filtering coefficients determined by the microprocessor.

[0007] The sub-link includes a transmission link; the transmission link includes a signal compensation unit.

[0008] The signal compensation unit is configured to perform initial compensation on the radio frequency signal and send it to the equalizer, and the signal compensation unit is multiplexed as the channel evaluation unit in the transmission link.

[0009] The transmission link further includes a DC offset compensation unit;

[0010] The DC offset compensation unit is configured to perform DC offset compensation on the equalizer-filtered RF signal and transmit the DC offset-compensated RF signal.

[0011] The sub-link further includes a receiving link; the receiving link further includes a DC offset compensation unit.

[0012] The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

[0013] The receiving link includes a signal compensation unit.

[0014] The signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracked and compensated radio frequency signal.

[0015] The sub-link further includes a feedback link; the feedback link further includes a DC offset compensation unit.

[0016] The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

[0017] The feedback link further includes a signal compensation unit;

[0018] The signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracked and compensated radio frequency signal.

[0019] The equalizer includes a time-domain synchronization module, a storage module, and a filtering module.

[0020] The time-domain synchronization module is configured to synchronize the equalizer with the microprocessor in the time domain according to the received time-domain synchronization signal from the microprocessor.

[0021] The storage module is configured to receive and store the filter coefficients sent by the microprocessor when detecting edge changes in the request signal sent by the microprocessor.

[0022] The filtering module is configured to filter the radio frequency signal according to the filtering coefficients stored in the storage module under the control of an enable signal.

[0023] The filtering module includes a first accumulator, a multiplier, a second accumulator, a first arithmetic unit, and a second arithmetic unit.

[0024] The first accumulator is configured to receive radio frequency signals and accumulate a portion of the radio frequency signals;

[0025] The multiplier is used to multiply the radio frequency signal input to the filtering module with the filtering coefficients.

[0026] The second accumulator is configured to accumulate the output of the multiplier;

[0027] The first arithmetic unit is configured to perform a rounding operation on the radio frequency signal output by the second accumulator and transmit the calculation result to the second arithmetic unit;

[0028] The second arithmetic unit is configured to perform saturation calculation on the radio frequency signal output by the first arithmetic unit and then output it.

[0029] The transmission link includes two sub-links, namely a first sub-link and a second sub-link; the radio frequency signal transmitted by the first sub-link is orthogonal to the radio frequency signal transmitted by the second sub-link.

[0030] Secondly, embodiments of this disclosure also provide a signal processing method for a digital front-end processing device, the signal processing method of which includes processing radio frequency signals transmitted through N transmission links between a baseband and an antenna unit by any of the aforementioned digital front-end processing devices; wherein, the processing of radio frequency signals transmitted through any sub-link of each of the N transmission links includes:

[0031] The channel evaluation unit evaluates the transmission channel of the received radio frequency signal and feeds back the evaluation result to the microprocessor.

[0032] The microprocessor determines the filtering coefficients based on the evaluation results;

[0033] The equalizer filters the radio frequency signal according to the filtering coefficients determined by the microprocessor.

[0034] The sub-link includes a transmission link; the transmission link includes a signal compensation unit, and the signal compensation unit is multiplexed as the channel evaluation unit in the transmission link; the sub-link further includes the following before the equalizer filters the radio frequency signal:

[0035] The radio frequency signal is initially compensated by the signal compensation unit and then sent to the equalizer microprocessor.

[0036] The transmission link further includes a DC offset compensation unit; and after the equalizer filters the radio frequency signal, it further includes:

[0037] The DC offset compensation unit performs DC offset compensation on the equalizer-filtered RF signal and then transmits the DC offset-compensated RF signal.

[0038] The sub-link includes a receiving link; the receiving link includes a DC offset compensation unit; and the process further includes the following steps before the equalizer filters the radio frequency signal:

[0039] The DC offset compensation unit performs DC offset compensation on the radio frequency signal and sends it to the channel evaluation unit. The channel evaluation unit performs channel evaluation on the radio frequency signal received by the input signal terminal and transmits the radio frequency signal to the equalizer through the output signal terminal. At the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

[0040] The receiving link further includes a signal compensation unit; and after the equalizer filters the radio frequency signal, it further includes:

[0041] The signal compensation unit performs tracking compensation on the radio frequency signal and then transmits the tracked and compensated radio frequency signal.

[0042] The sub-link is a feedback link; the feedback link includes a DC offset compensation unit; and the process further includes the following steps before the equalizer filters the RF signal:

[0043] The DC offset compensation unit performs DC offset compensation on the radio frequency signal and sends it to the channel evaluation unit. The channel evaluation unit performs channel evaluation on the radio frequency signal received by the input signal terminal and transmits the radio frequency signal to the equalizer through the output signal terminal. At the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

[0044] The feedback link further includes a signal compensation unit; and after the equalizer filters the radio frequency signal, it further includes:

[0045] The signal compensation unit performs tracking compensation on the radio frequency signal and then transmits the tracked and compensated radio frequency signal.

[0046] Thirdly, embodiments of this disclosure also provide an antenna device, the antenna device including any of the digital front-end processing devices described above. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the equalizer connection structure according to an embodiment of the present disclosure.

[0048] Figure 2 This is a schematic diagram of the transmission link connection structure according to an embodiment of the present disclosure.

[0049] Figure 3 This is a schematic diagram of the transmission link connection structure according to an embodiment of the present disclosure.

[0050] Figure 4 This is a schematic diagram of the receiving link connection structure according to an embodiment of the present disclosure.

[0051] Figure 5 This is a schematic diagram of the feedback link connection structure according to an embodiment of the present disclosure.

[0052] Figure 6 This is a flowchart of a signal processing method of a digital front-end processing apparatus according to an embodiment of the present disclosure.

[0053] Figure 7 This is a flowchart of a signal processing method of a digital front-end processing device in a transmission link according to an embodiment of the present disclosure.

[0054] Figure 8 This is a flowchart illustrating the operation of each module of the equalizer in the transmission link according to an embodiment of this disclosure.

[0055] Figure 9 This is a flowchart illustrating the filtering process performed by the equalizer in the transmission link according to an embodiment of this disclosure.

[0056] Figure 10 This is a flowchart of a signal processing method of a digital front-end processing device in a receiving link according to an embodiment of the present disclosure.

[0057] Figure 11 This is a flowchart illustrating the operation of each module of the equalizer in the receiving link according to an embodiment of this disclosure.

[0058] Figure 12 This is a flowchart illustrating the filtering process performed by the equalizer in the receiving link according to an embodiment of this disclosure. Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0061] When radio frequency (RF) signal transceivers enable communication between devices, they typically use three transmission links: a receiving transmission link for receiving RF signals transmitted by external devices via antennas, a transmitting transmission link for transmitting RF signals, and a feedback transmission link for verifying the transmitted signals. Taking signal transmission as an example, the transmission process of the transmitting transmission link includes, in sequence, RF signal input, analog-to-digital conversion, digital logic processing and filtering of the converted digital signal, transmission of the filtered signal to the multimedia layer for data format conversion, transmission of the format-converted data signal to the physical layer, modulation of the digital signal to obtain the time and frequency domains of the signal, and finally conversion into an analog signal for transmission via antenna. The receiving process of the receiving transmission link is the reverse of the transmitting process and will not be repeated here.

[0062] In the process of radio frequency signal transmission and reception, digital logic operations and filtering are required for the received and transmitted signals to improve signal quality. Filtering is a crucial step in this process. Taking low-pass filtering as an example, when low-pass filtering is applied to the received or transmitted signal, the signal may experience amplitude roll-off, resulting in poor final signal quality.

[0063] Therefore, this disclosure provides a digital front-end processing device that can simultaneously filter and equalize / compensate radio frequency (RF) signals. Implementing equalizers using analog circuits in the prior art is difficult and its performance is hard to guarantee; implementing equalization functions and algorithms in software is time-consuming. The digital front-end processing device of this disclosure includes a technical solution that uses a microprocessor to adjust the filter coefficients, combined with circuitry to filter and compensate for RF signals. A signal processing method for the digital front-end processing device is also disclosed to achieve simultaneous filtering of RF signals and compensation for potential amplitude roll-off.

[0064] The digital front-end processing apparatus of this disclosure will be described in detail below with reference to specific embodiments and accompanying drawings.

[0065] In a first aspect, embodiments of this disclosure provide a digital front-end processing device, such as... Figure 1 As shown, the digital front-end processing device is configured to process radio frequency (RF) signals transmitted through N transmission links between the baseband and antenna elements, where N ≥ 1 and N is an integer; each of the N transmission links includes at least one sub-link. Each sub-link is equipped with an equalizer 10 and a channel evaluation unit 12; the digital front-end processing device also includes a microprocessor 11. For any sub-link, the channel evaluation unit 12 is configured to evaluate the transmission channel of the received RF signal and send the evaluation result to the microprocessor 11, so that the microprocessor 11 determines the filtering coefficients based on the evaluation result; the equalizer 10 is configured to filter the RF signal according to the filtering coefficients determined by the microprocessor 11.

[0066] It should be noted that in this embodiment, the microprocessor 11 and the equalizer 10 are connected via an Advanced High Performance Bus (AHB). Those skilled in the art can adjust the connection method and the type of connection cable between the microprocessor 11 and the equalizer 10 according to the actual product and usage. This disclosure does not impose any further limitations on this.

[0067] In the digital front-end processing apparatus of this embodiment, since the microprocessor 11 generates filter coefficients based on the channel evaluation results, and the equalizer 10 filters the radio frequency (RF) signal based on these filter coefficients, the analog circuitry is combined with software to implement the filtering, compensation, and equalization operations of the RF signal. This reduces the difficulty of performing filtering, compensation, and equalization operations on the RF signal and improves the signal processing effect. Furthermore, when the equalizer 10 is used as a low-pass filter, the problem of amplitude roll-off during low-pass filtering of the RF signal is also solved, improving the signal quality of the final processed RF signal.

[0068] In some examples, N transmission links between the baseband and antenna elements can perform radio frequency signal transmission, reception, and feedback processing. For example, in this embodiment of the disclosure, the transmission links include three paths, i.e., N is 3, and the three transmission links are used for transmission, reception, and feedback, respectively; each transmission link may include multiple sub-links. Figure 2 As shown in the embodiments of this disclosure, the transmission link includes three paths: a transmitting path, a receiving path, and a feedback path, and each transmission link includes two sub-links. The two sub-links in each transmission link are the first sub-link and the second sub-link; the radio frequency (RF) signal transmitted by the first sub-link is orthogonal to the RF signal transmitted by the second sub-link. It is understood that before the RF signal enters the data front-end processing device, the RF signal is vector-decomposed, breaking down the original single RF signal into two vector signals with the same frequency and peak amplitude but a 90-degree phase difference. These vector signals are then transmitted through the first and second sub-links respectively. For example, using IQ modulation, the data can be divided into two paths, each modulated by a carrier, with the two carriers being orthogonal to each other. I stands for In-phase, and Q stands for Quadrature. IQ modulation divides the signal input to the filter into two paths for modulation. In the embodiments of this disclosure, the RF signal transmitted by the first sub-link is an in-phase signal, and the RF signal transmitted by the second sub-link is a quadrature signal. Throughout the entire signal transmission and reception process, the radio frequency (RF) signal needs to be converted from an analog signal to a digital signal. Therefore, unless otherwise specified, the RF signal in this document is a digital signal. The transmission link can be changed in actual configuration. This disclosure uses IQ modulation as a preferred embodiment, but other modulation methods are also possible. There can be one or more sub-links. The specific structure of each sub-link in the embodiments of this disclosure, when the sub-link is a transmitting link, a receiving link, and a feedback link, is described below.

[0069] First example: such as Figure 3 As shown, when the sub-link is a transmission link, the transmission link includes not only the equalizer 10 mentioned above, but also the signal compensation unit 13 and / or the DC offset compensation unit 14. In this embodiment of the disclosure, the transmission link includes both the signal compensation unit 13 and the DC offset compensation unit 14 as an example.

[0070] The signal compensation unit 13 is configured to perform initial compensation on the radio frequency signal and send it to the equalizer 10. Simultaneously, the signal compensation unit 13 is multiplexed as the channel evaluation unit 12 in the transmission link, meaning that the signal compensation unit 13 can evaluate the channel.

[0071] Specifically, the signal compensation unit 13 has an input signal terminal, an output signal terminal, and a feedback signal terminal. The input signal terminal of the signal compensation unit 13 is used to receive radio frequency signals and serves as the signal input terminal of the digital front-end processing device. The output signal terminal of the signal compensation unit 13 is connected to the equalizer 10, and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11. The input signal terminal of the signal compensation unit 13 receives radio frequency signals, performs initial compensation on the received radio frequency signals, and sends the compensated radio frequency signals to the equalizer 10. Simultaneously, it performs channel evaluation based on the compensated radio frequency signals and outputs the channel evaluation results to the microprocessor 11 through the feedback signal terminal.

[0072] The DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal filtered by the equalizer 10 and send the DC offset compensated radio frequency signal.

[0073] Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal. The input signal terminal of the DC offset compensation unit 14 is connected to the equalizer 10, and the output signal terminal of the DC offset compensation unit 14 serves as the output signal terminal of the digital front-end processing device.

[0074] The reason for setting up the DC offset compensation unit 14 is that the amplitude of the RF signal output by the equalizer 10 after filtering according to the filtering coefficient sent by the microprocessor 11 will decrease to a certain extent. Therefore, the DC offset compensation unit 14 is needed to compensate for the decreased signal amplitude, so that the overall signal amplitude can be increased and the compensated RF signal can be sent out of the digital front-end processing device.

[0075] Second example: such as Figure 4 As shown, when the sub-link is a receiving link, the receiving link includes not only the equalizer 10 mentioned above, but also the DC offset compensation unit 14 and / or the signal compensation unit 13. In this embodiment of the disclosure, the receiving link includes both the signal compensation unit 13 and the DC offset compensation unit 14 as an example.

[0076] The DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit 12.

[0077] Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal. The input signal terminal of the DC offset compensation unit 14 serves as the input signal terminal of the digital front-end processing device, and the output signal terminal of the DC offset compensation unit 14 is connected to the channel evaluation unit 12.

[0078] The reason for setting up the DC offset compensation unit 14 is that during the signal reception process, the signal received by the antenna may be subject to certain losses, and its amplitude will decrease to a certain extent. Therefore, it is necessary to use the DC offset compensation unit 14 to compensate for the decreased signal amplitude, so as to increase the overall signal amplitude and transmit the compensated radio frequency signal to the channel evaluation unit 12.

[0079] Specifically, the channel evaluation unit 12 has an input signal terminal, an output signal terminal, and a feedback signal terminal. The input signal terminal of the signal compensation unit 13 is used to receive the radio frequency signal compensated by the DC offset compensation unit 14. The output signal terminal of the signal compensation unit 13 is connected to the equalizer 10, and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11. The channel evaluation unit 12 performs channel evaluation based on the received radio frequency signal compensated by the DC offset compensation unit 14, transmits the evaluated radio frequency signal to the equalizer 10 through the output signal terminal, and simultaneously generates a channel evaluation result, which is sent to the microprocessor 11 through the feedback signal terminal.

[0080] The signal compensation unit 13 is configured to perform tracking compensation on the radio frequency and send the tracked and compensated radio frequency signal.

[0081] Specifically, the signal compensation unit 13 has an input signal terminal and an output signal terminal. The input signal terminal of the signal compensation unit 13 is connected to the equalizer 10, and the output signal terminal of the signal compensation unit 13 is used to transmit radio frequency signals as the signal output signal terminal of the digital front-end processing device.

[0082] The reason for setting up the signal compensation unit 13 is that the amplitude of the radio frequency signal output by the equalizer 10 after filtering according to the filtering coefficient sent by the microprocessor 11 will fluctuate to a certain extent. Therefore, it is necessary to use the signal compensation unit 13 to compensate for the excessively high or low signal amplitude, so that the overall signal amplitude tends to be stable, and then send the compensated radio frequency signal out of the digital front-end processing device.

[0083] The third example: such as Figure 5 As shown, when the sub-link is a feedback link, the feedback link includes not only the equalizer 10 mentioned above, but also the DC offset compensation unit 14 and / or the signal compensation unit 13. In this embodiment of the disclosure, the feedback link includes both the signal compensation unit 13 and the DC offset compensation unit 14 as an example.

[0084] The DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit 12.

[0085] Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal. The input signal terminal of the DC offset compensation unit 14 serves as the input signal terminal of the digital front-end processing device, and the output signal terminal of the DC offset compensation unit 14 is connected to the channel evaluation unit 12.

[0086] The DC offset compensation unit 14 is provided because during signal reception, the signal received by the antenna may suffer some loss, resulting in a decrease in amplitude. Therefore, the DC offset compensation unit 14 is needed to compensate for this decrease in signal amplitude, increasing the overall signal amplitude before transmitting the compensated RF signal to the channel evaluation unit 12. Specifically, the channel evaluation unit 12 has an input signal terminal, an output signal terminal, and a feedback signal terminal. The input signal terminal of the signal compensation unit 13 receives the RF signal compensated by the DC offset compensation unit 14. The output signal terminal of the signal compensation unit 13 is connected to the equalizer 10, and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11. The channel evaluation unit 12 performs channel evaluation based on the received RF signal compensated by the DC offset compensation unit 14, transmits the evaluated RF signal to the equalizer 10 through the output signal terminal, and simultaneously generates a channel evaluation result, which is sent to the microprocessor 11 through the feedback signal terminal.

[0087] The signal compensation unit 13 is configured to perform tracking compensation on the radio frequency and send the tracked and compensated radio frequency signal.

[0088] Specifically, the signal compensation unit 13 has an input signal terminal and an output signal terminal. The input signal terminal of the signal compensation unit 13 is connected to the equalizer 10, and the output signal terminal of the signal compensation unit 13 is used to transmit radio frequency signals as the signal output signal terminal of the digital front-end processing device.

[0089] The reason for setting up the signal compensation unit 13 is that the amplitude of the radio frequency signal output by the equalizer 10 after filtering according to the filtering coefficient sent by the microprocessor 11 will fluctuate to a certain extent. Therefore, it is necessary to use the signal compensation unit 13 to compensate for the excessively high or low signal amplitude, so that the overall signal amplitude tends to be stable, and then send the compensated radio frequency signal out of the digital front-end processing device.

[0090] It should be noted that the above-mentioned filter coefficient can be a single data point or a set of data points. When the filter coefficient is a set of data points, the number of coefficients included in the set of data points is related to the filter order implemented by the equalizer 10 and the actual use of the product. No further restrictions are made here on the form of the filter coefficients or the specific number of coefficients included.

[0091] In some examples, regardless of which sub-link is in the previous case, the equalizer 10 in this embodiment may specifically include a time-domain synchronization module, a storage module, and a filtering module. The time-domain synchronization module is configured to synchronize the equalizer 10 with the time domain of the microprocessor 11 by receiving a time-domain synchronization signal from the microprocessor 11. The storage module is configured to receive and store filter coefficient data by detecting edge changes of the request signal sent by the microprocessor 11. The filtering module is configured to filter the radio frequency signal according to the filter coefficients stored in the storage module under the control of an enable signal. The microprocessor 11 sends a request signal to the equalizer 10, but the clock domains of the equalizer 10 and the microprocessor 11 are different. Therefore, it is necessary to adjust the clock domains of the equalizer 10 and the microprocessor 11 to be consistent. Typically, the first and second request signals sent by the microprocessor 11 are used as clock synchronization signals to synchronize the clock domains of the equalizer 10 and the microprocessor 11. After the clock domains of equalizer 10 and microprocessor 11 are synchronized, equalizer 10 can receive request signals from microprocessor 11. Microprocessor 11 sends request signals to equalizer 10. When equalizer 10 detects an edge change in the request signal, microprocessor 11 sends filter coefficient data to equalizer 10. After receiving the filter coefficient data, equalizer 10 stores the filter coefficients in its register. The aforementioned edge change can be understood as equalizer 10 receiving the filter coefficient data sent by the control unit when it detects the request signal changing from 1 to 0 or from 0 to 1. The aforementioned register only serves as a buffer. After equalizer 10 uses the stored filter coefficients to process the RF signal, the stored filter coefficients become invalid. When filtering is needed again, new filter coefficients will be stored, and equalizer 10 can directly load the newly stored filter coefficients. Under the control of the enable signal, the filtering module automatically filters the RF signal according to the filter coefficients stored in the storage module. The edge detection method of the equalizer 10 for the requested signal can reduce the difficulty of software design for the microprocessor 11, and also eliminate the need to add a counter to the equalizer 10, thus reducing the complexity of the device.

[0092] It should be noted that the received, transmitted, and feedback signals are continuous signals. During reception, the signal quality is affected by variations in the distance between the external signal source and the receiving device, as well as the signal propagation environment. Similarly, during transmission, the distance to the target object and the actual environment also vary, necessitating adjustments to the transmitted signal. The radio frequency (RF) signal enters the digital front-end processing device as a continuous signal. As the RF signal passes through the digital front-end processing device, continuous filtering, equalization, and compensation are unnecessary. The channel evaluation unit 12 or the signal compensation unit 13 evaluates the channel to determine whether compensation is required. Therefore, a request signal is needed to instruct the equalizer 10, and different filter coefficients are applied to the equalizer 10 depending on the situation. When filtering, compensation, and equalization of the RF signal are not required, the equalizer 10 can be skipped, as can the signal compensation unit 13 and the DC offset compensation unit 14, thereby reducing power consumption.

[0093] In some examples, the equalizer 10 includes a first accumulator, a multiplier, a second accumulator, a first arithmetic unit, and a second arithmetic unit. The first accumulator is configured to receive a radio frequency (RF) signal and accumulate a portion of the RF signal. The multiplier is used to perform multiplication calculations on the RF signal input to the filtering module and the filter coefficients. The second accumulator is configured to accumulate the result output by the multiplier. The first arithmetic unit is configured to perform rounding operations on the RF signal output by the second accumulator and transmit the calculation result to the second arithmetic unit. The second arithmetic unit is configured to perform saturation operations on the RF signal output by the first arithmetic unit to obtain the final filtering result of the equalizer 10. In this embodiment, taking the equalizer 10 as a tenth-order low-pass filter as an example, the RF signal already converted into a data signal includes X1-X... 10 Each signal data is sequentially input into the accumulator; each signal corresponds to a filter coefficient, and the filter coefficients input to equalizer 10 are A1-A1. 10 Because its filter coefficients are symmetrical in the middle and equal at both ends, that is, A1 = A 10 A2 = A9, A3 = A8, A4 = A7, and A5 = A6. Therefore, only five filter coefficients are needed in microprocessor 11: Y1, Y2, Y3, Y4, and Y5. The signal processing flow of equalizer 10 is as follows:

[0094] S1: Accumulate the radio frequency signal, X1 + X 10 , X2+X9, X3+X8, X4+X7, X5+X6.

[0095] S2: Multiply the accumulated result by the filter coefficients, Y1×(X1+X 10), Y2×(X2+X9), Y3×(X3+X8), Y4×(X4+X7), Y5×(X5+X6).

[0096] S3: The five sets of data after multiplication are summed again to obtain the result after RF signal filtering.

[0097] The calculation method implemented by the above modules reduces complex calculation steps compared to directly multiplying the RF signal by the filter coefficients and then accumulating the results. Furthermore, in the final accumulation process, the above process only requires accumulating five data points, while directly multiplying the RF signal by the filter coefficients yields ten data points; therefore, the final accumulation process is more optimized. It should be noted that the number of signal data points and the filter order corresponding to equalizer 10 can be adjusted according to the actual signal and usage conditions.

[0098] Since radio frequency (RF) signals are digital signals in digital front-end processing devices, they are processed as data. The first processing unit further processes the data output from the second accumulator. When the data bit width of the signal output from the second accumulator is too large, it reduces part of the data bit width to reduce power consumption. The second processing unit sets the signal range; specifically, it sets the maximum and minimum values ​​for the signal data bit width to further compensate for the RF signal, preventing the received or transmitted RF signal from being too large or too small.

[0099] Secondly, embodiments of this disclosure provide a signal processing method for a digital front-end processing device, such as... Figure 6 As shown, the device includes processing radio frequency signals transmitted through N transmission links between the baseband and the antenna unit using any of the aforementioned digital front-end processing devices; wherein, the processing of radio frequency signals transmitted through any sub-link of each of the N transmission links includes:

[0100] S01, the microprocessor 11 evaluates the transmission channel of the radio frequency signal through the channel evaluation unit 12, generates evaluation results, and feeds back the evaluation results to the microprocessor 11.

[0101] S02, the microprocessor 11 obtains the corresponding filter coefficients based on the channel evaluation results and the pre-stored correspondence between the channel evaluation results and the filter coefficients, and sends them to the equalizer 10.

[0102] S03 and equalizer 10 filter the radio frequency signal according to the filtering coefficient.

[0103] This method combines analog circuitry with software to perform filtering, compensation, and equalization on radio frequency (RF) signals. This reduces the complexity of these operations and improves signal processing performance. Furthermore, when the equalizer 10 is used as a low-pass filter, it solves the problem of amplitude roll-off during low-pass filtering, thus improving the signal quality of the final processed RF signal.

[0104] In this embodiment of the disclosure, the transmission link includes three paths, i.e., N is 3, namely the sending path, the receiving path, and the feedback path, and each transmission link includes two sub-links for illustration.

[0105] In this embodiment, the sub-link may include a transmit link, a receive link, and a feedback link. The signal processing methods for the receive link and the feedback link are the same; the following description uses the example of a sub-link including both a transmit link and a receive link to illustrate the signal processing methods.

[0106] First example: Figure 7 As shown, when the sub-link is a transmission link, the sub-link includes a signal compensation unit 13, an equalizer 10, and a DC offset compensation unit 14; wherein, the signal compensation unit 13 is multiplexed as the channel evaluation unit 12 in the transmission link. The method specifically includes the following steps:

[0107] S11, Signal compensation unit 13 receives radio frequency signals and performs initial compensation on the radio frequency signals.

[0108] It should be noted that the radio frequency signal received by the signal compensation unit 13 in step S11 is a digital signal. In some examples, the signal compensation unit 13 receives the radio frequency signal and performs initial compensation on the radio frequency signal, including: the signal compensation unit 13 performs initial compensation on the amplitude of the received signal, and compensates for the signal parts of the radio frequency signal with excessively high or low amplitude, so that the overall amplitude of the radio frequency signal tends to be stable.

[0109] S12, the signal compensation unit 13 performs channel evaluation based on the initially compensated radio frequency signal and feeds back the channel evaluation result to the microprocessor 11, while sending the initially compensated radio frequency signal to the equalizer 10.

[0110] S13, the microprocessor 11 determines the corresponding filtering coefficients based on the channel evaluation results fed back by the signal compensation unit 13 and the correspondence between the channel evaluation results and filtering coefficients stored in the microprocessor 13, and sends them to the equalizer 10.

[0111] In some examples, the pre-stored correspondence between channel evaluation results and filter coefficients in step S13 can be a mapping table or a preset algorithm, that is, the filter coefficients are calculated based on the channel evaluation results using the corresponding algorithm.

[0112] S14. The equalizer 10 compensates the radio frequency signal according to the filtering coefficients determined by the microprocessor 11.

[0113] In some examples, equalizer 10 includes a time-domain synchronization module, a storage module, and a filtering module. For example... Figure 8 As shown, step S14 may specifically include:

[0114] S141, the time-domain synchronization module synchronizes its own time domain with the time domain of the microprocessor 11 by receiving the time-domain synchronization signal sent by the microprocessor 11.

[0115] S142. Receive the request signal sent by the microprocessor 11, and upon detecting an edge change in the request signal from the microprocessor 11, receive the microprocessor filter coefficients and store them in the storage module.

[0116] It should be noted that the storage only serves as a buffer. When the equalizer 10 uses the stored filter coefficients to process the RF signal, the stored filter coefficients will become invalid. When filtering is needed again, new filter coefficients will be stored, and the equalizer 10 can then directly load the newly stored filter coefficients.

[0117] S143. Under the control of the enable signal, the filtering module filters the radio frequency signal according to the filtering coefficients stored in the storage module.

[0118] It should be noted that the reason why the filtering module needs to perform filtering control under the control of the enable signal is that the radio frequency signal is a continuous signal during transmission. It is not necessary to filter this continuous signal all the time. The equalizer 10 only needs to perform filtering processing when there are specific situations or when the radio frequency signal needs to be adjusted. Therefore, by setting an enable signal, the equalizer 10 can be turned off when it is not needed for a long time, so as to stop the equalizer 10 from working and reduce the power consumption of the entire digital front-end processing device.

[0119] In some examples, the filtering module may include a first adder, a multiplier, a second adder, a first arithmetic unit, and a second arithmetic unit. For example... Figure 9 As shown, step S143 may specifically include:

[0120] S1431, The radio frequency signal received at the input signal terminal of the equalizer 10 is accumulated for the first time in the first accumulator. For example, the first and last signals are accumulated in pairs.

[0121] S1432, The multiplier performs a multiplication operation between the filter coefficients loaded into the equalizer 10 and the RF signal after the first accumulation.

[0122] S1433, the second accumulator accumulates the RF signal after the multiplication operation again to obtain an RF signal.

[0123] S1434, The first arithmetic unit performs rounding operation on the radio frequency signal after the above steps.

[0124] S1435, the second arithmetic unit performs saturation operation on the RF signal after the above steps and obtains the final RF signal filtered by the equalizer 10.

[0125] It should be noted that the first and second arithmetic units are used to limit the bit width of the radio frequency (RF) signal converted into a mathematical signal. Rounding operations process RF signals exceeding a certain limit, reducing their bit width and decreasing device power consumption. Saturation operations further limit the bit width range of the RF signal, processing RF signals with excessively high or low bit widths to control the bit width within a certain range. In this embodiment, the bit width of the RF signal is not further limited; those skilled in the art can adjust it according to actual usage.

[0126] S15, DC offset compensation unit 14 performs DC offset compensation on the radio frequency signal filtered by equalizer 10, and sends the DC offset compensated radio frequency signal.

[0127] In some examples, step S15 may specifically include: the DC offset compensation unit 14 compensates for the amplitude of the filtered RF signal, increasing its amplitude to a certain extent before outputting it. The reason for amplitude compensation is that the RF signal output by the equalizer 10 after filtering according to the filtering coefficients sent by the microprocessor 11 will experience a certain decrease in amplitude. Therefore, the DC offset compensation unit 14 needs to compensate for the decreased signal amplitude, increasing the overall signal amplitude, and then using the compensated RF signal as the output of the digital front-end processing device.

[0128] The second example: When the sub-link is a receiving link, it includes a DC offset compensation unit 14, a channel evaluation unit 12, an equalizer 10, and a signal compensation unit 13. For example... Figure 10 As shown, the method specifically includes the following steps:

[0129] S21, DC offset compensation unit 14 performs DC offset compensation on radio frequency signals.

[0130] In some examples, step S21 may specifically include: the DC offset compensation unit 14 performs DC offset compensation on the amplitude of the radio frequency signal, thereby increasing its amplitude to a certain extent. The reason for compensating the amplitude is that during signal reception, the signal received by the antenna may suffer some loss, and its amplitude will decrease to a certain extent. Therefore, the DC offset compensation unit 14 is needed to compensate for the decreased signal amplitude, thereby increasing the overall signal amplitude. After that, the radio frequency signal after DC offset compensation is transmitted to the channel evaluation unit 12.

[0131] S22, the channel evaluation unit 12 performs channel evaluation based on the DC offset compensated radio frequency signal and feeds back the channel evaluation result to the microprocessor 11, while sending the DC offset compensated radio frequency signal to the equalizer 10.

[0132] S23, the microprocessor 11 determines the corresponding filtering coefficients based on the channel evaluation results fed back by the channel evaluation unit 12 and the correspondence between the channel evaluation results and filtering coefficients stored in the microprocessor 11, and sends them to the equalizer 10.

[0133] In some examples, the pre-stored correspondence between channel evaluation results and filter coefficients in step S23 can be a mapping table or a preset algorithm, that is, the filter coefficients are calculated based on the channel evaluation results using the corresponding algorithm.

[0134] S24. The equalizer 10 compensates the radio frequency signal according to the filtering coefficients determined by the microprocessor 11.

[0135] In some examples, equalizer 10 includes a time-domain synchronization module, a storage module, and a filtering module. For example... Figure 11 As shown, step S14 may specifically include:

[0136] S241, the time-domain synchronization module synchronizes its own time domain with the time domain of the microprocessor 11 by receiving the time-domain synchronization signal sent by the microprocessor 11.

[0137] S242. Receive the request signal sent by the microprocessor 11, and upon detecting an edge change in the request signal from the microprocessor 11, receive the microprocessor filter coefficients and store them in the storage module.

[0138] It should be noted that the storage only serves as a buffer. When the equalizer 10 uses the stored filter coefficients to process the RF signal, the stored filter coefficients will become invalid. When filtering is needed again, new filter coefficients will be stored, and the equalizer 10 can then directly load the newly stored filter coefficients.

[0139] S243. Under the control of the enable signal, the filtering module filters the radio frequency signal according to the filtering coefficients stored in the storage module.

[0140] It should be noted that the reason why the filtering module needs to perform filtering control under the control of the enable signal is that the radio frequency signal is a continuous signal during transmission. It is not necessary to filter this continuous signal all the time. The equalizer 10 only needs to perform filtering processing when there are specific situations or when the radio frequency signal needs to be adjusted. Therefore, by setting an enable signal, the equalizer 10 can be turned off when it is not needed for a long time, so as to stop the equalizer 10 from working and reduce the power consumption of the entire digital front-end processing device.

[0141] In some examples, the filtering module may include a first adder, a multiplier, a second adder, a first arithmetic unit, and a second arithmetic unit. For example... Figure 12 As shown, step S243 may specifically include:

[0142] The radio frequency signal received at the input signal terminal of equalizer 10 (S2431) is accumulated for the first time in the first accumulator. For example, the first and last signals are accumulated in pairs.

[0143] S2432, the multiplier performs a multiplication operation between the filter coefficients loaded into equalizer 10 and the RF signal after the first accumulation.

[0144] S2433, the second accumulator accumulates the RF signal after the multiplication operation again to obtain an RF signal.

[0145] S2434, The first arithmetic unit performs rounding operation on the radio frequency signal after the above steps.

[0146] S2435, the second arithmetic unit performs saturation operation on the RF signal after the above steps and obtains the final RF signal filtered by the equalizer 10.

[0147] It should be noted that the first and second arithmetic units are used to limit the bit width of the radio frequency (RF) signal converted into a mathematical signal. Rounding operations process RF signals exceeding a certain limit, reducing their bit width and decreasing device power consumption. Saturation operations further limit the bit width range of the RF signal, processing RF signals with excessively high or low bit widths to control the bit width within a certain range. In this embodiment, the bit width of the RF signal is not further limited; those skilled in the art can adjust it according to actual usage.

[0148] S25, Signal compensation unit 13 receives radio frequency signals and performs tracking compensation on the radio frequency signals.

[0149] It should be noted that the radio frequency signal received by the signal compensation unit 13 in step S25 is a digital signal. In some examples, the signal compensation unit 13 receives the radio frequency signal and performs tracking compensation on the radio frequency signal, including: the signal compensation unit 13 performs tracking compensation on the amplitude of the received signal, compensates for the signal portion of the radio frequency signal with excessively high or low amplitude, so that the overall amplitude of the radio frequency signal tends to be stable, and uses the compensated radio frequency signal as the output of the digital front-end processing device.

[0150] Thirdly, this disclosure also provides an antenna device including any of the aforementioned digital front-end processing devices. The antenna device further includes a baseband and antenna units; the baseband and antenna units are connected via N transmission links, each transmission link being equipped with a digital front-end processing device. Each antenna unit may include N antenna modules, and the N antenna modules are connected one-to-one with the N transmission links.

[0151] Since the antenna device in this embodiment includes any of the aforementioned digital front-end processing devices, analog circuits can be combined with software to implement filtering, compensation, and equalization operations on radio frequency signals. This reduces the difficulty of filtering, compensating, and equalizing radio frequency signals and improves the signal processing effect. Furthermore, when the equalizer is used as a low-pass filter, it also solves the problem of amplitude roll-off during low-pass filtering of the radio frequency signal, improving the signal quality of the final processed radio frequency signal.

[0152] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A digital front-end processing apparatus configured to process radio frequency signals transmitted via N transmission links between a baseband and an antenna element, where N ≥ 1 and N is an integer; the N transmission links include a transmit link, a receive link, and a feedback link; each of the transmit link, the receive link, and the feedback link includes at least one sub-link; wherein, The sub-link is equipped with an equalizer and a channel evaluation unit; the digital front-end processing device also includes a microprocessor. For any of the sub-links, the channel evaluation unit thereon is configured to evaluate the transmission channel of the received radio frequency signal and feed the evaluation result back to the microprocessor so that the microprocessor determines the filtering coefficients based on the evaluation result; the equalizer is configured to filter the radio frequency signal based on the filtering coefficients determined by the microprocessor. The transmission link includes a signal compensation unit, which is configured to perform initial compensation on the radio frequency signal and send it to the equalizer, and the signal compensation unit is multiplexed as the channel evaluation unit in the transmission link; The transmission link further includes a DC offset compensation unit; the DC offset compensation unit is configured to perform DC offset compensation on the equalizer-filtered radio frequency signal and transmit the DC offset-compensated radio frequency signal. The equalizer includes a time-domain synchronization module, a storage module, and a filtering module; The time-domain synchronization module is configured to synchronize the equalizer with the time domain of the microprocessor based on the received time-domain synchronization signal from the microprocessor, wherein the first two request signals from the microprocessor are used as the time-domain synchronization signal. The storage module is configured to receive and store the filter coefficients sent by the microprocessor when detecting edge changes in the request signal sent by the microprocessor. The filtering module is configured to filter the radio frequency signal according to the filtering coefficients stored in the storage module under the control of the enable signal. The filtering module utilizes the symmetry of the filtering coefficients to sum the first and last signals pairwise and then multiply them by the filtering coefficients.

2. The digital front-end processing apparatus according to claim 1, wherein, The receiving link also includes a DC offset compensation unit; The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

3. The digital front-end processing apparatus according to claim 2, wherein, The receiving link includes a signal compensation unit. The signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracked and compensated radio frequency signal.

4. The digital front-end processing apparatus according to claim 1, wherein, The feedback link also includes a DC offset compensation unit; The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

5. The digital front-end processing apparatus according to claim 4, wherein, The feedback link also includes a signal compensation unit; The signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracked and compensated radio frequency signal.

6. The digital front-end processing apparatus according to any one of claims 1-5, wherein, The filtering module includes a first accumulator, a multiplier, a second accumulator, a first arithmetic unit, and a second arithmetic unit; The first accumulator is configured to receive radio frequency signals and accumulate a portion of the radio frequency signals; The multiplier is used to multiply the radio frequency signal input to the filtering module with the filtering coefficients. The second accumulator is configured to accumulate the output of the multiplier; The first arithmetic unit is configured to perform a rounding operation on the radio frequency signal output by the second accumulator and transmit the calculation result to the second arithmetic unit; The second arithmetic unit is configured to perform saturation calculation on the radio frequency signal output by the first arithmetic unit and then output it.

7. The digital front-end processing apparatus according to claim 1, wherein, The transmission link includes two sub-links, namely a first sub-link and a second sub-link; the radio frequency signal transmitted by the first sub-link is orthogonal to the radio frequency signal transmitted by the second sub-link.

8. A signal processing method for a digital front-end processing device, wherein, The signal processing method of the digital front-end processing device includes processing radio frequency signals transmitted through N transmission links between the baseband and the antenna unit using the digital front-end processing device according to any one of claims 1-7; the N transmission links include a transmitting link, a receiving link, and a feedback link; the transmitting link, the receiving link, and the feedback link; wherein, the processing of radio frequency signals transmitted through any sub-link of each of the N transmission links includes: The channel evaluation unit evaluates the transmission channel of the received radio frequency signal and feeds back the evaluation result to the microprocessor. The microprocessor determines the filtering coefficients based on the evaluation results; The equalizer filters the radio frequency signal according to the filtering coefficients determined by the microprocessor; Before the equalizer filters the radio frequency signal, the following steps are also included: The signal compensation unit performs initial compensation on the radio frequency signal and sends it to the equalizer. The signal compensation unit is also multiplexed as the channel evaluation unit in the transmission link to perform the channel evaluation. After the equalizer filters the radio frequency signal, the following steps are also included: The DC offset compensation unit performs DC offset compensation on the equalizer-filtered RF signal and then transmits the DC offset-compensated RF signal. The process by which the equalizer performs filtering based on the filtering coefficients includes: The equalizer is synchronized with the microprocessor in the time domain by means of a time domain synchronization module based on a time domain synchronization signal issued by the microprocessor; wherein the first two request signals issued by the microprocessor are used as the time domain synchronization signal. When the storage module detects an edge change in the request signal sent by the microprocessor, it receives and stores the filter coefficients sent by the microprocessor. Under the control of the enable signal, the filtering module filters the radio frequency signal according to the stored filtering coefficients. The filtering module utilizes the symmetry of the filtering coefficients to sum the first and last signals in pairs and then multiply them by the filtering coefficients.

9. The signal processing method of the digital front-end processing device according to claim 8, wherein, The receiving link includes a DC offset compensation unit; and before the equalizer filters the RF signal, it further includes: The DC offset compensation unit performs DC offset compensation on the radio frequency signal and sends it to the channel evaluation unit. The channel evaluation unit performs channel evaluation on the radio frequency signal received by the input signal terminal and transmits the radio frequency signal to the equalizer through the output signal terminal. At the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

10. The signal processing method of the digital front-end processing device according to claim 9, wherein, After the equalizer filters the radio frequency signal, the following steps are also included: The radio frequency signal is tracked and compensated by the signal compensation unit, and the tracked and compensated radio frequency signal is then transmitted.

11. The signal processing method of the digital front-end processing device according to claim 8, wherein, The sub-link is a feedback link; the feedback link includes a DC offset compensation unit; and before the equalizer filters the RF signal, it further includes: The DC offset compensation unit performs DC offset compensation on the radio frequency signal and sends it to the channel evaluation unit. The channel evaluation unit performs channel evaluation on the radio frequency signal received by the input signal terminal and transmits the radio frequency signal to the equalizer through the output signal terminal. At the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

12. The signal processing method of the digital front-end processing device according to claim 11, wherein, The feedback link further includes a signal compensation unit; and after the equalizer filters the radio frequency signal, it further includes: The radio frequency signal is tracked and compensated by the signal compensation unit, and the tracked and compensated radio frequency signal is then transmitted.

13. An antenna device, wherein, The antenna device includes the digital front-end processing apparatus according to any one of claims 1-7.

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