Encoding and decoding method, system and terminal for simulating HDLC protocol through SPI and storage medium

Abstract

The application relates to the field of information technology, in particular to a coding and decoding method, system, terminal and storage medium for simulating an HDLC protocol through SPI. The method comprises the following steps: when a host controller needs to send data, first sending high-layer data to a sending protocol stack; the sending protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the coded data through SPI, and sends the binary code through DMA to complete data sending; when the host controller needs to receive data, receiving the data through the DMA mode of SPI, and cyclically executing a receiving protocol stack; according to a characteristic value, finding a frame header and a start flag of the data, continuously converting SPI data into binary code and byte data, until a timeout or a frame tail is received, and finally sending the byte data to a high layer.

Description

Technical Field

[0001] This invention relates to the field of information technology, and in particular to a method, system, terminal, and storage medium for encoding and decoding HDLC protocol emulated via SPI. Background Technology

[0002] HDLC (High-Level Data Link Control) is an international standard link layer protocol defined by ISO / IEC 13239, used to enable resource sharing and information exchange between remote users. HDLC is also a bit-oriented, high-efficiency link layer protocol. In this type of bit-oriented data link protocol, the frame header and trailer are specific binary sequences. Control fields are used to monitor the link, and various encoding methods can be used to achieve efficient, reliable, and transparent transmission. HDLC ensures that data transmitted to the next layer is accurately received during transmission, meaning there is no loss during error handling and the sequence is correct. Another important function of HDLC is flow control, which allows the receiving end to immediately transmit data once it is received.

[0003] In ETC applications, the main controller transmits data to the radio frequency front-end via the HDLC interface to wirelessly transmit the data at 5.8GHz. The radio frequency front-end then sends the received 5.8GHz wireless data back to the main controller via the HDLC link to complete data reception. In existing technologies, the HDLC link acts as the bridge for wireless communication, responsible for data encoding and decoding, flow control, and error correction. Using a hardware HDLC controller allows direct acquisition of the final data from the HDLC without additional work. However, on the one hand, there are very few control chips with hardware HDLC interfaces, resulting in a very narrow selection of control chips and necessitating trade-offs between performance and interface. On the other hand, because hardware HDLC controllers have high requirements for data timing—the binary sequence must be free of interfering pulses, and the number of specific binary sequences in the frame header and tail is strictly limited—the hardware HDLC controller experiences a high failure rate and inflexible decoding when parsing irregular codes, thus significantly reducing the reliability and real-time performance of the entire system. Summary of the Invention

[0004] To address the technical problems existing in the prior art, this invention provides a method, system, terminal, and storage medium for encoding and decoding HDLC protocol simulated by SPI. This solves the problem of inflexibility and low decoding accuracy caused by the use of dedicated hardware HDLC interface for encoding and decoding between the main controller and the radio frequency chip in the ETC system. It also solves the problem of difficulty in selecting the main controller.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions: In a first aspect, in one embodiment of the present invention, a method for encoding and decoding the HDLC protocol by simulating SPI is provided, the method comprising the following steps: When the main controller needs to send data, it first sends the higher-level data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. When the main controller needs to receive data, it uses the DMA mode of SPI to receive data. The receive protocol stack executes in a loop, finds the frame header and start flag of the data according to the feature value, and continues to convert the SPI data into binary code and bytecode until timeout or the end of the frame is received. Finally, the byte data is sent to the higher layer.

[0006] As a further aspect of the present invention, the sending protocol stack first serializes the data to obtain serialized data, and before that, it also includes adding 2 bytes of CRC verification to the end of the received data.

[0007] As a further aspect of the present invention, the step of converting serialized data into binary encoding further includes adding a start flag, an end flag, a frame header, and a frame tail to the binary encoding.

[0008] As a further aspect of the present invention, the step of sampling and encoding data via SPI and transmitting the binary encoding via DMA includes the following steps: The SPI samples the binary bitstream. Based on the SPI baud rate of 4M, each bitstream is converted into 1 byte after SPI sampling, and a new byte sequence is generated after sampling. DMA sends data, initializes the SPI controller and DMA function, and sends out the byte sequence via DMA.

[0009] As a further aspect of the present invention, the method of receiving data using the DMA mode of SPI further includes: SPI controller and DMA initialization, and setting the baud rate of the SPI controller to 8M; Set the DMA to circular receive mode, the receive buffer to 128 bytes, and set it to half-full and full interrupts.

[0010] As a further aspect of the present invention, the step of finding the frame header and start marker of the data based on the feature values ​​is preceded by the following steps: Find the feature value of frame header 1: In the received data, search in a loop for the sequence FF 00 FF 00FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 ; Data serialization: Convert the byte stream after frame header 1 into a bit stream, and adjust the starting bit of the bit stream according to the position of the 8 0s or 8 1s that appear in the bit stream to reassemble it into a byte stream, which will result in a byte stream that is either FF or 00.

[0011] As a further aspect of the present invention, the step of converting SPI data into binary encoding and byte-based encoding includes the following steps: performing binary inverse encoding, binary inverse encoding, bitstream byte-based encoding, and data CRC check processing on the data in sequence.

[0012] Secondly, in another embodiment provided by the present invention, an encoding and decoding system for simulating the HDLC protocol via SPI is provided, the system comprising: a main controller and a radio frequency front end; The main controller includes an SPI controller; the MISO pin of the SPI controller is connected to the TxD pin of the HDLC of the RF front-end, and the MOSI pin of the SPI controller is connected to the RxD pin of the HDLC of the RF front-end.

[0013] Thirdly, in another embodiment provided by the present invention, a terminal is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of an encoding and decoding method for simulating the HDLC protocol via SPI.

[0014] Fourthly, in another embodiment of the present invention, a storage medium is provided storing a computer program, which, when loaded and executed by a processor, implements the steps of the encoding and decoding method for simulating the HDLC protocol via SPI.

[0015] The technical solution provided by this invention has the following beneficial effects: This invention provides a method, system, terminal, and storage medium for simulating HDLC protocol via SPI, solving the problem of inflexibility and low decoding accuracy in ETC systems where only dedicated hardware HDLC interfaces can be used for encoding and decoding between the main controller and the RF chip. It also addresses the difficulty in selecting a main controller. This invention eliminates the need for a dedicated HDLC hardware interface for the main controller chip; it only requires a standard SPI interface, a requirement that most chips meet.

[0016] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an embodiment of the encoding and decoding method for simulating the HDLC protocol using SPI according to one of the present invention. Figure 2 The transmission protocol stack workflow of an encoding / decoding method for simulating the HDLC protocol via SPI according to an embodiment of the present invention is described below. Figure 3 This describes the receiving protocol stack workflow of an encoding / decoding method for simulating the HDLC protocol via SPI, according to one embodiment of the present invention. Figure 4 This is a block diagram of a codec system for simulating the HDLC protocol via SPI, according to an embodiment of the present invention. Figure 5 This is a diagram of the HDLC data encoding format in an encoding and decoding system that simulates the HDLC protocol via SPI, according to an embodiment of the present invention. Figure 6 This is a terminal structure diagram according to an embodiment of the present invention.

[0019] In the diagram: Processor-301, Communication Interface-302, Memory-303, Communication Bus-304. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0022] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] Specifically, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0024] Please see Figure 1 , Figure 1 This is a flowchart of an encoding and decoding method for simulating the HDLC protocol using SPI, as provided in an embodiment of the present invention. Figure 1 As shown, the encoding and decoding method for simulating the HDLC protocol via SPI includes steps S10 to S20.

[0025] Please see Figure 2 S10. When the main controller needs to send data, it first sends the higher-level data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, and before that, it also includes adding 2 bytes of CRC verification to the end of the received data.

[0026] In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, including: First, convert the byte stream into a bit stream, and then insert a 0 after every 5 bits of 1 to generate a new bit stream. For example, after serialization, 7A9F becomes 01011110 11111000 1.

[0027] In an embodiment of the present invention, converting serialized data into binary code includes: According to the specific encoding format, each 1-bit bitstream is encoded into a 2-bit binary codestream. For example, FM0 encoding encodes 110010 into 001101010010, and Manchester encoding encodes 110010 into 101001011001, generating a new binary codestream.

[0028] In an embodiment of the present invention, the step of converting serialized data into binary code further includes adding a start flag, an end flag, a frame header, and a frame tail to the binary code.

[0029] The addition of start and end markers involves encoding 0x7E in binary and adding it to the beginning and end of the binary code stream.

[0030] The addition of frame headers and frame trailers involves encoding 16 ones and 16 zeros in binary and adding them to the beginning of the binary bitstream, and encoding 8 zeros in binary and adding them to the end of the binary bitstream.

[0031] In an embodiment of the present invention, the step of sampling and encoding data via SPI and sending out the binary encoding via DMA includes the following steps: The SPI samples the binary bitstream. Based on the SPI baud rate of 4M, each bitstream is converted into 1 byte after SPI sampling, and a new byte sequence is generated after sampling. DMA sends data, initializes the SPI controller and DMA function, and sends out the byte sequence via DMA.

[0032] Please see Figure 3 S20. When the main controller needs to receive data, it uses the DMA mode of SPI to receive data. The receiving protocol stack executes in a loop, finds the frame header and start flag of the data according to the feature value, and continues to convert the SPI data into binary code and bytecode until timeout or the end of the frame is received. Finally, the byte data is sent to the higher layer.

[0033] In an embodiment of the present invention, the step of receiving data using the DMA mode of SPI further includes: SPI controller and DMA initialization, and setting the baud rate of the SPI controller to 8M; Set the DMA to circular receive mode, the receive buffer to 128 bytes, and set it to half-full and full interrupts.

[0034] In an embodiment of the present invention, the step of finding the frame header and start marker of the data based on feature values ​​is preceded by the following steps: Find the feature value of frame header 1: In the received data, search in a loop for the sequence FF 00 FF 00FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 ; Data serialization: Convert the byte stream after frame header 1 into a bit stream, and adjust the starting bit of the bit stream according to the position of the 8 0s or 8 1s that appear in the bit stream to reassemble it into a byte stream, which will result in a byte stream that is either FF or 00.

[0035] In an embodiment of the present invention, finding the frame header and start flag of the data based on the feature value includes searching for frame header 2 and the start flag. First, in the new byte stream, search for FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1. Then, search for FF 00 FF FF 00 00 FF FF 00 00 FF FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1 again.

[0036] In an embodiment of the present invention, the step of converting SPI data into binary encoding and byte-based encoding includes the following steps: performing binary inverse encoding, binary inverse encoding, bitstream byte-based encoding, and data CRC check processing on the data in sequence.

[0037] In an embodiment of the present invention, the binary decoding involves generating a new binary code stream by decoding the byte stream generated in step 3 byte by byte. If an FF (Flash) is found, a 1 is inserted into the binary code stream; if a 00 is found, a 0 is inserted. This process continues until 0100110011001101 or its reverse sequence is found in the binary code stream, or the decoding times out. If a byte stream is found to be non-FF or 00 during decoding, special processing is required, and subsequent byte streams are re-serialized before decoding. This process effectively filters out interference and perfectly adapts to the problem of inconsistent received baud rates.

[0038] In an embodiment of the present invention, the binary inverse encoding is to inversely encode every 2 bits in the binary code stream into a 1-bit code stream according to a specific encoding format. For example, FM0 encoding encodes 001101010010 into 110010, and Manchester encoding encodes 101001011001 into 110010, thereby generating a new binary code stream.

[0039] In an embodiment of the present invention, the bitstream byteification is to reorganize the obtained binary bitstream by removing the last 0 after five 1s to obtain a new bitstream, and then reorganizing the bitstream into a bytestream.

[0040] In an embodiment of the present invention, the data CRC check is performed by performing a CRC16 (X16+X12+X5+1) calculation on the data excluding the last two bytes of the byte stream, comparing the result with the last two bytes, and if they are equal, it means that the data is correct. After removing the check, the data is sent to the higher layer.

[0041] This invention reduces reliance on HDLC control equipment and limits chip selection, effectively lowering material costs. It also solves the problems of high decoding failure rates and inflexible decoding in hardware HDLC controllers for non-standard encoding. By simulating FM0 encoding via SPI, software developers can more flexibly preprocess the raw data, such as filtering and error correction, before decoding, improving system fault tolerance and compatibility, and enhancing system real-time performance and reliability.

[0042] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0043] In one embodiment, see Figure 4 As shown, an embodiment of the present invention also provides an encoding and decoding system that simulates the HDLC protocol via SPI, the system including a main controller and a radio frequency front end.

[0044] The main controller includes an SPI controller; the MISO pin of the SPI controller is connected to the TxD pin of the HDLC of the RF front-end, and the MOSI pin of the SPI controller is connected to the RxD pin of the HDLC of the RF front-end.

[0045] The specific signal definitions are shown in Table 1. Table 1 Signal Definitions

[0046] In an embodiment of the present invention, the HDLC frame format includes multiple fields, as shown in the figure.

[0047]

[0048] In an embodiment of the present invention, in the ETC application, the pre-synchronization signal, i.e., the frame header, is changed to 16 '1's and 16 '0's, and the post-synchronization signal, i.e., the frame tail, is changed to 8 bits of '0's.

[0049] In embodiments of the present invention, the HDLC protocol supports multiple data encoding formats, such as NRZ, NRZI, FMO, MANCHESTER, etc., and the corresponding 1s and 0s are not entirely the same for each encoding format, such as... Figure 5 As shown.

[0050] This invention reduces reliance on HDLC control equipment and limits chip selection, effectively lowering material costs. It also solves the problems of high decoding failure rates and inflexible decoding in hardware HDLC controllers for non-standard encoding. By simulating FM0 encoding via SPI, software developers can more flexibly preprocess the raw data, such as filtering and error correction, before decoding, improving system fault tolerance and compatibility, and enhancing system real-time performance and reliability.

[0051] In one embodiment, see Figure 6 As shown, an embodiment of the present invention also provides a terminal, including a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302 and the memory 303 communicate with each other through the communication bus 304.

[0052] Memory 303 is used to store computer programs; When processor 301 executes the computer program stored in memory 303, it executes the encoding and decoding method of simulating HDLC protocol via SPI. When the processor executes instructions, it implements the steps in the above method embodiment: S10. When the main controller needs to send data, it first sends the higher-level data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, and before that, it also includes adding 2 bytes of CRC verification to the end of the received data.

[0053] In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, including: First, convert the byte stream into a bit stream, and then insert a 0 after every 5 bits of 1 to generate a new bit stream. For example, after serialization, 7A9F becomes 01011110 11111000 1.

[0054] In an embodiment of the present invention, converting serialized data into binary code includes: According to the specific encoding format, each 1-bit bitstream is encoded into a 2-bit binary codestream. For example, FM0 encoding encodes 110010 into 001101010010, and Manchester encoding encodes 110010 into 101001011001, generating a new binary codestream.

[0055] The process of converting serialized data into binary code further includes adding a start flag, an end flag, a frame header, and a frame tail to the binary code in sequence.

[0056] The addition of start and end markers involves encoding 0x7E in binary and adding it to the beginning and end of the binary code stream.

[0057] The addition of frame headers and frame trailers involves encoding 16 ones and 16 zeros in binary and adding them to the beginning of the binary bitstream, and encoding 8 zeros in binary and adding them to the end of the binary bitstream.

[0058] The process of sampling and encoding data via SPI and then sending the binary encoded data out via DMA includes: The SPI samples the binary bitstream. Based on the SPI baud rate of 4M, each bitstream is converted into 1 byte after SPI sampling, and a new byte sequence is generated after sampling. DMA sends data, initializes the SPI controller and DMA function, and sends out the byte sequence via DMA.

[0059] S20. When the main controller needs to receive data, it uses the DMA mode of SPI to receive data. The receive protocol stack executes in a loop, finds the frame header and start flag of the data according to the feature value, and continues to convert the SPI data into binary code and bytecode until timeout or the end of the frame is received. Finally, the byte data is sent to the higher layer.

[0060] In an embodiment of the present invention, the step of receiving data using the DMA mode of SPI further includes: initializing the SPI controller and DMA, setting the baud rate of the SPI controller to 8M, setting the DMA to cyclic receive mode, setting the receive buffer to 128 bytes, and setting half-full and full interrupts.

[0061] In an embodiment of the present invention, the step of finding the frame header and start marker of the data based on feature values ​​is preceded by the following steps: Find the feature value of frame header 1: In the received data, search in a loop for the sequence FF 00 FF 00FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 ; Data serialization: Convert the byte stream after frame header 1 into a bit stream, and adjust the starting bit of the bit stream according to the position of the 8 0s or 8 1s that appear in the bit stream to reassemble it into a byte stream, which will result in a byte stream that is either FF or 00.

[0062] In an embodiment of the present invention, finding the frame header and start flag of the data based on the feature value includes searching for frame header 2 and the start flag. First, in the new byte stream, search for FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1. Then, search for FF 00 FF FF 00 00 FF FF 00 00 FF FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1 again.

[0063] In an embodiment of the present invention, the step of converting SPI data into binary encoding and byte-based encoding includes the following steps: performing binary inverse encoding, binary inverse encoding, bitstream byte-based encoding, and data CRC check processing on the data in sequence.

[0064] The binary decoding process involves generating a new binary code stream by decoding the byte stream generated in step 3 byte by byte. If an FF (Flash) is found, a 1 is inserted into the binary code stream; if a 00 is found, a 0 is inserted. This process continues until the binary code stream contains either 0100110011001101 or its reverse sequence, or until a timeout occurs. If a byte stream is found to be non-FF or 00 during decoding, special processing is required, and subsequent byte streams are re-serialized before decoding. This process filters out interference and perfectly adapts to the problem of inconsistent received baud rates.

[0065] The binary inverse encoding is to inversely encode every 2 bits in the binary code stream into a 1-bit code stream according to a specific encoding format. For example, FM0 encoding encodes 001101010010 into 110010, and Manchester encoding encodes 101001011001 into 110010, thus generating a new binary code stream.

[0066] The bitstream byteification involves reorganizing the obtained binary bitstream by removing the last 0 after five 1s to obtain a new bitstream, and then reorganizing the bitstream into a bytestream.

[0067] The data CRC check is performed by calculating CRC16 (X16+X12+X5+1) on the byte stream except for the last two bytes. The result is compared with the last two bytes. If they are equal, the data is correct. After removing the checksum, the data is sent to the higher layer.

[0068] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0069] The communication interface is used for communication between the aforementioned terminal and other devices.

[0070] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0071] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0072] The terminal includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement this invention, or it can connect to a network and interact with other terminals on the network to implement this invention. The network in which the terminal is located includes, but is not limited to, the Internet, wide area network (WAN), metropolitan area network (MAN), local area network (LAN), and VPN network.

[0073] The terminal includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement this invention, or it can connect to a network and interact with other terminals on the network to implement this invention. The network in which the terminal is located includes, but is not limited to, the Internet, wide area network (WAN), metropolitan area network (MAN), local area network (LAN), and VPN network.

[0074] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0075] In one embodiment of the present invention, a storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above method embodiments: S10. When the main controller needs to send data, it first sends the higher-level data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, and before that, it also includes adding 2 bytes of CRC verification to the end of the received data.

[0076] In an embodiment of the present invention, the sending protocol stack first serializes the data to obtain serialized data, including: First, convert the byte stream into a bit stream, and then insert a 0 after every 5 bits of 1 to generate a new bit stream. For example, after serialization, 7A9F becomes 01011110 11111000 1.

[0077] In an embodiment of the present invention, converting serialized data into binary code includes: According to the specific encoding format, each 1-bit bitstream is encoded into a 2-bit binary codestream. For example, FM0 encoding encodes 110010 into 001101010010, and Manchester encoding encodes 110010 into 101001011001, generating a new binary codestream.

[0078] The process of converting serialized data into binary code further includes adding a start flag, an end flag, a frame header, and a frame tail to the binary code in sequence.

[0079] The addition of start and end markers involves encoding 0x7E in binary and adding it to the beginning and end of the binary code stream.

[0080] The addition of frame headers and frame trailers involves encoding 16 ones and 16 zeros in binary and adding them to the beginning of the binary bitstream, and encoding 8 zeros in binary and adding them to the end of the binary bitstream.

[0081] The process of sampling and encoding data via SPI and then sending the binary encoded data out via DMA includes: The SPI samples the binary bitstream. Based on the SPI baud rate of 4M, each bitstream is converted into 1 byte after SPI sampling, and a new byte sequence is generated after sampling. DMA sends data, initializes the SPI controller and DMA function, and sends out the byte sequence via DMA.

[0082] S20. When the main controller needs to receive data, it uses the DMA mode of SPI to receive data. The receive protocol stack executes in a loop, finds the frame header and start flag of the data according to the feature value, and continues to convert the SPI data into binary code and bytecode until timeout or the end of the frame is received. Finally, the byte data is sent to the higher layer.

[0083] In an embodiment of the present invention, the step of receiving data using the DMA mode of SPI further includes: initializing the SPI controller and DMA, setting the baud rate of the SPI controller to 8M, setting the DMA to cyclic receive mode, setting the receive buffer to 128 bytes, and setting half-full and full interrupts.

[0084] In an embodiment of the present invention, the step of finding the frame header and start marker of the data based on feature values ​​is preceded by the following steps: Find the feature value of frame header 1: In the received data, search in a loop for the sequence FF 00 FF 00FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 ; Data serialization: Convert the byte stream after frame header 1 into a bit stream, and adjust the starting bit of the bit stream according to the position of the 8 0s or 8 1s that appear in the bit stream to reassemble it into a byte stream, which will result in a byte stream that is either FF or 00.

[0085] In an embodiment of the present invention, finding the frame header and start flag of the data based on the feature value includes searching for frame header 2 and the start flag. First, in the new byte stream, search for FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1. Then, search for FF 00 FF FF 00 00 FF FF 00 00 FF FF 00 FF 00 or the reverse sequence; otherwise, return to 2 to search for the feature value of frame header 1 again.

[0086] In an embodiment of the present invention, the step of converting SPI data into binary encoding and byte-based encoding includes the following steps: performing binary inverse encoding, binary inverse encoding, bitstream byte-based encoding, and data CRC check processing on the data in sequence.

[0087] The binary decoding process involves generating a new binary code stream by decoding the byte stream generated in step 3 byte by byte. If an FF (Flash) is found, a 1 is inserted into the binary code stream; if a 00 is found, a 0 is inserted. This process continues until the binary code stream contains either 0100110011001101 or its reverse sequence, or until a timeout occurs. If a byte stream is found to be non-FF or 00 during decoding, special processing is required, and subsequent byte streams are re-serialized before decoding. This process filters out interference and perfectly adapts to the problem of inconsistent received baud rates.

[0088] The binary inverse encoding is to inversely encode every 2 bits in the binary code stream into a 1-bit code stream according to a specific encoding format. For example, FM0 encoding encodes 001101010010 into 110010, and Manchester encoding encodes 101001011001 into 110010, thus generating a new binary code stream.

[0089] The bitstream byteification involves reorganizing the obtained binary bitstream by removing the last 0 after five 1s to obtain a new bitstream, and then reorganizing the bitstream into a bytestream.

[0090] The data CRC check is performed by calculating CRC16 (X16+X12+X5+1) on the byte stream except for the last two bytes. The result is compared with the last two bytes. If they are equal, the data is correct. After removing the checksum, the data is sent to the higher layer.

[0091] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory.

[0092] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0093] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for encoding and decoding the HDLC protocol using SPI, applied to a system including a main controller and an RF front-end, characterized in that, The method includes: When the main controller needs to send data to the RF front end, it first sends the higher-layer data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. When the main controller needs to receive data from the RF front end, it uses the DMA mode of SPI to receive the data. The receive protocol stack executes in a loop, finds the frame header and start flag of the data based on the feature value, and continues to convert the SPI data into binary code and bytecode until timeout or the end of the frame is received. Finally, the byte data is sent to the higher layer.

2. The encoding and decoding method for simulating HDLC protocol via SPI as described in claim 1, characterized in that, The sending protocol stack first serializes the data to obtain serialized data, and before that, it also includes a 2-byte CRC check added to the end of the received data.

3. The encoding and decoding method for simulating the HDLC protocol via SPI as described in claim 2, characterized in that, The process of converting serialized data into binary code further includes adding a start flag, an end flag, a frame header, and a frame tail to the binary code.

4. The encoding and decoding method for simulating the HDLC protocol via SPI as described in claim 3, characterized in that, The process of sampling and encoding data via SPI and sending out the binary encoding via DMA includes the following steps: The SPI samples the binary code stream. Based on the SPI baud rate of 4M, each code stream is converted into 1 byte after SPI sampling, and a new byte sequence is generated after sampling. DMA sends data, initializes the SPI controller and DMA function, and sends out the byte sequence via DMA.

5. The encoding and decoding method for simulating HDLC protocol via SPI as described in claim 1, characterized in that, The process of receiving data using the DMA mode of SPI also includes: SPI controller and DMA initialization, and setting the SPI controller baud rate to 8M; Set the DMA to circular receive mode, the receive buffer to 128 bytes, and set it to half-full and full interrupts.

6. The encoding and decoding method for simulating the HDLC protocol via SPI as described in claim 5, characterized in that, Before finding the frame header and start marker of the data based on feature values, the following steps are also included: Find the feature value of frame header 1: In the received data, search in a loop for the sequence FF 00 FF 00 FF00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 ; Data serialization: Convert the byte stream after frame header 1 into a bit stream, and adjust the starting bit of the bit stream according to the position of the 8 0s or 8 1s that appear in the bit stream to reassemble it into a byte stream, which will result in a byte stream that is either FF or 00.

7. The encoding and decoding method for simulating the HDLC protocol via SPI as described in claim 6, characterized in that, The process of converting SPI data into binary encoding and byte-based data includes the following steps: performing binary de-encoding, bitstream byte-based encoding, and data CRC check processing on the data in sequence.

8. A codec system for simulating the HDLC protocol via SPI, characterized in that, The system includes: a main controller and an RF front-end; The main controller includes an SPI controller; the MISO pin of the SPI controller is connected to the TxD pin of the HDLC of the RF front-end, and the MOSI pin of the SPI controller is connected to the RxD pin of the HDLC of the RF front-end. The system configuration is as follows: when the main controller needs to send data to the RF front-end, it first sends the higher-layer data to the transmission protocol stack. The transmission protocol stack first serializes the data to obtain serialized data, then converts the serialized data into binary code, samples the encoded data through SPI, and sends the binary code out through DMA to complete the data transmission. When the main controller needs to receive data from the RF front-end, it uses the DMA mode of SPI to receive the data. The receive protocol stack executes in a loop, finds the frame header and start flag of the data based on the feature value, continues to convert the SPI data into binary code and bytecode, until timeout or the end of the frame is received, and finally sends the byte data to the higher layer.

9. A terminal comprising a memory and a processor, the memory storing a computer program, the processor loading and executing the computer program to implement the steps of the encoding and decoding method for simulating the HDLC protocol via SPI as described in any one of claims 1-7.

10. A storage medium storing a computer program, which, when loaded and executed by a processor, implements the steps of the encoding / decoding method for simulating the HDLC protocol via SPI as described in any one of claims 1-7.

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