A vertical gate-all-around transistor, a non-capacitive memory structure and a method of fabricating the same
By using a vertical ring gate transistor structure and low-temperature process, the challenges of low integration density and three-dimensional integration were solved, achieving a high-efficiency three-dimensional integration and low-power memory structure, and enhancing the gate's control over the channel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2022-10-28
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, horizontal channel configurations result in low integration density, traditional DRAM cell structures consume a lot of power, three-dimensional chip interconnect efficiency is limited, low-temperature fabrication of IGZO-TFT is limited, and high-density three-dimensional integration is difficult to achieve in integrated circuit processes.
A vertical gate ring transistor structure is adopted, which enhances the gate's control over the channel by vertically stacking two transistors. The shared electrode simplifies the interconnection. The number and size of nanosheets are adjusted to control the gate width. Three-dimensional integration is achieved using a low-temperature process.
It improves integration density, reduces subthreshold swing and off-state current, simplifies interconnection complexity, reduces parasitic effects, and enables low-temperature fabrication and efficient three-dimensional integration.
Smart Images
Figure CN115768109B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistors, and particularly to a vertical ring gate transistor, a capacitor-free memory structure, and a method for fabricating the same. Background Technology
[0002] Amorphous oxide-semiconductor thin film transistors (OSTFTs) have great application prospects in display panel driving, memory and flexible circuit fields due to their low leakage current and simple low-temperature fabrication process.
[0003] Currently, both horizontal and vertical channel transistors are planar devices, with the gate only covering one side of the channel. The back channel on the other side is highly susceptible to performance degradation due to carrier scattering and diffusion of impurities such as hydrogen caused by surface irregularities. A ring-gate transistor with a fully enclosed structure can eliminate this instability caused by the back channel.
[0004] Vertical channel devices are considered to have a smaller footprint and are easier to integrate in three dimensions, so they have great application potential in high-density chips. Vertical gate-around oxide thin film transistors have great application prospects in monolithic three-dimensional stacked chips due to their back-end process compatibility.
[0005] Currently, the common DRAM cell structure consists of a transistor with its drain connected to a capacitor. This structure requires constantly refreshing the charge in the capacitor to prevent data loss, and during reading, the charge in the capacitor must be released, and then rewritten after the read is complete, resulting in relatively high power consumption. Furthermore, the large area required for capacitor manufacturing makes miniaturization a significant challenge.
[0006] The dual-transistor capacitorless dynamic random access memory (2Transistor 0Capacitor 2T0C) uses two transistors as its unit structure, as shown in the circuit diagram below. Figure 1 As shown, the drain of one transistor is connected to the gate of another transistor, using the gate capacitance to store charge and changing the transconductance of the transistor to store information.
[0007] In recent years, 2TOC memory using indium gallium zinc oxide (IGZO) channels has become increasingly popular due to the extremely low off-state current of IGZO thin-film transistors (TFTs), which significantly reduces leakage current in 2TOC DRAM cells. However, existing IGZO TFT-based 2TOC DRAM cells typically use two horizontally channeled TFTs connected on the same plane, resulting in a larger footprint and lower integration density.
[0008] Traditional 3D chip structures often employ 3D packaging, wafer bonding, or TSV (Through-Silicon-Via) technology, which reduces cell area and increases integration density to some extent. However, due to the size limitations of these methods, the interconnect channels between memory and logic sections are on the order of several micrometers or tens of micrometers, significantly limiting the efficiency and bandwidth of 3D vertical interconnects. Furthermore, the aspect ratio of deep vias limits their area to a relatively large size. Monolithic 3D integration builds upon traditional 2D chips by using integrated circuit processes (such as thin-film deposition, photolithography, and etching) to grow devices with specific functions. Monolithic 3D integration can minimize interconnect length and increase integration density. It also allows for internal interconnects between layers, further reducing interconnect complexity. One of the biggest challenges of monolithic 3D integration is low-temperature processing (generally requiring <400℃), which IGZO-TFTs can achieve.
[0009] Therefore, this invention is proposed. Summary of the Invention
[0010] The main objective of this invention is to provide a vertical ring gate transistor structure, a capacitor-free memory structure, and a method for fabricating the same, which solves the problem of low integration density caused by horizontal channel arrangement in the prior art. It also uses a ring gate transistor to enhance the gate's control over the conductive channel, controls the gate width by controlling the number and size of nanosheets, and simplifies interconnection by having the upper and lower transistors share the same electrode.
[0011] To achieve the above objectives, the present invention provides the following technical solutions.
[0012] A first aspect of the present invention provides a vertical ring gate transistor structure, comprising, from bottom to top:
[0013] Substrate;
[0014] Isolation layer;
[0015] Source electrode layer;
[0016] And a plurality of columnar first stacked structures disposed on the upper surface of the read bit line layer, wherein the first stacked structure is formed by stacking a first channel layer, a read word line layer and a first hard mask layer from bottom to top;
[0017] And a first gate dielectric layer, which surrounds the side surface, the top surface and the top surface of the read bit line layer of the first stacked structure;
[0018] And a first gate layer covering the surface of the first gate dielectric layer, wherein the first gate layer fills the gap between adjacent first stacked structures.
[0019] A second aspect of the present invention provides a capacitor-free memory structure with a vertical ring gate.
[0020] From bottom to top, they include:
[0021] Substrate, isolation layer, lower transistor, and upper transistor;
[0022] The lower-level transistor includes: a readout bitline layer;
[0023] And a plurality of columnar first stacked structures disposed on the upper surface of the read bit line layer, wherein the first stacked structure is formed by stacking a first channel layer, a read word line layer and a first hard mask layer from bottom to top;
[0024] And a first gate dielectric layer, which surrounds the side surface, the top surface and the top surface of the read bit line layer of the first stacked structure;
[0025] And a first gate layer covering the surface of the first gate dielectric layer, wherein the first gate layer fills the gap between adjacent first stacked structures;
[0026] The upper-layer transistor includes:
[0027] Multiple columnar second stacked structures are disposed on the upper surface of the first gate layer. The second stacked structure is formed by stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top.
[0028] And a second gate dielectric layer, the second gate dielectric layer surrounding the side surface, the top surface and the top surface of the first gate layer of the second stacked structure;
[0029] And a second gate layer covering the surface of the second gate dielectric layer, wherein the second gate layer fills the gap between adjacent second stacked structures;
[0030] The first gate layer in the lower transistor also serves as the drain of the upper transistor.
[0031] The capacitor-free memory structure of the present invention exhibits superior performance compared to existing memories in terms of integration density, gate-to-channel control capability, and gate width adjustability due to its specific structural characteristics. These specific structural characteristics mainly refer to the following aspects.
[0032] On the one hand, the two transistors are vertically stacked, and the bit lines, word lines, gates and channels in each transistor are also vertically stacked. The above multiple three-dimensional stacking greatly reduces the unit area and increases the integration density.
[0033] On the other hand, the gates (first gate layer and second gate layer) in both transistors adopt a "ring gate" structure, which surrounds the channel and the source / drain and fills the gap between adjacent stacked structures (i.e., the nanosheet structure composed of the channel and the source / drain). The gap is used to indirectly increase the gate width, thus having a strong control over the channel, thereby reducing the subthreshold swing and reducing the off-state current.
[0034] On the other hand, the number and size of nanosheet structures such as the first stacked structure and the second stacked structure can be freely adjusted during the patterning and etching stages, so the gate width can also be adjusted accordingly, and it has almost no impact on the integration density.
[0035] On the other hand, the gates (first gate layer and second gate layer) in both transistors adopt a "gate-around" structure, which can completely surround the channel, thereby avoiding the adverse effects of the back channel on the transistor.
[0036] On the other hand, the gate of the lower transistor and the drain of the upper transistor use the same electrode (that is, the gate of the lower transistor also serves as the drain of the upper transistor), which further simplifies the interconnection process and reduces parasitic effects.
[0037] The above-described vertical ring gate capacitor-free memory structure can be further improved to enhance the overall performance of the device, as listed below.
[0038] Furthermore, the isolation layer is made of SiO2 or SiN. x At least one of them;
[0039] And / or, the read bit line layer, the read word line layer, the first gate layer, the write bit line layer and the second gate layer each independently employ at least one of Mo, TiN, Ti, Al, indium tin oxide and indium zinc oxide.
[0040] Furthermore, the first trench layer and the second trench layer each independently employ at least one of In2O3, ZnO, and IGZO;
[0041] And / or, the first gate dielectric layer and the second gate dielectric layer each independently employ at least one of SiO2, HfO2, and Al2O3.
[0042] Furthermore, the first stacked structure and the second stacked structure are conformal.
[0043] Furthermore, the first gate dielectric layer and the second gate dielectric layer are conformal.
[0044] Furthermore, the first gate layer and the second gate layer are conformal.
[0045] A third aspect of the present invention provides a method for fabricating the vertical ring gate transistor structure described above, comprising the following steps:
[0046] Provide substrate;
[0047] An isolation layer, a source electrode layer, a first channel layer, a read word line layer, and a first hard mask layer are stacked sequentially from bottom to top on the substrate.
[0048] The first hard mask layer is patterned, and then the first channel layer and read word line layer are etched using the first hard mask layer as a mask, thereby forming multiple columnar first stacked structures composed of the first channel layer, read word line layer and first hard mask layer.
[0049] A first gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the read bit line layer of the first stacked structure.
[0050] A first gate layer is formed by filling the gap between adjacent first stacked structures with gate material.
[0051] A fourth aspect of the present invention provides a method for fabricating a capacitor-free memory structure with a vertical ring gate, comprising the following steps:
[0052] Provide substrate;
[0053] An isolation layer, a read bit line layer, a first channel layer, a read word line layer, and a first hard mask layer are stacked sequentially from bottom to top on the substrate.
[0054] The first hard mask layer is patterned, and then the first channel layer and read word line layer are etched using the first hard mask layer as a mask, thereby forming multiple columnar first stacked structures composed of the first channel layer, read word line layer and first hard mask layer.
[0055] A first gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the read bit line layer of the first stacked structure.
[0056] A first gate layer is formed by filling the gap between adjacent first stacked structures with gate material;
[0057] A second channel layer, a write bit line layer, and a second hard mask layer are stacked sequentially from bottom to top on the surface of the first gate layer.
[0058] The second hard mask layer is patterned, and then the second channel layer and the bit line layer are etched and written using the pattern as a mask, thereby forming multiple columnar second stacked structures composed of the second channel layer, the bit line layer, and the second hard mask layer.
[0059] A second gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the first gate layer of the second stacked structure.
[0060] A second gate layer is formed by filling the gap between adjacent second stacked structures with gate material.
[0061] Furthermore, the process includes the following steps after forming the first gate layer and before forming the second channel layer:
[0062] A dielectric material is deposited, and then planarized to expose the upper surface of the first gate layer.
[0063] Furthermore, it also includes: leading out electrodes for the read bit line layer, the read word line layer, the first gate layer, the write bit line layer, and the second gate layer.
[0064] Furthermore, after forming the first gate layer and before forming the second channel layer, the method further includes: patterning the first gate layer.
[0065] In summary, compared with the prior art, the present invention achieves the following technical effects:
[0066] (1) The present invention uses a gate ring transistor to enhance the gate’s control over the conductive channel, reduce the subthreshold swing, and reduce the off-state current.
[0067] (2) The present invention controls the gate width by controlling the number and size of nanosheets to meet different application requirements.
[0068] (3) The present invention achieves three-dimensional integration by vertical stacking, which further reduces the unit area and increases the integration density.
[0069] (4) The gate of the lower transistor and the drain of the upper transistor use the same electrode, which further simplifies the interconnection difficulty and reduces parasitic effects.
[0070] (5) The preparation method provided by the present invention has a simple process and low requirements for equipment and operating conditions. Attached Figure Description
[0071] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.
[0072] Figure 1 This is a schematic diagram of the structure of a dual-transistor capacitorless dynamic random access memory in the prior art;
[0073] Figure 2 This is a schematic diagram of the structure of the capacitor-free memory provided by the present invention;
[0074] Figure 3 for Figure 2 The diagram shows the storage principle of the structure shown.
[0075] Figures 4 to 14 This is a schematic diagram of the structure obtained in each step of the manufacturing method provided by the present invention. Detailed Implementation
[0076] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0077] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0078] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0079] In existing 2T0C DRAM cells, two horizontal channel TFTs are typically connected on the same plane, which occupies a large area and is not conducive to improving integration density.
[0080] Therefore, the present invention provides, as follows Figure 2The capacitor-free DRAM cell structure based on thin-film transistors shown can be functionally divided into three regions from bottom to top: substrate, lower transistor, and upper transistor, as detailed below.
[0081] The substrate 101 can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide, etc.
[0082] An isolation layer 102 is formed on the substrate 101. The isolation layer 102 may be made of a high-k dielectric material such as oxides or oxynitrides, for example, typical silicon oxide (SiO2), silicon oxynitride, or silicon nitride (SiN). x )wait.
[0083] With the isolation layer 102 as the boundary, the upper part is the lower layer transistor. The transistor is vertically stacked and realizes the function of the read transistor. It includes a read bit line layer 103 (i.e. the source of the lower layer transistor) that covers a large area of the isolation layer, a first stacked structure, a first gate dielectric layer 107, and a first gate layer 108.
[0084] Multiple columnar first stacked structures are disposed on the upper surface of the read bit line layer 103. These first stacked structures are formed by stacking a first channel layer 104, a read word line layer 105, and a first hard mask layer 106 sequentially from bottom to top. The read bit line layer 103 is not patterned into nanosheets like the first channel layer 104; this is primarily to enhance the isolation effect of the gate dielectric on the first channel layer 104, while also enhancing the gate's control over the first channel layer 104. The read word line layer 105 is the drain. The first hard mask layer 106 is retained primarily for etching to form the nanosheet stacked structure. The first gate dielectric layer 107 surrounds the side surfaces and top surface of the first stacked structure and the top surface of the read bit line layer 103, providing excellent isolation. The first gate layer 108 covers the surface of the first gate dielectric layer 107 and fills the gaps between adjacent first stacked structures. This ring gate formation has the characteristics of small footprint but large gate width, resulting in stronger control over the channel. The first gate layer 108 in the lower transistor is also the drain of the upper transistor, that is, the lower transistor and the upper transistor share a common electrode.
[0085] The upper transistors are also vertically stacked to enable the write function, and include a second stacked structure, a second gate dielectric layer 113, and a second gate layer 114.
[0086] In this configuration, multiple columnar second stacked structures are disposed on the upper surface of the first gate layer 108. These second stacked structures are formed by sequentially stacking the second channel layer 110, the write bit line layer 111, and the second hard mask layer 112 from bottom to top. The second gate dielectric layer 113 surrounds the side surface and upper surface of the second stacked structure and the upper surface of the first gate layer 108, providing excellent isolation. The second gate layer 114 covers the surface of the second gate dielectric layer 113 and fills the gaps between adjacent second stacked structures. This ring gate formation has the advantages of small footprint but large gate width, providing stronger control over the channel. Furthermore, the first gate layer 108 and the second gate layer 114 can be patterned to obtain a preset shape, and the gaps created by the patterning can be filled with a dielectric material, such as... Figure 2 Medium filling layer 109.
[0087] Figure 2 The capacitor-free memory structure shown has the following characteristics.
[0088] (1) Two transistors are vertically stacked, and the bit lines, word lines, gates and channels in each transistor are also vertically stacked. The above multiple three-dimensional stacking greatly reduces the unit area and increases the integration density.
[0089] (2) The gates (first gate layer and second gate layer) in both transistors adopt a "ring gate" structure, which surrounds the channel and the source / drain and fills the gap between adjacent stacked structures (i.e., the nanosheet structure composed of the channel and the source / drain). The gap is used to indirectly increase the gate width, thus having a strong control over the channel, thereby reducing the subthreshold swing and reducing the off-state current.
[0090] (3) The gates (first gate layer and second gate layer) in both transistors adopt a "ring gate" structure, which can completely surround the channel, thereby avoiding the adverse effects of the back channel on the transistor.
[0091] (4) The number and size of nanosheet structures such as the first stacked structure and the second stacked structure can be freely adjusted during the patterning and etching stages, so the gate width can also be adjusted accordingly, and it has almost no effect on the integration density.
[0092] The working principle of the capacitor-free memory structure described above in this invention is as follows: Figure 3 As shown (the positions of the transistors in the figure are only for illustrative purposes and do not represent the actual layout), the first layer of transistors acts as the read transistor, and the second layer of transistors acts as the write transistor. The gate of the former and the drain of the latter are on the same electrode. By changing the charge in the gate capacitance of the read transistor through the write transistor, the resistance state between the source and drain of the read transistor is affected, thereby realizing the distinction between "0" and "1". The specific principle is as follows.
[0093] During the writing of a "1", a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL to turn on the write transistor, and a positive voltage is applied to the write bit line WBL to inject charge into the gate capacitance of the read transistor (i.e., the storage node). After charge injection, the gate and source voltages of the write transistor are removed, and the "1" state is preserved.
[0094] In the process of reading "1", a reading voltage is applied to the drain of the reading transistor. Since there is a certain charge in the gate capacitor, the reading transistor is in a low resistance state and obtains a large current. The reading "1" is then amplified and identified by the external circuit.
[0095] During the writing "0" process, a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read transistor to turn on the write transistor, and a negative voltage is applied to the source of the write transistor to draw charge from the gate capacitance of the read transistor (i.e., the storage node). After the charge is drawn, the gate and source voltages of the write transistor are removed, and the "0" state is preserved.
[0096] In the process of reading "0", a reading voltage is applied to the drain of the read transistor. Since there is no charge in the gate capacitor, the read transistor is in a high resistance state and obtains a small current. This current is then amplified and identified by the external circuit to complete the process of reading "0".
[0097] In terms of material selection, each layer of the above capacitor-free memory structure can use any material that can realize its basic function. However, in order to further improve the electrical performance and performance of the memory, each layer has its preferred material.
[0098] For example, the first channel layer 104 and the second channel layer 110 are each independently made of at least one of In2O3, ZnO, and IGZO. Among them, IGZO thin-film transistors have very low off-state leakage current, so the information in the storage node can be retained for a relatively long time.
[0099] The first gate dielectric layer 107 and the second gate dielectric layer 113 serve as insulation between the gate and the channel. They are preferably made of materials with wide bandgap and high dielectric constant, or materials suitable for fabricating extremely small devices, such as at least one of SiO2, HfO2, and Al2O3.
[0100] The read bit line layer 103, the read word line layer 105, the first gate layer 108, the write bit line layer 111, and the second gate layer 114 serve as electrodes to be connected to the power supply. They are preferably made of metal materials or doped semiconductor materials with good conductivity, including but not limited to at least one of Mo, TiN, Ti, Al, W, indium tin oxide, and indium zinc oxide. Furthermore, considering the speed and stability of current transfer between the electrodes, the read bit line layer 103, the read word line layer 105, the first gate layer 108, the write bit line layer 111, and the second gate layer 114 are preferably made of the same material or materials with very similar properties.
[0101] This invention also provides a method for manufacturing the above-mentioned capacitor-free memory structure. This method is simple, has good compatibility with existing 3D semiconductor device fabrication processes, and combines... Figures 4 to 14 and Figure 2 The specific process is as follows.
[0102] First, in such Figure 4 An isolation layer 102 is formed on the surface of the semiconductor substrate 101 shown. As described above, the isolation layer 102 is preferably made of silicon oxide and can be deposited by in-situ oxidation, PECVD, ALCVD or other deposition methods.
[0103] Next, metal is sputtered or other electrode material layers are grown on the surface of the isolation layer 102 to serve as the read bit line layer 103.
[0104] Then, a first channel layer 104 is formed on the surface of the read bit line layer 103.
[0105] Next, conductive material is deposited on the upper surface of the first channel layer 104 to form the read word line layer 105, such as Figure 4 As shown.
[0106] A hard mask material is grown on the upper surface of the read word line layer 105 to form a first hard mask layer 106, such as... Figure 5 As shown.
[0107] The first hard mask layer 106 is patterned according to a predetermined nanosheet structure, such as... Figure 6 As shown in the figure, only two nanosheets are illustrated, but this does not limit the number of nanosheets in the present invention, and they can be adjusted arbitrarily in actual processes.
[0108] by Figure 6 The first hard mask layer 106 shown is a mask. The first channel layer 104 and the read word line layer 105 are etched to form multiple columnar first stacked structures composed of the first channel layer 104, the read word line layer 105, and the first hard mask layer 106. Figure 7 As shown.
[0109] Then, a first gate dielectric layer 107 is grown, which surrounds the side surface, top surface, and top surface of the read bit line layer 103 of the first stacked structure, as shown below. Figure 8 As shown.
[0110] The gate material is filled and the gaps between adjacent first stacked structures are filled to form a first gate layer 108, such as... Figure 9 As shown. Typically, the first gate layer 108 needs to be patterned so that part of the first gate dielectric layer 107 covering the read bit line layer is exposed, thereby better isolating it from the read bit line layer 103, as shown. Figure 10As shown. The cavities formed after patterning can be filled with deposited dielectric materials, such as... Figure 11 The medium filling layer 109 is shown.
[0111] Next, a second channel layer 110, a write bit line layer 111, and a second hard mask layer 112 are sequentially stacked from bottom to top on the surface of the first gate layer 108, as follows: Figure 12 As shown.
[0112] Next, the same process as the first stacked structure is used: first, the second hard mask layer 112 is patterned according to a predetermined nanosheet structure; then, using it as a mask, the second channel layer 110 is etched and the bit line layer 111 is written, thereby forming multiple columnar second stacked structures composed of the second channel layer 110, the bit line layer 111, and the second hard mask layer 112, such as... Figure 13 As shown. In some preferred embodiments, the second stacking structure is conformal to the first stacking structure, but this does not limit the maximum scope of protection of the invention.
[0113] Then, a second gate dielectric layer 113 is grown, which surrounds the side surface, the top surface, and the top surface of the first gate layer 108 of the second stacked structure, as shown below. Figure 14 As shown. In some preferred embodiments, the second gate dielectric layer 113 is conformal to the first gate dielectric layer 107, but this does not limit the maximum scope of protection of the present invention.
[0114] A second gate layer 114 is formed by filling the gaps between adjacent second stacked structures with gate material. Similarly, the second gate layer 114 is patterned to obtain the desired shape. Figure 2 The structure is shown. In some preferred embodiments, the second gate layer 114 is conformal to the first gate layer 108, but this does not limit the maximum scope of protection of the present invention.
[0115] Finally, select any large-area deposition medium material to fill the area, and then use photolithography contact holes or etching step structures to bring out the electrodes of each conductive layer.
[0116] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A transistor structure with a vertical ring gate, characterized in that, From bottom to top, they include: Substrate; Isolation layer; Read the bitline layer; And a plurality of columnar first stacked structures disposed on the upper surface of the read bit line layer, wherein the first stacked structure is formed by stacking a first channel layer, a read word line layer and a first hard mask layer from bottom to top; And a first gate dielectric layer, which surrounds the side surface, the top surface and the top surface of the read bit line layer of the first stacked structure; And a first gate layer covering the surface of the first gate dielectric layer, wherein the first gate layer fills the gap between adjacent first stacked structures.
2. A capacitor-free memory structure with a vertical ring gate, characterized in that, From bottom to top, they include: Substrate, isolation layer, lower transistor, and upper transistor; The lower-level transistor includes: Read the bitline layer; And a plurality of columnar first stacked structures disposed on the upper surface of the read bit line layer, wherein the first stacked structure is formed by stacking a first channel layer, a read word line layer and a first hard mask layer from bottom to top; And a first gate dielectric layer, which surrounds the side surface, the top surface and the top surface of the read bit line layer of the first stacked structure; And a first gate layer covering the surface of the first gate dielectric layer, wherein the first gate layer fills the gap between adjacent first stacked structures; The upper-layer transistor includes: Multiple columnar second stacked structures are disposed on the upper surface of the first gate layer. The second stacked structure is formed by stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top. And a second gate dielectric layer, the second gate dielectric layer surrounding the side surface, the top surface and the top surface of the first gate layer of the second stacked structure; And a second gate layer covering the surface of the second gate dielectric layer, wherein the second gate layer fills the gap between adjacent second stacked structures; The first gate layer in the lower transistor also serves as the drain of the upper transistor.
3. The capacitor-free memory structure with a vertical ring gate according to claim 2, characterized in that, The isolation layer is made of at least one of SiO2 and SiNx; And / or, the read bit line layer, the read word line layer, the first gate layer, the write bit line layer and the second gate layer each independently employ at least one of Mo, TiN, Ti, and Al.
4. The capacitor-free memory structure with a vertical ring gate according to claim 2, characterized in that, The first trench layer and the second trench layer each independently employ at least one of In2O3, ZnO, and IGZO; And / or, the first gate dielectric layer and the second gate dielectric layer each independently employ at least one of SiO2, HfO2, and Al2O3.
5. The capacitor-free memory structure with a vertical ring gate according to claim 2 or 3, characterized in that, The first stacked structure and the second stacked structure are conformal.
6. The capacitor-free memory structure with a vertical ring gate according to claim 2 or 3, characterized in that, The first gate dielectric layer and the second gate dielectric layer are conformal.
7. The capacitor-free memory structure with a vertical ring gate according to claim 2 or 3, characterized in that, The first gate layer and the second gate layer are conformal.
8. The method for fabricating the transistor structure with a vertical ring gate according to claim 1, characterized in that, Includes the following steps: Provide substrate; An isolation layer, a read bit line layer, a first channel layer, a read word line layer, and a first hard mask layer are stacked sequentially from bottom to top on the substrate. The first hard mask layer is patterned, and then the first channel layer and read word line layer are etched using the first hard mask layer as a mask, thereby forming multiple columnar first stacked structures composed of the first channel layer, read word line layer and first hard mask layer. A first gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the read bit line layer of the first stacked structure. A first gate layer is formed by filling the gap between adjacent first stacked structures with gate material.
9. A method for fabricating a capacitor-free memory structure with a vertical ring gate according to any one of claims 2-7, characterized in that, Includes the following steps: Provide substrate; An isolation layer, a read bit line layer, a first channel layer, a read word line layer, and a first hard mask layer are stacked sequentially from bottom to top on the substrate. The first hard mask layer is patterned, and then the first channel layer and read word line layer are etched using the first hard mask layer as a mask, thereby forming multiple columnar first stacked structures composed of the first channel layer, read word line layer and first hard mask layer. A first gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the read bit line layer of the first stacked structure. A first gate layer is formed by filling the gap between adjacent first stacked structures with gate material; A second channel layer, a write bit line layer, and a second hard mask layer are stacked sequentially from bottom to top on the surface of the first gate layer. The second hard mask layer is patterned, and then the second channel layer and the bit line layer are etched and written using the pattern as a mask, thereby forming multiple columnar second stacked structures composed of the second channel layer, the bit line layer, and the second hard mask layer. A second gate dielectric layer is formed, which surrounds the side surface, the top surface, and the top surface of the first gate layer of the second stacked structure. A second gate layer is formed by filling the gap between adjacent second stacked structures with gate material.
10. The preparation method according to claim 9, characterized in that, The process after forming the first gate layer and before forming the second channel layer also includes: A dielectric material is deposited, and then planarized to expose the upper surface of the first gate layer.
11. The preparation method according to claim 9, characterized in that, Also includes: The electrodes of the read bit line layer, the read word line layer, the first gate layer, the write bit line layer, and the second gate layer are brought out.
12. The preparation method according to claim 9, characterized in that, The process includes, after forming the first gate layer and before forming the second channel layer, patterning the first gate layer.