Three-dimensional memory, method for manufacturing three-dimensional memory, and memory system

Abstract

This application provides a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a memory system. The three-dimensional memory includes: a stacked layer comprising an alternately stacked first dielectric layer and a conductive layer; and a channel structure passing through the stacked layer and including a second dielectric layer and a barrier layer disposed sequentially from the outside to the inside, wherein the dielectric constant of the second dielectric layer is greater than or equal to 3.9.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a memory system. Background Technology

[0002] Planar memory devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, three-dimensional memory has been proposed. Three-dimensional memory typically consists of stacked layers formed by alternating dielectric and gate layers. It also includes a channel structure running through the stacked layers.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] This application provides a three-dimensional memory, a method for manufacturing a three-dimensional memory, and a memory system. According to one aspect of this application, the three-dimensional memory includes: a stacked layer comprising an alternately stacked first dielectric layer and a conductive layer; and a channel structure passing through the stacked layer and including a second dielectric layer and a barrier layer disposed sequentially from the outside to the inside, wherein the dielectric constant of the second dielectric layer is greater than or equal to 3.9.

[0005] In one embodiment of this application, the dielectric constant of the second dielectric layer is greater than or equal to 10.

[0006] In one embodiment of this application, the barrier layer includes: a first barrier portion located on the surface of the second dielectric layer away from the first dielectric layer; and a second barrier portion located at least on the surface of the second dielectric layer away from the conductive layer, wherein the thickness of the first barrier portion is greater than the thickness of the second barrier portion in a direction parallel to the first dielectric layer.

[0007] In one embodiment of this application, the surface of the barrier layer away from the second dielectric layer is flat.

[0008] In one embodiment of this application, the surface of the first blocking portion away from the second dielectric layer is flush with the surface of the second blocking portion away from the second dielectric layer.

[0009] In one embodiment of this application, the thickness of the first blocking portion is greater than the thickness of the second dielectric layer in a direction parallel to the first dielectric layer.

[0010] In one embodiment of this application, the channel structure further includes a storage layer, a tunneling layer, and a channel layer arranged sequentially from the outside to the inside, wherein the storage layer is located on the surface of the barrier layer away from the second dielectric layer.

[0011] A memory system according to another aspect of this application includes: a three-dimensional memory as described in any of the preceding claims; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0012] In one embodiment of this application, the memory system includes a solid-state drive or a memory card.

[0013] A method for manufacturing a three-dimensional memory according to another aspect of this application includes: forming a channel hole in a stacked layer, the stacked layer including alternating stacked first dielectric layers and material layers; and sequentially forming a second dielectric layer and a barrier layer on the inner wall of the channel hole, wherein the dielectric constant of the second dielectric layer is greater than or equal to 3.9.

[0014] In one embodiment of this application, forming a channel hole in the stacked layer includes: forming a first channel hole through the stacked layer; and removing a portion of the first dielectric layer along the first channel hole to form the channel hole.

[0015] In one embodiment of this application, forming the barrier layer includes: forming a first barrier layer on the surface of the second dielectric layer; and removing a portion of the first barrier layer away from the material layer to form the barrier layer, wherein the surface of the barrier layer away from the second dielectric layer is flat.

[0016] In one embodiment of this application, forming the barrier layer includes: forming a first barrier layer on the surface of the second dielectric layer; removing a portion of the first barrier layer away from the material layer and exposing the surface of the second dielectric layer away from the material layer; and forming a second barrier layer on the remaining portion of the first barrier layer and the exposed surface of the second dielectric layer, wherein the surface of the second barrier layer away from the second dielectric layer is flat, and the remaining portion of the first barrier layer and the second barrier layer together constitute the barrier layer.

[0017] In one embodiment of this application, the material layer includes a first sacrificial layer, and the method further includes: removing the first sacrificial layer after forming the barrier layer; and forming a conductive layer in the space formed by removing the first sacrificial layer.

[0018] In one embodiment of this application, the material layer includes a conductive layer, wherein forming the stacked layer includes: forming a second channel via in a stacked structure, the stacked structure including alternating stacked first dielectric layers and first sacrificial layers; removing the first sacrificial layer; and forming the conductive layer in the space formed by removing the first sacrificial layer.

[0019] In one embodiment of this application, forming the stacked layer further includes: filling the second sacrificial layer in the second channel via before removing the first sacrificial layer; and removing the second sacrificial layer after forming the conductive layer.

[0020] In one embodiment of this application, forming a channel hole in the stacked layer includes removing a portion of the first dielectric layer via the second channel hole to form the channel hole.

[0021] In one embodiment of this application, the method further includes: sequentially forming a storage layer, a tunneling layer, and a channel layer on the surface of the barrier layer; and forming a dielectric core in the space defined by the channel layer. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0023] Figure 1 This is a schematic diagram of a three-dimensional memory including peripheral circuitry and a memory array according to some embodiments of this application;

[0024] Figure 2 Here is a schematic equivalent circuit diagram of a storage block according to some embodiments of this application;

[0025] Figure 3 This is a block diagram of an exemplary memory system including a three-dimensional memory according to some embodiments of this application;

[0026] Figure 4 This is a schematic diagram of an exemplary memory card including a three-dimensional memory according to some embodiments of this application;

[0027] Figure 5 This is a schematic diagram of an exemplary solid-state drive (SSD) including a three-dimensional memory according to some embodiments of this application;

[0028] Figure 6 This is a schematic diagram of the structure of a three-dimensional memory according to some embodiments of this application;

[0029] Figure 7 for Figure 6 A magnified view of the area within the dashed box;

[0030] Figure 8 A flowchart illustrating a method for manufacturing a three-dimensional memory according to some embodiments of this application; and

[0031] Figures 9 to 27 This is a schematic diagram of a semiconductor structure formed after certain steps in a method for manufacturing a three-dimensional memory according to some embodiments of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0033] Note that references to "one embodiment," "example embodiment," "some embodiments," "optionally," and "as an alternative" in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0034] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0035] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0036] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0037] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers.

[0038] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0039] It should also be understood that the terms “comprising,” “including,” “having,” “containing,” and / or “comprising”, when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as “at least one of…” appear after a list of listed features, they modify the entire list of features, not individual elements in the list.

[0040] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] The framework of a three-dimensional memory is typically formed by bonding a memory array and peripheral circuitry. Figure 1 A schematic diagram of a three-dimensional memory 601 according to some embodiments of this application is shown. The three-dimensional memory 601 may be, for example, a 3D NAND memory or a 3D NOR memory. It should be understood that the three-dimensional memory 601 may also be any example of the three-dimensional memory 400 described below. In some embodiments, the memory array 301 and peripheral circuitry may be arranged on the same wafer. In other embodiments, the memory array 301 and peripheral circuitry may be arranged on different wafers, which may be electrically coupled together, for example, by bonding processes. In some embodiments, the three-dimensional memory 601 is an integrated circuit (IC) package that encapsulates one or more array chips and a CMOS chip.

[0043] Continue to refer to Figure 1 The storage array 301 may be, for example, a flash memory array. Peripheral circuitry includes, for example, a page buffer / sensor amplifier 505, a column decoder / bit line driver 507, a row decoder / word line driver 509, a voltage generator 510, a control logic unit 512, a register 514, an I / F interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuitry may also include… Figure 1 Additional peripheral circuitry not shown.

[0044] In some examples, the page buffer / sensor amplifier 505 can be configured to read and program (write) data from and to the memory array according to control signals from the control logic unit 512. Optionally, the page buffer / sensor amplifier 505 can store a page of programming data (write data) to be programmed into a memory page of the memory array. In another example, the page buffer / sensor amplifier 505 can also sense a low-power signal representing a data bit stored in the memory page from the bit line during a read operation and amplify a small voltage swing to a recognizable logic level. The column decoder / bit line driver 507 can be configured to be controlled by the control logic unit 512 and select one or more such... Figure 2 The storage unit string shown is 308.

[0045] In some embodiments, the line decoder / word line (WL) driver 509 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks of the memory array and to select / deselect word lines of the blocks. The line decoder / word line driver 509 can also be configured to drive word lines using word line voltages generated by the voltage generator 510. In some embodiments, the line decoder / word line (WL) driver 509 can also select / deselect and drive the source select line (SSL) and drain select line (DSL).

[0046] In some embodiments, voltage generator 510 may be configured to be controlled by control logic unit 512 and generate various operating voltages (erase voltage, programming voltage, or read voltage) to be provided to the memory array. For example, in a read operation, the read voltage is provided to row decoder 509 to drive word lines (WL) to read memory cells 306 coupled thereto.

[0047] In some embodiments, control logic unit 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Control logic unit 512 may execute the flash memory operation methods described below. Register 514 may be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit.

[0048] In some embodiments, the I / F interface 516 may be coupled to the control logic unit 512 and act as a control buffer to buffer data from the host (e.g., Figure 3 The host 408 (shown) receives control commands and forwards them to the control logic unit 512, and buffers status information received from the control logic unit 512 and forwards it to the host 408. The I / F interface 516 can also be coupled to the column decoder / bit line driver 507 via the data bus 518, and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory array.

[0049] like Figure 2As shown, the memory array 401 may include multiple memory blocks 319. In an example where the three-dimensional memory 601 may be, for example, a 3D NAND memory, the memory blocks 319 may include multiple memory cell strings 308, each memory cell string 308 including multiple memory cells 317 that are series-coupled and vertically stacked. Each memory cell 317 is capable of holding a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 317. Each memory cell 317 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0050] In some implementations, the three-dimensional memory 601 includes at least one type of SLC, MLC, TLC, and QLC. The SLC type indicates that each memory cell 317 stores 1 bit of data, and the memory cell 317 has only two data states: "0" and "1". The MLC type indicates that each memory cell stores 2 bits of data, and the memory cell 317 has four data states: "00", "01", "10", and "11". The TLC type indicates that each memory cell stores 3 bits of data, and the memory cell 317 has eight data states: "000", "001", "010", "011", "100", "101", "110", and "111". Similarly, the QLC type indicates that each memory cell stores 4 bits of data, and the memory cell 317 has sixteen data states. It is understood that in some examples, the memory cell 317 may also store more than 4 bits of data.

[0051] Continue to refer to Figure 2Each memory cell string 308 may also include a drain-select gate transistor 312 at its drain end. In some examples where the drain-select gate transistor is located at the top of the memory cell string 308, the drain-select gate transistor may also be referred to as a "top-select gate transistor" (i.e., TSG transistor). Each memory cell string 308 may also include a source-select gate transistor 311 at its source end. In some examples where the source-select gate transistor is located at the bottom of the memory cell string, the source-select gate transistor may also be referred to as a "bottom-selective gate (BSG) transistor." The TSG transistor 312 and the BSG transistor 311 may be controlled by corresponding top-selective gate (TSG) and bottom-selective gate (BSG) transistors and are configured to activate the corresponding memory cell string 308 during operation of the three-dimensional memory 601. In some embodiments, the sources of memory cell strings 308 within the same memory block 319 may be coupled via the same source line 314. According to some embodiments, the drain of each memory cell string 308 is coupled to a corresponding bit line 316. In some embodiments, a corresponding selection voltage may be applied to the gate of the corresponding drain-selective gate transistor 312 via one or more drain-select lines 313. In some embodiments, a corresponding selection voltage may also be applied to the gate of the corresponding source-selective gate transistor 311 via one or more source-select lines 315.

[0052] Some embodiments of this application also provide a memory system 500 including a three-dimensional memory, wherein the three-dimensional memory included in the memory system may be any example of the three-dimensional memory 601 described above. For example... Figure 3 As shown, the memory system 500 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Continue to refer to Figure 3 The memory system 500 may include a host 408 and a memory system 409 having one or more memories 407 and a memory controller 406. The host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 408 may be configured to send or receive data stored in the memory 407.

[0053] According to some embodiments, memory controller 406 is coupled to memory 407 and host 408 and is configured to control memory 407. Memory controller 406 can manage data stored in memory 407 and communicate with host 408. In some embodiments, memory controller 406 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 406 is designed to operate in high duty cycle environments in SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 406 can be configured to control the operation of memory 407, such as read, erase, and program operations. Memory controller 406 can also be configured to manage various functions regarding data stored or to be stored in memory 407, including bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 406 is also configured to process error correction codes (ECC) for data read from or written to the memory 407. The memory controller 406 may also perform any other suitable function, such as formatting the memory 407. The memory controller 406 may communicate with external devices (e.g., host 408) according to specific communication protocols. For example, the memory controller 406 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Mini-Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0054] In some cases, the memory controller 406 and one or more memories 407 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 409 can be implemented as and packaged into different types of end electronic products. Figure 4In one example shown, the memory controller 406 and a single memory 407 can be integrated into the memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may further include a connection between the memory card 502 and a host computer (e.g., Figure 3 The host (408) is electrically coupled to the memory card connector 504. In such a... Figure 5 In another example shown, the memory controller 406 and multiple memories 407 can be integrated into the SSD 506. The SSD 506 may further include interfaces for connecting the SSD 506 to a host computer (e.g., Figure 3 The host 408 is electrically coupled to the SSD connector 508. In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0055] To increase the storage capacity of 3D memory, the number of stacked layers (e.g., the number of dielectric / gate layer pairs) is increasing. However, to limit the size of the 3D memory in the thickness direction of the stacked layers, the widths of the gate and dielectric layers along the thickness direction are relatively smaller. This results in a corresponding increase in coupling (e.g., parasitic capacitive coupling) between adjacent memory cells (e.g., at the intersection of adjacent gate layers and channel structures). For example, during programming operations on the 3D memory, charge in the gate layer will inevitably be injected into the region between adjacent memory cells (hereinafter referred to as the "inter-cell region"). Therefore, the parasitic coupling phenomenon between adjacent memory cells, also known as "inter-cell interference (ICI)," affects the threshold voltage of adjacent memory cells, thereby reducing the operational (e.g., read, write, and / or data retention) performance of the memory cells.

[0056] To address the aforementioned or other problems, some embodiments of this application provide a three-dimensional memory 400. This three-dimensional memory 400 is, for example, any example of the three-dimensional memory 601 described above. Figure 6 As shown, the three-dimensional memory 400 may include a semiconductor layer 410. Optionally, the material used for the semiconductor layer 410 may include, for example, silicon (e.g., monocrystalline silicon, polycrystalline silicon), metal, or metal nitride. In some cases, the semiconductor layer 410 may also be doped, for example, by doping the semiconductor layer 410 with N-type conductive particles to improve the conductivity of the semiconductor layer 410.

[0057] In some examples, the three-dimensional memory 400 further includes a stacked layer 440 located on the semiconductor layer 410. Optionally, the stacked layer 440 may include a plurality of alternately stacked first dielectric layers 415 and conductive layers 416. Optionally, the conductive layer 416 may serve as a gate to lead out word lines, for example. In some examples, the material used for the conductive layer 416 may include, for example, metallic conductive materials such as W, Co, Cu, Al, Ti, Ta, Ni, etc. In some examples, the material used for the first dielectric layer 415 may also include, for example, polysilicon, doped silicon, metal silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof.

[0058] Continue to refer to Figure 6 In some examples, the stacked layer 440 may include a core region B1 and a stepped region B2 adjacent to the core region B1. Optionally, the stepped region B2 may include a stepped structure, each step of the stepped structure including at least one pair of first dielectric layers 416 / conductive layers 416. As an option, the stepped region B2 may be located in the middle of the core region B1; as another option, the stepped region B2 may be located on both sides of the core region B1. The three-dimensional memory 400 according to the embodiments of this application does not limit the positional relationship between the core region B1 and the stepped region B2.

[0059] In some examples, the three-dimensional memory 400 also includes an insulating layer 411 located on a stepped structure. Optionally, the surface of the insulating layer 411 away from the semiconductor layer 410 may be a substantially flat surface. The material used for the insulating layer 411 includes, for example, silicon oxide. In some cases, the insulating layer 411 may provide structural support for the subsequently formed contact structure 444.

[0060] In some examples, the core region B1 of the three-dimensional memory 400 includes multiple channel structures 420 extending through the stacked layers 440. When the conductive layer 416 serves as the gate, the intersection of the channel structure 420 and the conductive layer 416 can form the memory cell 317 described above. As an example, the channel structure 420 includes a second dielectric layer 426, a functional layer, a channel layer 424, and a dielectric core 425, arranged sequentially from the outside in.

[0061] In some examples, the second dielectric layer 426 may comprise a dielectric material (e.g., a dielectric metal oxide). For example, the second dielectric layer 426 may comprise a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than or equal to 3.9). Exemplarily, the dielectric constant of the second dielectric layer 426 may also be greater than or equal to 10. Materials used for the second dielectric layer 426 include, for example, one of AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, and / or alloys thereof.

[0062] refer to Figure 7 The second dielectric layer 426 includes, for example, a plurality of first dielectric portions 426_1 extending in the thickness direction of the stacked layer 440 and a plurality of second dielectric portions 426_2 extending in a direction parallel to the first dielectric layer 415. As an example, the thickness of the first dielectric portions 426_1 in the direction parallel to the first dielectric layer 415 and the thickness of the second dielectric portions 426_2 in the extension direction of the channel structure 420 may be substantially consistent. In some cases, the first dielectric portions 426_1 and the second dielectric portions 426_2 may be in contact with each other. In other cases, the first dielectric portions 426_1 and the second dielectric portions 426_2 may form a continuous second dielectric layer 426. As an example, a recess may be formed between the first dielectric portion 426_1 corresponding to the first dielectric layer 415 and two adjacent second dielectric portions 426_2 in a direction parallel to the first dielectric layer 415. As another example, the first dielectric portion 426_1 and the two adjacent second dielectric portions 426_2 of the corresponding conductive layer 416 may form protrusions in a direction parallel to the first dielectric layer 415. Alternatively, the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 may be covered by the corresponding first dielectric portion 426_1 and the two adjacent second dielectric portions 426_2.

[0063] According to some embodiments of the present application, the three-dimensional memory 400, since the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 can be covered by the corresponding first dielectric portion 426_1 and two adjacent second dielectric portions 426_2, when a bias voltage is applied to the conductive layer 416, the potential drop between two adjacent conductive layers 416 can be slowed down, the risk of breakdown caused by the discharge at the tip (e.g., end) of the conductive layer 416 is reduced, and the reliability of the device is improved.

[0064] Optionally, the functional layer may include, for example, a barrier layer 421, a storage layer 422, and a tunneling layer 423 disposed sequentially toward the channel layer 424. The barrier layer 421 may be used, for example, to block the transfer of charge from, for example, the conductive layer 416 to the storage layer 422 described below. The material used for the barrier layer 421 may include, for example, an insulating material such as silicon oxide.

[0065] In one option, the surface of the barrier layer 421 away from the second dielectric layer 426 is flat. When the profile shape of the surface of the barrier layer 421 away from the second dielectric layer 426 is cylindrical or conical, the flatness of the surface of the barrier layer 421 away from the second dielectric layer 426 can be understood as the cylindrical or conical surface being a smooth surface. Here, a smooth surface can be understood as smooth within the range of process tolerance, rather than absolutely smooth (e.g., a surface without obvious depressions).

[0066] Continue to refer to Figure 7 As an example, the barrier layer 421 may include a first barrier portion 421_1. This first barrier portion 421_1 may be surrounded, for example, by a first dielectric portion 426_1 along the circumferential direction of the channel structure 420. Alternatively, the first barrier portion 421_1 may be located on and in contact with the surface of the second dielectric layer 426 remote from the first dielectric layer 415. For example, the first barrier portion 421_1 may occupy a portion of the surface of the first dielectric portion 426_1 remote from the first dielectric layer 415. Optionally, the first barrier portion 421_1 may also be located in a recess formed by the first dielectric portion 426_1 and two adjacent second dielectric portions 426_2.

[0067] As an example, the barrier layer 421 may further include a second barrier portion 421_2. The second barrier portion 421_2 is, for example, at least surrounded by the conductive layer 416 in the circumferential direction along the channel structure 420. Alternatively, the second barrier portion 421_2 may be located at least on the surface of the second dielectric layer 426 away from the conductive layer 416; for example, the second barrier portion 421_2 may occupy the surface of the second dielectric portion 426_2 away from the conductive layer 416 and the surface of the first dielectric portion 426_1 away from the conductive layer 416 between two adjacent second dielectric portions 426_2.

[0068] In some examples, the thickness of the first blocking portion 421_1 is greater than the thickness of the second blocking portion 421_2 in the direction parallel to the first dielectric layer 415.

[0069] refer to Figure 7 According to some embodiments of the present application, in the direction parallel to the first dielectric layer 415, since the thickness of the first blocking portion 421_1 of the blocking layer 421 is greater than the thickness of the second blocking portion 421_2, the physical thickness of the end of the conductive layer 416 that contacts the channel structure 420 and, for example, the inter-cell region described above, in the thickness direction of the stacked layer 440 can be increased.

[0070] Typically, the dielectric constant K, physical thickness THK, and equivalent oxide thickness EOT of a film are related as follows: K = 3.9 × THK / EOT. With the dielectric constant remaining constant, the effective oxide thickness EOT is directly proportional to the physical thickness THK. Therefore, increasing the physical thickness will correspondingly increase the effective oxide thickness.

[0071] In the example where the conductive layer 416 serves as the gate, for instance, during the application of a bias voltage to the gate, the increased effective oxide layer thickness can reduce the electric field strength between the end of the conductive layer 416 in contact with the channel structure 420 and the inter-cell region. This reduces the charge leakage from the conductive layer 416 to the inter-cell region, improves the coupling between adjacent memory cells (e.g., parasitic capacitive coupling), and enhances the operational performance of the memory cells (e.g., read, write, and / or data retention).

[0072] Optionally, in some cases where the thickness of the first blocking portion 421_1 is greater than the thickness of the second blocking portion 421_2, in the direction parallel to the first dielectric layer 415, the surface of the first blocking portion 421_1 away from the second dielectric layer 426 is flush with the surface of the second blocking portion 421_2 away from the second dielectric layer 426, thereby enabling the surface of the blocking layer 421 away from the second dielectric layer 426 to remain flat. The aforementioned flat surface of the blocking layer 421 can further reduce coupling (e.g., parasitic capacitance coupling) between adjacent memory cells.

[0073] Alternatively, the first blocking portion 421_1 and the second blocking portion 421_2 may be in contact. Alternatively, the first blocking portion 421_1 and the second blocking portion 421_2 may form a continuous blocking layer 421.

[0074] Optionally, in the direction parallel to the first dielectric layer 415, the thickness of the first blocking portion 421_1 may be greater than the thickness of the second dielectric layer 426. Specifically, the thickness of the first blocking portion 421_1 may be greater than the thickness of the second dielectric portion.

[0075] During operation of the three-dimensional memory, the storage layer 422 can be used to capture charges in the channel layer 424, as described below. The material used for the storage layer 422 may include, for example, a charge-capturing material, such as silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some examples, the storage layer 422 may be located on the surface of the barrier layer 421 remote from the second dielectric layer 426. Optionally, the thickness of the storage layer 422 may be substantially consistent in any direction parallel to the first dielectric layer 415.

[0076] In some examples, the tunneling layer 423 may comprise a dielectric material through which tunneling can occur under suitable bias. The material used for the tunneling layer 423 may, for example, comprise silicon oxide, silicon oxynitride, or any combination thereof. In one example, the functional layer may be, for example, a composite layer comprising silicon oxide / silicon oxynitride / silicon oxide (ONO). As an example, the tunneling layer 423 may be located on the surface of the storage layer 422 remote from the barrier layer 421. Optionally, the thickness of the tunneling layer 423 may be substantially consistent in any direction parallel to the first dielectric layer 415.

[0077] During operation of the three-dimensional memory, charges transferred in the channel layer 424 can tunnel through the tunneling layer to the storage layer 422. The material used for the channel layer 424 includes, for example, polysilicon. In some cases, the channel layer 424 may also be conductively doped (e.g., N-type or P-type conductive doping) to improve conductivity. Optionally, the channel layer 424 may be in contact with, for example, the semiconductor layer 410.

[0078] Continue to refer to Figure 6 The channel structure 420 also includes a dielectric core 425 located within the space defined by the channel layer 424. The material used for the dielectric core 425 includes, for example, silicon oxide.

[0079] In some examples, the 3D memory 400 also includes a conductive plug (not shown) located at the end of the channel structure 420 remote from the semiconductor layer 410, the conductive plug being contactable, for example, with the channel layer 424. Optionally, the 3D memory 400 also includes a plurality of contact structures 444 located in the step region B2. Alternatively, the contact structures 444 may extend through the insulating layer 411 in the step region B2 to the conductive layer 416 of the corresponding step. When the conductive layer 416 is used as a gate, the contact structures 444 may be used to lead out word lines.

[0080] In some examples, the three-dimensional memory 400 may also include a dummy channel structure (not shown) located in the step region B2. The dummy channel structure may penetrate the insulating layer 411 and extend into the semiconductor layer 410. In some cases, the dummy channel structure may provide structural support for the step structure. Optionally, the material used for the dummy channel structure may include, for example, an insulating material such as silicon oxide. Optionally, the internal structure of the dummy channel structure may also be the same as the internal structure of the channel structure 420.

[0081] In some examples, the three-dimensional memory 400 also includes a gate line gap structure (not shown) that extends through the stacked layer 440 and into the semiconductor layer 410. Optionally, the gate line gap structure may include an isolation layer (not shown) and a conductor layer (not shown) disposed from the outside in. Optionally, the isolation layer may be used to electrically isolate the conductive layers 416 of adjacent layers.

[0082] In some examples, the three-dimensional memory 400 also includes peripheral circuitry (not shown), which includes a substrate (not shown) and peripheral circuitry structures (not shown) located on the substrate. Optionally, the peripheral circuitry structures (not shown) may include, for example, high-voltage devices for controlling high-voltage signals and / or low-voltage devices for improving read / write speeds. Optionally, the aforementioned high-voltage devices and / or low-voltage devices may include, for example, MOS transistors (not shown). Optionally, the three-dimensional memory 400 may also include an interconnect layer located on the peripheral circuitry structures.

[0083] In some cases, peripheral circuitry and memory array 301 ( Figure 1 The peripheral circuits and the memory array 301 are bonded face-to-face, and their respective interconnect layers can make corresponding contact at the bonding interface, thereby achieving electrical connection between the peripheral circuits and the memory array 301. During the operation of the three-dimensional memory, the peripheral circuits can access the memory cell strings 308 in the memory array 301 through the electrical connection between the memory array 301 and the peripheral circuits. Figure 2 (Control)

[0084] Some embodiments of this application also provide a method 300 for manufacturing a three-dimensional memory, which, for example, involves some operations for forming a channel structure 420 of the three-dimensional memory 400 described above. Figure 8 This is a flowchart of a method 300 for manufacturing a three-dimensional memory according to some embodiments of this application. Figures 9 to 27 This is a partial schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a three-dimensional memory according to some embodiments of this application.

[0085] In detailing the embodiments of this application, for ease of explanation, the cross-sectional views showing the device structure are not enlarged to scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0086] The following will combine Figures 9 to 27 The manufacturing method 300 is described in detail. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or in between any of the operations described.

[0087] refer to Figure 8 Method 300 includes operation S310, which forms a channel via in a stacked layer comprising alternating stacked first dielectric layers and material layers. Figure 9As shown, a stacked layer 440 can be formed by alternately stacking multiple first dielectric layers 415 and material layers (e.g., a first sacrificial layer 416') on a substrate (not shown) using thin film formation processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof. Optionally, the material used for the substrate may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. Exemplarily, as will be described below, the substrate can be used to provide mechanical support for structures such as channel structures 420 formed thereon and to be at least partially removed in subsequent processes.

[0088] In some examples, the number of stacked layers of the first dielectric layer 415 and the first sacrificial layer 416' in the stacked layer 440 may be, for example, 8, 32, 64, 128, or more. This application does not specifically limit the number of stacked layers of the first dielectric layer 415 and the first sacrificial layer 416'. In some cases, the materials used for the first dielectric layer 415 and the first sacrificial layer 416' may satisfy the following condition: in the same etching process, the first sacrificial layer 416' may have a higher etching selectivity than the first dielectric layer 415, so that the first dielectric layer 415 is hardly removed during the subsequent removal of the first sacrificial layer 416'. Furthermore, the materials used for the first dielectric layer 415 and the first sacrificial layer 416' may be suitable materials known in the art; for example, the first dielectric layer 415 may be an oxide layer (e.g., silicon oxide), and the first sacrificial layer 416' may be a nitride layer (e.g., silicon nitride).

[0089] In the formation of such Figure 9 In some exemplary processes following the stacked layer 440 shown, a structure such as... can be formed in the stacked layer 440 (e.g., at the location corresponding to core B1 involved in the three-dimensional memory 400 described above). Figure 11 The channel hole 404 is shown. Specifically, refer to... Figure 10 Multiple first channel holes 404' are formed in the stacked layer 440 using photolithography and etching processes. In some examples, the outline shape of the first channel holes 404' is, for example, cylindrical or conical. Exemplarily, a portion of the first dielectric layer 415 along the first channel holes 404' can be removed using dry etching, wet etching, or plasma etching to form such a structure. Figure 11 The channel hole 404 is shown.

[0090] As an example, for instance, during the process of removing a portion of the first dielectric layer 415 along the first channel hole 404' using an etching process, the first dielectric layer 415 has higher etching selectivity than the first sacrificial layer 416', thereby reducing the risk of damage to the first sacrificial layer 416'.

[0091] As an example, through the above processing, the surface of the first dielectric layer 415 along the channel hole 404 may form a recess with the adjacent first sacrificial layer 416' (e.g., two first sacrificial layers 416' along the thickness direction of the stacked layer 440).

[0092] As an example, through the above processing, the surface of the first sacrificial layer 416' exposed to the channel hole 404 is formed as a raised structure. In some cases, the thickness of the removed portion of the first dielectric layer 415 (e.g., the thickness in the direction parallel to the first dielectric layer 415) can be any suitable offset value that allows the first sacrificial layer 416' to be formed between the recessed surface (e.g., the surface along the thickness direction of the stacked layer 440) and the first dielectric layer 415 (e.g., the surface along the thickness direction of the stacked layer 440).

[0093] Back Figure 7 Method 300 includes operation S320, in which a second dielectric layer and a barrier layer are sequentially formed on the inner wall of the channel hole. (Reference) Figure 13 In some examples, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to form a second dielectric layer 426 on the inner wall of the channel hole 404.

[0094] Alternatively, a second dielectric layer 426 may be formed on the recessed surface formed by removing a portion of the first dielectric layer 415 and on the inner wall of the first channel hole 404'. Through this process, the end of the first sacrificial layer 416' in the direction parallel to the first dielectric layer 415 may be covered by the second dielectric layer 426. Specifically, the end of the first sacrificial layer 416' in the direction parallel to the first dielectric layer 415 may be covered by the first dielectric portion 426_1 (e.g., the first dielectric portion corresponding to the conductive layer 416) and two adjacent second dielectric portions 426_2 involved in the three-dimensional memory 400 described above.

[0095] In some examples, the second dielectric layer 426 may comprise a dielectric material (e.g., a dielectric metal oxide). For example, the second dielectric layer 426 may comprise a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than or equal to 3.9). Exemplarily, the dielectric constant of the second dielectric layer 426 may also be greater than or equal to 10. Materials used for the second dielectric layer 426 include, for example, one of AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, and / or alloys thereof.

[0096] Continue to refer to Figure 13 In some examples, a barrier layer 421 of suitable thickness may be formed on the surface of the second dielectric layer 426. As an example, in a direction parallel to the first dielectric layer 415, the thickness of the portion of the second dielectric layer 426 surrounded by the first dielectric layer 415 may be less than the aforementioned offset value, such that the formed barrier layer 421 can at least completely fill the depression. Optionally, the barrier layer 421 may comprise, for example, a dielectric material different from the second dielectric layer 426. Optionally, the material used for the barrier layer 421 may be selected from, for example, silicon oxide, silicon oxynitride, and silicon nitride.

[0097] refer to Figure 12 In some exemplary processes for forming the barrier layer 421, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the first barrier layer 421' on the surface of the second dielectric layer 426 via the channel hole 404. As an example, the first barrier layer 421' may at least completely fill the recess. Optionally, at least a portion of the first barrier layer 421' surrounded by the first sacrificial layer 416' may protrude toward the channel hole 404.

[0098] Continue to refer to Figure 13 In some exemplary processes that employ, for example, ALD deposition to form the first barrier layer 421', a portion of the first barrier layer 421' away from the material layer (e.g., the first sacrificial layer 416') may be removed using, for example, dry etching, wet etching, or plasma etching, to thin the thickness of the first barrier layer 421' (e.g., the thickness in the direction parallel to the first dielectric layer 415) until the barrier layer 421 is formed.

[0099] The surface of the barrier layer 421 formed by the above-described thinning process, away from the second dielectric layer 426, is flat. When the outline shape of the surface of the barrier layer 421 away from the second dielectric layer 426 is cylindrical or conical, the flatness of the surface of the barrier layer 421 away from the second dielectric layer 426 can be understood as the cylindrical or conical surface being a smooth surface. Here, a smooth surface can be understood as smooth within the range of process tolerance, rather than absolutely smooth (e.g., a surface without obvious depressions).

[0100] Continue to refer to Figure 13 Through the above processing, in the direction parallel to the first dielectric layer 415, the thickness of the portion of the barrier layer 421 surrounded by the first dielectric layer 415 along the circumferential direction of the channel hole 404 (e.g., the first barrier portion 421_1) can be greater than the thickness of at least the portion surrounded by the first sacrificial layer 416' along the circumferential direction of the channel hole 404 (e.g., the second barrier portion 421_2). Alternatively, the first barrier portion 421_1 may be located, for example, on the surface of the second dielectric layer 426 away from the first dielectric layer 415; the second barrier portion 421_2 may be located at least on the second barrier portion 421_2 on the surface of the second dielectric layer 426 away from the first sacrificial layer 416'.

[0101] refer to Figure 14 In some exemplary processes that employ, for example, CVD deposition to form the first barrier layer 421', a portion of the material layer (e.g., the first sacrificial layer 416') of the first barrier layer 421' may be removed using, for example, dry etching, wet etching, or plasma etching, to thin the thickness of the first barrier layer 421' (e.g., the thickness in the direction parallel to the first dielectric layer 415) until the surface of the second dielectric layer 426 away from the material layer (e.g., the first sacrificial layer 416') is exposed.

[0102] refer to Figure 15 In some exemplary processes following the exposure of the surface of the second dielectric layer 426 away from the material layer (e.g., the first sacrificial layer 416'), a second barrier layer 431' may be formed on the remaining portion of the first barrier layer 421' and the exposed surface of the second dielectric layer 426 away from the material layer (e.g., the first sacrificial layer 416'). Processes for forming the second barrier layer 431' include, for example, an ALD deposition process.

[0103] In some cases, the surface of the second barrier layer 431' away from the second dielectric layer 426 is flat. When the profile of the surface of the second barrier layer 431' away from the second dielectric layer 426 is cylindrical or conical, the flatness of this surface can be understood as a smooth surface. Here, "smooth surface" can be understood as smooth within the range of process tolerances, rather than absolutely smooth (e.g., a surface without obvious depressions). As an example, the remaining portion of the first barrier layer 421' and the second barrier layer 431' together constitute barrier layer 421.

[0104] Continue to refer to Figure 15Through the above processing, in the direction parallel to the first dielectric layer 415, the thickness of the portion of the barrier layer 421 surrounded by the first dielectric layer 415 along the circumferential direction of the channel hole 404 (e.g., the first barrier portion 421_1) can be greater than the thickness of at least the portion surrounded by the first sacrificial layer 416' along the circumferential direction of the channel hole 404 (e.g., the second barrier portion 421_2). Alternatively, the first barrier portion 421_1 may be located, for example, on the surface of the second dielectric layer 426 away from the first dielectric layer 415; the second barrier portion 421_2 may be located at least on the second barrier portion 421_2 on the surface of the second dielectric layer 426 away from the first sacrificial layer 416'.

[0105] The barrier layer 421 formed according to method 300 of some embodiments of this application, in the direction parallel to the first dielectric layer 415, has a first barrier portion 421_1 with a greater thickness than the second barrier portion 421_2. This increases the effective oxide layer thickness in the thickness direction of the stacked layer 440 between the end of the conductive layer 416 in contact with the channel structure 420 and, for example, the inter-cell region described above. In the example where the conductive layer 416 serves as a gate, for example during the application of a bias voltage to the gate, the increase in the effective oxide layer thickness can reduce the electric field strength between the end of the conductive layer 416 in contact with the channel structure 420 and the inter-cell region. This reduces the charge leakage from the conductive layer 416 to the inter-cell region, improves the coupling between adjacent memory cells (e.g., parasitic capacitive coupling), and enhances the operational performance (e.g., read, write, and / or data retention) of the memory cells.

[0106] according to Figure 14 and Figure 15 The exemplary process for forming the barrier layer 421 shown can employ a low-cost and relatively high-deposition-rate CVD process in forming the first barrier layer 421', and an ALD deposition process in forming the second barrier layer 431'. This approach ensures the deposition quality of the film while balancing efficiency.

[0107] refer to Figure 16In some exemplary processes following the formation of barrier layer 421, a storage layer 422 and a tunneling layer 423 may be sequentially formed on the surface of barrier layer 421 using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. During operation of the three-dimensional memory, storage layer 422 can be used to capture charges in channel layer 424, as described below. The material for storage layer 422 may include, for example, a charge-capturing material, including silicon nitride, silicon oxynitride, silicon, or any combination thereof. Tunneling layer 423 may include a dielectric material through which tunneling can occur under suitable bias. The material for tunneling layer 423 may include, for example, silicon oxide, silicon oxynitride, or any combination thereof.

[0108] Continue to refer to Figure 16 As an example, a channel layer 424 can also be formed on the surface of the tunneling layer 423 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. During operation of the three-dimensional memory, the charge transferred in the channel layer 424 can tunnel through the tunneling layer to the storage layer 422. The material used for the channel layer 424 includes, for example, polysilicon, and in some cases, the channel layer 424 can also be conductively doped (e.g., N-type conductive doping or P-type conductive doping) to improve conductivity.

[0109] Continue to refer to Figure 16 As an example, a thin-film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a dielectric core 425 within the space defined by the channel layer 424 to form the channel structure 420. Materials used for the dielectric core 425 include, for example, silicon oxide.

[0110] In some exemplary processes following the formation of the channel structure 420, a conductive plug (not shown) may also be formed on the top of the channel structure 420 away from the substrate, contacting the channel layer 424. In some examples, the conductive plug may function as a corresponding memory cell string 308. Figure 2 It serves as part of the drain electrode. Materials used for conductive plugs include, for example, polycrystalline silicon.

[0111] In other examples following the formation of the channel structure 420, a step region B2, as described in, for example, the three-dimensional memory 400, may be formed. Figure 6 The stepped structure is shown. Exemplarily, the stepped structure can be formed by performing multiple "etch-trimming" processes on alternatingly stacked first dielectric layers 415 and multiple first sacrificial layers 416'. Optionally, each step of the stepped structure includes at least one first dielectric layer / first sacrificial layer pair. Optionally, after forming the stepped structure, an insulating layer covering the stepped structure (e.g., ...) can be formed. Figure 6 Insulating layer 411 shown.

[0112] refer to Figure 18 In some exemplary processes following the formation of the channel structure 420, the first sacrificial layer 416' may be replaced with the conductive layer 416. Specifically, the first sacrificial layer 416' may be removed, and the conductive layer 416 may be formed in the space created by removing the first sacrificial layer 416'. As an example of forming the conductive layer 416, a gate gap (not shown) may be formed in the stacked layer 440, and then the first sacrificial layer 416' may be removed via the gate gap using, for example, a wet etching process, thereby forming a structure as shown in the example. Figure 17 The sacrifice space shown is 415'.

[0113] In some cases, removing the first sacrificial layer 416' to form the sacrificial space 415' can expose the surface of the second dielectric layer 426 away from the barrier layer 421. Alternatively, the sacrificial space 415' can be filled with a conductive material to form a shape such as Figure 18 The conductive layer 416 is shown. Through the above processing, the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 can be covered by the second dielectric layer 426. Specifically, the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 can be covered by the first dielectric portion involved in the three-dimensional memory 400 described above and two adjacent second dielectric portions.

[0114] The second dielectric layer 426 formed according to method 300 of some embodiments of this application can cover the end of the conductive layer 416 in a direction parallel to the first dielectric layer 415. When a bias voltage is applied to the conductive layer 416, it can slow down the potential drop between two adjacent conductive layers 416, reduce the risk of breakdown caused by discharge at the tip (e.g., end) of the conductive layer 416, and improve the reliability of the device.

[0115] Optionally, the first sacrificial layer 416' and the first dielectric layer 415 may have a high etch selectivity, such that the first dielectric layer 415 is hardly removed during the removal of the first sacrificial layer 416'. Optionally, the conductive layer 416 may be used, for example, as a gate to lead out word lines. In some examples, the material used for the conductive layer 416 may include, for example, metallic conductive materials such as W, Co, Cu, Al, Ti, Ta, and Ni.

[0116] In some examples after the formation of the conductive layer 416, an insulating material can be deposited on the inner wall of the gate gap and the gate gap can be filled with a conductive material by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0117] In the formation of such Figure 9In some other exemplary processes following the stacked layer 440 (e.g., the stacked structure), for example, a gate gap (not shown) may be formed in the stacked structure before the channel structure 420 is formed, and the first sacrificial layer 416' may be replaced with the conductive layer 416 via the gate gap.

[0118] In some specific examples, multiple second channel holes (not shown) can be formed in the stacked structure (e.g., at the location corresponding to core B1 in the three-dimensional memory 400 described above) using photolithography and etching processes. In some examples, the outline shape of the second channel holes is, for example, cylindrical or conical. Figure 19 As shown, a second sacrificial layer 425' can be filled in the second channel hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0119] As another example of forming the conductive layer 416, after forming the second sacrificial layer 425', a gate gap (not shown) can be formed in the stacked structure, and then the first sacrificial layer 416' can be removed through the gate gap using, for example, a wet etching process, thereby forming a structure as shown in the figure. Figure 20 The sacrificial space 415' is shown. In some cases, the material used for the second sacrificial layer 425' includes, for example, polycrystalline silicon. Alternatively, the sacrificial space 415' can be filled with a conductive material to form a shape such as... Figure 21 The conductive layer 416 is shown.

[0120] refer to Figure 22 In some exemplary processes following the formation of the conductive layer 416, the second sacrificial layer 425' may be removed using, for example, dry etching, wet etching, or plasma etching. During the removal of the second sacrificial layer 425' using, for example, an etching process, the second sacrificial layer 425' may have a higher etching selectivity than the first dielectric layer 415 and the conductive layer 416, thereby reducing the risk of damage to the first dielectric layer 415 and the conductive layer 416 during the removal of the second sacrificial layer 425'.

[0121] refer to Figure 23 The aforementioned channel hole 404 can be formed by removing a portion of the first dielectric layer 415 along the second channel hole using one of dry etching, wet etching, or plasma etching. As an example, for instance, during the process of removing a portion of the first dielectric layer 415 along the second channel hole using an etching process, the first dielectric layer 415 has higher etching selectivity than the conductive layer 416', thereby reducing the risk of damage to the first sacrificial layer 416'.

[0122] Through the above processing, the surface of the first dielectric layer 415 along the channel hole 404 can form a recess with the adjacent first sacrificial layer 416' (e.g., two first sacrificial layers 416' along the thickness direction of the stacked layer 440).

[0123] Through the above processing, the surface of the first sacrificial layer 416' exposed to the channel hole 404 can be formed as a raised structure. In some cases, the thickness of the removed portion of the first dielectric layer 415 (e.g., the thickness in the direction parallel to the first dielectric layer 415) can be any suitable offset value that allows the first sacrificial layer 416' to form between the recessed surface (e.g., the surface along the thickness direction of the stacked layer 440) and the first dielectric layer 415 (e.g., the surface along the thickness direction of the stacked layer 440).

[0124] refer to Figure 25 In some exemplary processes following the formation of the channel hole 404, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a second dielectric layer 426 on the inner wall of the channel hole 404.

[0125] Specifically, a second dielectric layer 426 can be formed on the recessed surface formed by removing a portion of the first dielectric layer 415 and on the inner wall of the first channel hole 404'. Through this process, the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 can be covered by the second dielectric layer 426. Specifically, the end of the conductive layer 416 in the direction parallel to the first dielectric layer 415 can be covered by the first dielectric portion and two adjacent second dielectric portions involved in the three-dimensional memory 400 described above.

[0126] The second dielectric layer 426 formed by method 300 according to some embodiments of this application can cover the end of the conductive layer 416 in a direction parallel to the first dielectric layer 415. When a bias voltage is applied to the conductive layer 416, it can slow down the potential drop between two adjacent conductive layers 416, reduce the risk of breakdown caused by tip (e.g., end) discharge of the conductive layer 416, and improve the reliability of the device.

[0127] In some examples, the second dielectric layer 426 may comprise a dielectric material (e.g., a dielectric metal oxide). For example, the second dielectric layer 426 may comprise a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than or equal to 3.9). Exemplarily, the dielectric constant of the second dielectric layer 426 may also be greater than or equal to 10. Materials used for the second dielectric layer 426 include, for example, one of AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, and / or alloys thereof.

[0128] Continue to refer to Figure 25In some examples, a barrier layer 421 of suitable thickness may be formed on the surface of the second dielectric layer 426. As an example, in a direction parallel to the first dielectric layer 415, the thickness of the portion of the second dielectric layer 426 surrounded by the first dielectric layer 415 may be less than the aforementioned offset value, such that the formed barrier layer 421 can at least completely fill the depression. Optionally, the barrier layer 421 may comprise, for example, a dielectric material different from the second dielectric layer 426. Optionally, the material used for the barrier layer 421 may be selected from, for example, silicon oxide, silicon oxynitride, and silicon nitride.

[0129] refer to Figure 24 In some exemplary processes for forming the barrier layer 421, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form the first barrier layer 421' on the surface of the second dielectric layer 426 via the channel hole 404. As an example, the first barrier layer 421' may at least completely fill the recess. Optionally, at least a portion of the first barrier layer 421' surrounded by a material layer (e.g., conductive layer 416) may also protrude toward the channel hole 404.

[0130] Continue to refer to Figure 25 In some exemplary processes that employ, for example, ALD deposition to form the first barrier layer 421', a portion of the first barrier layer 421' away from the material layer (e.g., conductive layer 416) may be removed using, for example, dry etching, wet etching, or plasma etching, to thin the thickness of the first barrier layer 421' (e.g., the thickness in the direction parallel to the first dielectric layer 415) until the barrier layer 421 is formed.

[0131] The surface of the barrier layer 421 formed by the above-described thinning process, away from the second dielectric layer 426, is flat. When the outline shape of the surface of the barrier layer 421 away from the second dielectric layer 426 is cylindrical or conical, the flatness of the surface of the barrier layer 421 away from the second dielectric layer 426 can be understood as the cylindrical or conical surface being a smooth surface. Here, a smooth surface can be understood as smooth within the range of process tolerance, rather than absolutely smooth (e.g., a surface without obvious depressions).

[0132] refer to Figure 26 In some exemplary processes that employ, for example, CVD deposition to form the first barrier layer 421', a portion of the material layer (e.g., conductive layer 416) of the first barrier layer 421' may be removed using, for example, dry etching, wet etching, or plasma etching, to thin the thickness of the first barrier layer 421' (e.g., the thickness in the direction parallel to the first dielectric layer 415) until the surface of the second dielectric layer 426 away from the material layer (e.g., conductive layer 416) is exposed.

[0133] refer to Figure 27 In some exemplary processes following the exposure of the surface of the second dielectric layer 426 away from the material layer (e.g., conductive layer 416), a second barrier layer 431' may be formed on the remaining portion of the first barrier layer 421' and the exposed surface of the second dielectric layer 426 away from the material layer (e.g., conductive layer 416). Processes for forming the second barrier layer 431' include, for example, an ALD deposition process.

[0134] In some cases, the surface of the second barrier layer 431' away from the second dielectric layer 426 is flat. When the profile of the surface of the second barrier layer 431' away from the second dielectric layer 426 is cylindrical or conical, the flatness of this surface can be understood as a smooth surface. Here, "smooth surface" can be understood as smooth within the range of process tolerances, rather than absolutely smooth (e.g., a surface without obvious depressions). As an example, the remaining portion of the first barrier layer 421' and the second barrier layer 431' together constitute barrier layer 421.

[0135] according to Figure 26 and Figure 27 The exemplary process for forming the barrier layer 421 shown can employ a low-cost and relatively high-deposition-rate CVD process in forming the first barrier layer 421', and an ALD deposition process in forming the second barrier layer 431'. This approach ensures the deposition quality of the film while balancing efficiency.

[0136] refer to Figure 25 or Figure 27 In some examples, the barrier layer 421 includes, for instance, a first barrier portion 421_1 located on the surface of the second dielectric layer 426 away from the first dielectric layer 415 and a second barrier portion 421_2 located on the surface of the second dielectric layer 426 away from the material layer (e.g., conductive layer 416). In some cases, the first barrier portion 421_1 is, for instance, surrounded by the first dielectric layer 415 in the circumferential direction of the channel hole 404, and the second barrier portion 421_2 is, for instance, surrounded by the material layer (e.g., conductive layer 416) in the circumferential direction of the channel hole 404. As an example, in a direction parallel to the first dielectric layer 415, the thickness of the portion of the second dielectric layer 426 surrounded by the first dielectric layer 415 may, for instance, be less than the thickness of the first barrier portion 421_1.

[0137] In the formation of such Figure 27 In some exemplary processes following the barrier layer 421 shown, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form a thin film on the surface of the barrier layer 421. Figure 17The storage layer 422 and tunneling layer 423 are shown. During operation of the three-dimensional memory, the storage layer 422 can be used to capture charges in, for example, the channel layer 424 described below. The material used for the storage layer 422 may include, for example, a charge-capturing material, which includes, for example, silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer 423 may include a dielectric material through which tunneling can occur under suitable bias. The material used for the tunneling layer 423 may include, for example, silicon oxide, silicon oxynitride, or any combination thereof.

[0138] Back Figure 18 As an example, a channel layer 424 can also be formed on the surface of the tunneling layer 423 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. During operation of the three-dimensional memory, the charge transferred in the channel layer 424 can tunnel through the tunneling layer to the storage layer 422. The material used for the channel layer 424 includes, for example, polysilicon, and in some cases, the channel layer 424 can also be conductively doped (e.g., N-type conductive doping or P-type conductive doping) to improve conductivity.

[0139] Continue to refer to Figure 18 As an example, a thin-film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a dielectric core 425 within the space defined by the channel layer 424 to form the channel structure 420. Materials used for the dielectric core 425 include, for example, silicon oxide.

[0140] In some exemplary processes following the formation of the channel structure 420, a conductive plug (not shown) may also be formed on the top of the channel structure 420 away from the substrate, contacting the channel layer 424. In some examples, the conductive plug may function as a corresponding memory cell string 308. Figure 2 It serves as part of the drain electrode. Materials used for conductive plugs include, for example, polycrystalline silicon.

[0141] Method 300 according to some embodiments of this application, for example, according to Figures 18 to 27 The method example shown allows the channel structure 420 to be formed after the first sacrificial layer 416' is replaced with the conductive layer 416, thus avoiding damage to the second dielectric layer 426 exposed in the sacrificial space 415' during the process of forming the channel structure 420 first and then replacing the first sacrificial layer 416' with the conductive layer 416.

[0142] In some examples, the method 300 for manufacturing a three-dimensional memory further includes forming peripheral circuitry (not shown) and bonding the peripheral circuitry to a memory array 301. In some examples, the peripheral circuitry structure may be formed on a substrate different from the substrate described above. Optionally, the peripheral circuitry structure may include, for example, high-voltage devices for controlling high-voltage signals and / or low-voltage devices for improving read / write speeds. Optionally, the aforementioned high-voltage devices and / or low-voltage devices may include, for example, MOS transistors (not shown). Optionally, an interconnect layer for interconnecting with the memory array may also be formed on the peripheral circuitry structure.

[0143] In some cases, the formed peripheral circuits and memory array 301 can be co-bonded face-to-face, with the interconnect layers of the peripheral circuits and memory array 301 respectively contacting each other at the bonding interface, thereby achieving electrical connection between the peripheral circuits and memory array 301. During the operation of the three-dimensional memory, the peripheral circuits can control the memory array 301 through the electrical connection between the memory array 301 and the peripheral circuits.

[0144] Since the structures and features described above regarding the three-dimensional memory 400 are wholly or partially applicable to the same or similar structures and features involved in the method 300 described herein, related or similar content will not be repeated.

[0145] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked layer comprising alternating stacked first dielectric layers and conductive layers; as well as The channel structure passes through the stacked layers and includes a second dielectric layer and a barrier layer arranged sequentially from the outside to the inside, wherein the dielectric constant of the second dielectric layer is greater than or equal to 3.9; Wherein, the second dielectric layer covers the end of the conductive layer in a direction parallel to the first dielectric layer, and the barrier layer includes a first barrier portion and a second barrier portion, wherein the first barrier portion is located on the surface of the second dielectric layer away from the first dielectric layer, and the second barrier portion is located on the surface of the second dielectric layer away from the conductive layer. In the direction parallel to the first dielectric layer, the thickness of the first blocking portion is greater than the thickness of the second blocking portion.

2. The three-dimensional memory according to claim 1, wherein, The surface of the barrier layer away from the second dielectric layer is flat.

3. The three-dimensional memory according to claim 1, wherein, The surface of the first blocking portion that is away from the second dielectric layer is flush with the surface of the second blocking portion that is away from the second dielectric layer.

4. The three-dimensional memory according to claim 1, wherein, The second dielectric layer includes: The first dielectric portion extends in the thickness direction of the stacked layers; and The second medium portion extends in a direction parallel to the first medium layer, wherein the first medium portion is in contact with the second medium portion.

5. The three-dimensional memory according to claim 4, wherein, In a direction parallel to the first dielectric layer, the thickness of the first blocking portion is greater than the thickness of the first dielectric portion.

6. The three-dimensional memory according to claim 1, wherein, The trench structure further includes a storage layer, a tunneling layer, and a trench layer arranged sequentially from the outside to the inside, wherein the storage layer is located on the surface of the barrier layer away from the second dielectric layer.

7. The three-dimensional memory according to claim 1, wherein, The dielectric constant of the second dielectric layer is greater than or equal to 10.

8. A memory system comprising: The three-dimensional memory as described in any one of claims 1 to 7; as well as A memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

9. The memory system according to claim 8, comprising: Solid-state drive or memory card.

10. A method for manufacturing a three-dimensional memory, characterized in that, include: Channel holes are formed in the stacked layers, the stacked layers comprising alternating stacked first dielectric layers and material layers; as well as A second dielectric layer and a barrier layer are sequentially formed on the inner wall of the channel hole, wherein the dielectric constant of the second dielectric layer is greater than or equal to 3.9; Wherein, the second dielectric layer covers the end of the material layer in a direction parallel to the first dielectric layer, and the barrier layer includes a first barrier portion and a second barrier portion, wherein the first barrier portion is located on the surface of the second dielectric layer away from the first dielectric layer, and the second barrier portion is located on the surface of the second dielectric layer away from the material layer; In the direction parallel to the first dielectric layer, the thickness of the first blocking portion is greater than the thickness of the second blocking portion.

11. The method of claim 10, wherein, Forming channel holes in the stacked layers includes: Forming a first channel hole through the stacked layers; and A portion of the first dielectric layer along the first channel hole is removed to form the channel hole.

12. The method according to claim 10 or 11, wherein, Forming the barrier layer includes: A first barrier layer is formed on the surface of the second dielectric layer; and A portion of the first barrier layer away from the material layer is removed to form the barrier layer, wherein the surface of the barrier layer away from the second dielectric layer is flat.

13. The method according to claim 10 or 11, wherein, Forming the barrier layer includes: A second barrier layer is formed on the surface of the second dielectric layer; Remove a portion of the second barrier layer away from the material layer and expose the surface of the second dielectric layer away from the material layer; and A third barrier layer is formed on the remaining portion of the second barrier layer and on the exposed surface of the second dielectric layer. The surface of the third barrier layer away from the second dielectric layer is flat, and the remaining part of the second barrier layer and the third barrier layer together form the barrier layer.

14. The method of claim 10, wherein, The material layer includes a first sacrificial layer, and the method further includes: After the barrier layer is formed, the first sacrificial layer is removed; and A conductive layer is formed in the space created by removing the first sacrificial layer.

15. The method of claim 10, wherein the material layer comprises a conductive layer, wherein, Forming the stacked layers includes: A second channel hole is formed in a stacked structure, the stacked structure comprising alternating stacked first dielectric layers and first sacrificial layers; Remove the first sacrificial layer; and The conductive layer is formed in the space created by removing the first sacrificial layer.

16. The method of claim 15, wherein, The formation of the stacked layers further includes: Before removing the first sacrificial layer, a second sacrificial layer is filled into the second channel hole; and After the conductive layer is formed, the second sacrificial layer is removed.

17. The method according to claim 16, wherein, Forming channel holes in the stacked layers includes: A portion of the first dielectric layer is removed via the second channel hole to form the channel hole.

18. The method of claim 10, further comprising: A storage layer, a tunneling layer, and a trench layer are sequentially formed on the surface of the barrier layer; as well as A dielectric core is formed within the space defined by the channel layer.

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