Semiconductor device and method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate in a vertical direction, a charge trapping layer disposed on the ferroelectric layer, a gate insulating layer disposed on the charge trapping layer, and a gate electrode layer disposed on the gate insulating layer. The charge trapping layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0116639, filed with the Korean Intellectual Property Office on September 1, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a semiconductor device including a ferroelectric layer. Background Technology

[0004] Generally, ferroelectric materials refer to materials that exhibit spontaneous polarization in the absence of an applied external electric field. Furthermore, ferroelectric materials may exhibit polarization hysteresis behavior depending on the applied electric field. Therefore, by controlling the applied electric field, one of two stable residual polarization states can be reversibly achieved on the polarization hysteresis curve. This characteristic can be applied to the non-volatile storage of "0" and "1" signal information.

[0005] Recently, research has been conducted on field-effect transistor (FET) type non-volatile memory devices that utilize ferroelectric materials in the gate dielectric layer. Write operations on the non-volatile memory device can be performed by applying a write voltage to the device to write different residual polarization states as logic information into the gate dielectric layer. Read operations on the non-volatile memory device can be performed by utilizing the variation in the resistance of the FET's channel layer according to the orientation and size of the residual polarization written into the gate dielectric layer. In other words, read operations on the non-volatile memory device can be performed by applying a read voltage to the device to read the channel current of the FET, which incorporates ferroelectric materials. Summary of the Invention

[0006] A semiconductor device according to embodiments of the present disclosure may include: a substrate, a ferroelectric layer disposed on the substrate, a charge trapping layer disposed on the ferroelectric layer, a gate insulating layer disposed on the charge trapping layer, and a gate electrode layer disposed on the gate insulating layer. The charge trapping layer may include a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

[0007] A semiconductor device according to another embodiment of the present disclosure may include: a substrate, a channel layer disposed on the substrate, a ferroelectric layer disposed on the channel layer, a charge trapping layer disposed on the ferroelectric layer, a gate insulating layer disposed on the charge trapping layer, a gate electrode layer disposed on the gate insulating layer, and a source electrode layer and a drain electrode layer disposed on the substrate respectively in contact with opposite ends of the channel layer. The charge trapping layer may include a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

[0008] In a method for manufacturing a semiconductor device according to another embodiment of the present disclosure, a substrate may be provided. A ferroelectric layer may be formed on the substrate. A two-dimensional conductive metal-organic framework having cavities may be stacked on the ferroelectric layer to form a metal-organic framework layer. In this case, the cavities of the conductive metal-organic framework may be configured to overlap each other in the thickness direction of the metal-organic framework layer. Metal particles may be placed in the overlapping cavities to form a charge-trapping layer. A gate insulating layer may be formed on the charge-trapping layer. A gate electrode layer may be formed on the gate insulating layer.

[0009] A semiconductor device according to another embodiment of the present disclosure may include: a substrate; a gate structure including a hole pattern on the substrate, the gate structure including gate electrode layers and interlayer insulating layers alternately stacked on the substrate; a gate insulating layer disposed on a sidewall surface of the gate structure exposed by the hole pattern; a charge trapping layer disposed on the sidewall surface of the gate insulating layer; a ferroelectric layer disposed on the sidewall surface of the charge trapping layer; and a channel layer disposed on the sidewall surface of the ferroelectric layer. The charge trapping layer may include a metal-organic framework layer and metal particles embedded in the metal-organic framework layer. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2A This is a schematic plan view illustrating the charge trapping layer of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2B This is a schematic perspective view showing the charge trapping layer of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B This is a schematic diagram illustrating a conductive metal-organic framework of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 4A to 4D This is a schematic view illustrating the operation of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5A This is a schematic diagram illustrating the hysteresis operation performed by the ferroelectric layer of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 5B This is a schematic diagram illustrating the memory window characteristics of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 5C This is a schematic diagram illustrating the threshold voltage characteristics of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 6 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0019] Figures 7 to 11 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 12A , Figure 12B , Figure 13A and Figure 13B This is a schematic diagram illustrating a method for forming a charge trapping layer according to an embodiment of the present disclosure.

[0021] Figures 14 to 16 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 17 This is a circuit diagram of a semiconductor device according to yet another embodiment of the present disclosure.

[0023] Figure 18 Is with Figure 17 A schematic 3D diagram of the structure of the semiconductor device corresponding to the circuit diagram.

[0024] Figure 19 yes Figure 18 A schematic cross-sectional view of the semiconductor device taken along line I-I'. Detailed Implementation

[0025] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (such as the width and thickness of the components) are enlarged to clearly illustrate the components of each device. The terminology used herein may correspond to words chosen in consideration of their function in the embodiments, and the meaning of the terms may be interpreted differently by those skilled in the art to which the embodiments pertain. If explicitly defined in detail, these terms may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0026] Furthermore, the singular form of a word should be understood to include the plural form of that word unless it is explicitly not used in the context. It should be understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, quantity, step, operation, component, element, part, or combination thereof, but are not intended to exclude the presence or possibility of adding one or more other features, quantities, steps, operations, components, elements, parts, or combinations thereof.

[0027] Furthermore, when performing a method or manufacturing method, each process constituting the method may be performed in a different order than prescribed, unless a specific order is explicitly described in the context. In other words, each process may be performed in the same manner as stated in the order, and may be performed substantially simultaneously. Moreover, at least a portion of each of the aforementioned processes may be performed in the reverse order.

[0028] Embodiments of this disclosure provide a semiconductor device including a charge trapping layer disposed between a ferroelectric layer and a gate insulating layer. The charge trapping layer includes a metal-organic framework (MOF) layer and metal particles embedded within the MOF layer. The MOF layer prevents the formation of a depolarization electric field within the ferroelectric layer, and the metal particles can increase the operating voltage range (i.e., storage window) of the semiconductor device by performing electron trapping or detrapping operations. Furthermore, the charge trapping layer can improve the robustness and polarization retention of the semiconductor device.

[0029] Figure 1 This is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 2A This is a schematic plan view illustrating the charge trapping layer of a semiconductor device according to an embodiment of the present disclosure. Figure 2B This is a schematic perspective view showing the charge trapping layer of a semiconductor device according to an embodiment of the present disclosure. Figure 3A and Figure 3B This is a schematic diagram illustrating a conductive metal-organic framework of a semiconductor device according to an embodiment of the present disclosure.

[0030] refer to Figure 1 The semiconductor device 1 may include: a substrate 101, a ferroelectric layer 110 disposed on the substrate 101, a charge trapping layer 120 disposed on the ferroelectric layer 110, a gate insulating layer 130 disposed on the charge trapping layer 120, and a gate electrode layer 140 disposed on the gate insulating layer 130. Furthermore, the semiconductor device 1 may also include a source region 103 and a drain region 105, both disposed in regions of the substrate 101 that are opposite to each other relative to the gate electrode layer 140.

[0031] Substrate 101 may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Substrate 101 may be doped with N-type or P-type dopants to become conductive.

[0032] Source region 103 and drain region 105 can be spaced apart from each other. Each of source region 103 and drain region 105 can be a doped region of substrate 101. The doping type of source region 103 and drain region 105 can be different from the doping type of substrate 101. For example, when substrate 101 is doped with P-type dopant, source region 103 and drain region 105 can be doped with N-type dopant. In another example, when substrate 101 is doped with N-type dopant, source region 103 and drain region 105 can be doped with P-type dopant.

[0033] The channel region 101c can be disposed in the substrate 101 between the source region 103 and the drain region 105. The channel region 101c can be located directly below the ferroelectric layer 110. Depending on the voltage applied to the gate electrode layer 140, a conductive channel that electrically connects the source region 103 and the drain region 105 to each other can be formed in the channel region 101c.

[0034] A ferroelectric layer 110 may be disposed on a substrate 101. The ferroelectric layer 110 may include a ferroelectric material. The ferroelectric material may have spontaneous polarization. Depending on the write voltage applied between the gate electrode layer 140 and the substrate 101, the ferroelectric material may exhibit hysteresis behavior with respect to polarization. In one example, the ferroelectric material may have a predetermined polarization determined from a polarization hysteresis curve in response to the write voltage. After the write voltage is removed, the ferroelectric material may retain a residual polarization corresponding to the predetermined polarization. The residual polarization may be used as signal information in the semiconductor device 1 and may be non-volatilely stored in the ferroelectric layer 110. That is, the ferroelectric layer 110 may be used as a storage layer of the semiconductor device 1.

[0035] In one embodiment, the ferroelectric layer 110 may comprise a metal oxide having an orthorhombic crystal structure as the ferroelectric material. The metal oxide may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In one embodiment, the ferroelectric layer 110 may comprise a dopant incorporated into the ferroelectric material. The dopant may comprise, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd), lanthanum (La), or combinations thereof. In one embodiment, the dopant may be distributed in the crystal lattice such that the ferroelectric layer 110 maintains an orthorhombic crystal structure, thereby stabilizing the ferroelectric properties of the ferroelectric layer 110.

[0036] refer to Figure 1 The charge trapping layer 120 can be disposed on the ferroelectric layer 110. The charge trapping layer 120 may include a metal-organic framework layer 122 and metal particles 124 embedded in the metal-organic framework layer 122. For example... Figure 1As shown, the diameter of the metal particles 124 can be substantially the same as the thickness of the metal-organic framework layer 122. That is, the metal particles 124 can penetrate or extend through the metal-organic framework layer 122 to contact the ferroelectric layer 110 and the gate insulating layer 130. As will be described later, because the metal-organic framework layer 122 has conductive properties, it can prevent the formation of a depolarization electric field within the ferroelectric layer 110, and by performing electron trapping or detrapping operations, the metal particles 124 can increase the operating voltage range (i.e., the storage operating window) of the semiconductor device 1. Furthermore, as will be described later, the charge trapping layer 120 can improve the robustness and polarization retention of the semiconductor device.

[0037] The metal-organic framework layer 122 may include at least two conductive metal-organic frameworks. (Reference) Figure 2A and Figure 2B In one embodiment, the metal-organic framework layer 122 comprises stacked or laminated layers. Figure 1 At least four conductive metal-organic frameworks 122a, 122b, 122c, and 122d are disposed on the ferroelectric layer 110. The at least four conductive metal-organic frameworks 122a, 122b, 122c, and 122d can be configured such that the cavities of the at least four conductive metal-organic frameworks 122a, 122b, 122c, and 122d overlap each other in the thickness direction (i.e., the z-direction) of the metal-organic framework layer 122, such as... Figure 2B As shown. The metal-organic framework layer 122 can have conductive properties. Although in Figure 2B The first to fourth conductive metal-organic frameworks 122a, 122b, 122c and 122d are shown, but the embodiments of this disclosure are not necessarily limited thereto.

[0038] Each of the first to fourth conductive metal-organic frameworks 122a, 122b, 122c, and 122d may have coordination bonds between the metal nodes and the organic ligands, and may include cavities V arranged at regular intervals. Each of the first to fourth conductive metal-organic frameworks 122a, 122b, 122c, and 122d may have a two-dimensional (2D) structure. Here, as... Figure 2AAs shown, a two-dimensional structure can refer to a sheet-like structure disposed on a two-dimensional plane. For example, a conductive metal-organic framework can be arranged into a two-dimensional hexagonal lattice structure, which forms cavities V at regular intervals or spacings. The shortest width d of the cavity V can have a size of, for example, 1 nanometer (nm) to 10 nm. The first to fourth conductive metal-organic frameworks 122a, 122b, 122c, and 122d can be made of the same material. As described below, each of the first to fourth conductive metal-organic frameworks 122a, 122b, 122c, and 122d can be conductive through bonding between the metal nodes and the organic ligands. For example, conductivity in the conductive metal-organic framework can be obtained through bonding between the d-orbitals of the metal constituting the metal node and the p-orbitals of the organic ligand.

[0039] refer to Figure 2B In the metal-organic framework layer 122, the cavities V of the first to fourth conductive metal-organic frameworks 122a, 122b, 122c and 122d can be configured to overlap or substantially overlap each other in the z-direction. The metal particles 124 can be located within the overlapping cavities V.

[0040] Each metal particle 124 can have the form of an aggregate of metal atoms. Figure 1 , Figure 2A and Figure 2B In the illustration, each metal particle 124 is depicted as spherical, but this disclosure is not limited thereto, and other three-dimensional shapes are also possible.

[0041] In one embodiment, the diameter D of the spherical metal particles 124 can have a size of, for example, 1 nm to 10 nm; however, the diameter D of the metal particles 124 can be smaller than the shortest width of the cavity V. Therefore, the metal particles 124 can be located inside the cavity V and can be regularly arranged in the metal-organic framework layer 122. The metal particles 124 can include, for example, cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), manganese (Mn), or a combination of two or more of these.

[0042] Figure 3A and Figure 3B The structural formula of a conductive metal-organic framework according to an embodiment of the present disclosure is shown. Reference Figure 3AThe conductive metal-organic framework M1 can be M3(HXTP)2 (where M is a metal, and X is oxygen (O), sulfur (S), or nitrogen (N)). As an example, when M is cobalt (Co), nickel (Ni), or copper (Cu) and X is oxygen (O), the conductive metal-organic framework M1 can be Co3(HHTP)2, Ni3(HHTP)2, or Cu3(HHTP)2, respectively. Here, the metal constituting the metal node is cobalt (Co), nickel (Ni), or copper (Cu), and the organic ligand HHTP can be hexahydroxytriphenylene. As another example, when M is iron (Fe), cobalt (Co), or platinum (Pt) and X is sulfur (S), the conductive metal-organic framework M1 can be Fe3(HTTP)2, Co3(HTTP)2, or Pt3(HTTP)2, respectively. In this case, the metal constituting the metal node is Fe, Co, or Pt, and the organic ligand HTTP can be hexathioltriphenylene. As another example, when M is cobalt (Co), nickel (Ni), or copper (Cu) and X is nitrogen (N), the conductive metal-organic framework M1 can be Co3(HITP)2, Ni3(HITP)2, or Cu3(HITP)2, respectively. In this case, the metal constituting the metal node is cobalt (Co), nickel (Ni), or copper (Cu), and the organic ligand HITP can be hexaiminotriphenylene.

[0043] refer to Figure 3B The conductive metal-organic framework M2 can be M3(HXB)2 (where M is a metal and X is oxygen (O), sulfur (S), or nitrogen (N)). For example, when M is copper (Cu) and X is oxygen (O), the conductive metal-organic framework M2 can be Cu3(HHP)2. In this case, the metal constituting the metal node is copper (Cu), and the organic ligand HHP can be hexahydrobenzene. As another example, when M is nickel (Ni) or palladium (Pd) and X is sulfur (S), the conductive metal-organic framework M2 can be Ni3(HTP)2 or Pd3(HTP)2, respectively. In this case, the metal constituting the metal node is nickel (Ni) or palladium (Pd), and the organic ligand HTP can be hexathiolbenzene. As another example, when M is manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), or copper (Cu) and X is nitrogen (N), the conductive metal-organic framework M2 can be Mn3(HAP)2, Fe3(HAP)2, Co3(HAP)2, Ni3(HAP)2, or Cu3(HAP)2, respectively. In this case, the metal constituting the metal node is manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), or copper (Cu), and the organic ligand HAP can be hexaaminobenzene.

[0044] Return to reference Figure 1 The gate insulating layer 130 may be disposed on the charge trapping layer 120. The gate insulating layer 130 may not have ferroelectric properties; that is, the gate insulating layer 130 may be non-ferroelectric. Lack of ferroelectricity may include paraelectricity or antiferroelectricity. The gate insulating layer 130 may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these. In one embodiment, the gate insulating layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer.

[0045] The gate electrode layer 140 may be disposed on the gate insulating layer 130. The gate electrode layer 140 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of the above, doped with n-type or p-type dopants.

[0046] In some embodiments, an interface insulating layer may be additionally disposed between the substrate 101 and the ferroelectric layer 110. The interface insulating layer can serve as a buffer layer to mitigate the difference in lattice constant between the substrate 101 and the ferroelectric layer 110.

[0047] As described above, the semiconductor device 1 according to embodiments of the present disclosure may be a memory device in the form of a field-effect transistor including a ferroelectric layer 110. The semiconductor device 1 may include a charge trapping layer 120 disposed between the ferroelectric layer 110 and the gate insulating layer 130. The charge trapping layer 120 may include a metal-organic framework layer 122 and metal particles 124 embedded in the metal-organic framework layer 122. As will be described later, the metal-organic framework layer 122 can prevent the formation of a depolarization electric field within the ferroelectric layer 110, and the metal particles 124 can increase the operating voltage range of the semiconductor device 1, i.e., the storage operating window, by performing charge trapping or detrapping operations. Furthermore, as will be described later, the charge trapping layer 120 can improve the durability and polarization retention of the semiconductor device 1.

[0048] Figures 4A to 4D This is a schematic view illustrating the operation of a semiconductor device according to an embodiment of the present disclosure. Figure 5A This is a schematic diagram illustrating the hysteresis operation performed by the ferroelectric layer of a semiconductor device according to an embodiment of the present disclosure. Figure 5B This is a schematic diagram illustrating the memory window characteristics of a semiconductor device according to an embodiment of the present disclosure. Figure 5C This is a schematic diagram illustrating the threshold voltage characteristics of a semiconductor device according to an embodiment of the present disclosure.

[0049] You can use the above reference. Figure 1 The semiconductor device 1 described is used to describe and Figures 4A to 4D and Figures 5A to 5C The operation of associated semiconductor devices.

[0050] refer to Figure 4A A first write operation can be performed on semiconductor device 1. Specifically, the first write operation can be performed by applying a first write voltage V1 between substrate 101 and gate electrode layer 140 using power supply 10. Substrate 101 may be conductive by including doped semiconductor material.

[0051] The method of applying the first write voltage V1 may include applying a negative bias to the gate electrode layer 140 with the substrate 101 grounded. Therefore, the polarization P inside the ferroelectric layer 110 can be aligned in one direction along the electric field formed by the first write voltage V1. The polarization P inside the ferroelectric layer 110 may have a polarization oriented from the substrate 101 toward the gate electrode layer 140. Additionally, during the first write operation, electrons e injected from the gate electrode layer 140 and moving toward the ferroelectric layer 110 can be trapped in the metal particles 124 of the charge trapping layer 120. Subsequently, after the first write operation is completed, the applied first write voltage V1 can be removed from the semiconductor device 1.

[0052] Compared to semiconductor devices without the charge trapping layer 120, in embodiments of this disclosure including the charge trapping layer 120, the first write voltage V1 applied to the semiconductor device 1 to perform the first write operation can be on a larger order of magnitude. For example, when the first write operation is performed on the semiconductor device 1, the level of the first write voltage V1 can be increased to perform additional operations to trap electrons e in the metal particles 124 of the charge trapping layer 120.

[0053] refer to Figure 4B After the first write voltage V1 is removed, the first residual polarization Pa within the ferroelectric layer 110 can be aligned. The first residual polarization Pa can have a polarization orientation substantially the same as the polarization P generated by the applied first write voltage V1. Due to the first residual polarization Pa, negative charges 110n can be distributed in the internal region of the ferroelectric layer 110 adjacent to the substrate 101, and positive charges 110p can be distributed in the internal region of the ferroelectric layer 110 adjacent to the charge trapping layer 120.

[0054] The substrate 101, comprising a semiconductor material, can have sufficient holes to shield the negative charge 110n of the adjacent ferroelectric layer 110. Furthermore, the charge-trapping layer 120, comprising a metal-organic framework layer 122, can have sufficient electrons to shield the positive charge 110p of the adjacent ferroelectric layer 110. Therefore, in embodiments of this disclosure, the generation of a depolarization electric field that could weaken the first residual polarization Pa in the ferroelectric layer 110 can be suppressed. Generally, when a ferroelectric layer and a thin film are in contact, a depolarization electric field may be generated within the ferroelectric layer, but the thin film cannot adequately shield the negative or positive charges generated by the polarization alignment of the ferroelectric layer. In embodiments of this disclosure, since the generation of the depolarization electric field is suppressed, the reliability of the residual polarization stored in the ferroelectric layer 110 can be improved.

[0055] On the other hand, when the charge trapping layer 120 is not included in the semiconductor device, the gate insulating layer 130 can be in direct contact with the ferroelectric layer 110. Because the gate insulating layer 130 comprises an insulating material, it may not have a sufficient number of electrons to shield the positive charge 110p of the ferroelectric layer 110. Therefore, a depolarization electric field that weakens the first residual polarization Pa of the ferroelectric layer 110 may be generated inside the ferroelectric layer 110. As described above, the depolarization electric field may lead to a deterioration in the signal information storage capability of the ferroelectric layer 110.

[0056] refer to Figure 4C It can target Figure 4B A second write operation is performed on a semiconductor device 1 storing a first residual polarization Pa. The second write operation can be performed by applying a second write voltage V2 between the substrate 101 and the gate electrode layer 140 of the semiconductor device 1 using a power supply 10. The second write voltage V2 can be applied by applying a positive bias to the gate electrode layer 140 with the substrate 101 grounded. Therefore, the polarization P inside the ferroelectric layer 110 can be switched and aligned in one direction along the electric field formed by the second write voltage V2. The polarization P can have a polarization oriented from the gate electrode layer 140 toward the substrate 101. Additionally, during the second write operation, electrons e trapped in the metal particles 124 of the charge trapping layer 120 can escape from the metal particles 124 and move to the gate electrode layer 140. Subsequently, after the second write operation is completed, the applied second write voltage V2 can be removed from the semiconductor device 1.

[0057] When a second write voltage V2 is applied to switch the polarization P inside the ferroelectric layer 110, the applied second write voltage V2 needs to overcome the potential formed by the electrons e trapped in the metal particles 124 of the charge trapping layer 120. Therefore, compared with the case where the semiconductor device 1 does not include the charge trapping layer 120, in this embodiment where the semiconductor device includes the charge trapping layer 120, the level of the second write voltage V2 applied to the semiconductor device 1 to perform the second write operation can be relatively increased.

[0058] refer to Figure 4D After the second write voltage V2 is removed, the second residual polarization Pb can be aligned within the ferroelectric layer 110. The second residual polarization Pb can have substantially the same polarization orientation as the polarization P generated by applying the second write voltage V2. Due to the second residual polarization Pb, positive charges 110p can be distributed in the internal region of the ferroelectric layer 110 adjacent to the substrate 101, while negative charges 110n can be distributed in the internal region of the ferroelectric layer 110 adjacent to the charge trapping layer 120.

[0059] The substrate 101 may be doped with a dopant and may have a sufficient number of electrons to shield the positive charge 110p of the ferroelectric layer 110. Furthermore, the charge trapping layer 120, including the metal-organic framework layer 122, may have a sufficient number of holes to shield the negative charge 110n of the ferroelectric layer 110. Therefore, the generation of a depolarization electric field that weakens the second remanent polarization Pb within the ferroelectric layer 110 can be suppressed. As a result, the reliability and stability of the remanent polarization stored in the ferroelectric layer 110 can be improved.

[0060] Figure 5A A first hysteresis curve 501a and a second hysteresis curve 502a of a semiconductor device are shown. The first hysteresis curve 501a may be a graph characterizing a semiconductor device 1 including a charge trapping layer 120 according to an embodiment of the present disclosure. The second hysteresis curve 502a may be a graph characterizing a semiconductor device in a comparative example in which the charge trapping layer 120 is omitted from the semiconductor device.

[0061] The first hysteresis curve 501a may include a first remanent polarization Pr1 and a second remanent polarization Pr2, as well as a first coercive field Ec1 and a second coercive field Ec2. The second hysteresis curve 502a may include a first remanent polarization Pr1 and a second remanent polarization Pr2, as well as a third coercive field EcA and a fourth coercive field EcB. The first remanent polarization Pr1 may correspond to... Figure 4B The first remanent polarization Pa, and the second remanent polarization Pr2 can correspond to Figure 4D The second residual polarization Pb.

[0062] Compared to the second hysteresis curve 502a, the first hysteresis curve 501a can have a larger storage operation window, which is proportional to the width between paired coercive fields. For example, the first storage operation window MWp of the first hysteresis curve 501a can be larger than the second storage operation window MWc of the second hysteresis curve 502a. The increase in the storage operation window size can be due to the increase in the first write voltage V1 level during the first write operation to additionally perform the operation of trapping electrons e in the metal particles 124 of the charge trapping layer 120. Furthermore, the increase in the storage operation window size can be due to the increase in the second write voltage V2 level required to overcome the potential formed by the electrons e trapped in the metal particles 124 of the charge trapping layer 120 during the second write operation. As a result, with respect to the first hysteresis curve 501a, the operating voltage range (i.e., the storage operation window) of the semiconductor device can be increased compared to the second hysteresis curve 502a. Therefore, due to the increase in the storage operation window, the voltage interval between multiple write voltages can be increased in a semiconductor device storing multi-level residual polarization as signal information. As a result, the operational reliability of storage in semiconductor devices can be improved.

[0063] Figure 5B A first memory window curve 501b and a second memory window curve 502b of a semiconductor device are shown. The first memory window curve 501b may be a graph characterizing a semiconductor device 1 including a charge trapping layer 120 according to an embodiment of the present disclosure. The second memory window curve 502b may be a graph characterizing a semiconductor device in a comparative example in which the charge trapping layer 120 is omitted from the semiconductor device.

[0064] As referenced above Figure 5A In its initial state, the storage window V1i of the semiconductor device 1 according to an embodiment of the present disclosure can be larger than the storage window V2i of the semiconductor device of the comparative example. As the number of operation cycles of the semiconductor devices in this embodiment and the comparative example increases, the storage window of the comparative semiconductor device shown in the second storage window curve 502b is significantly smaller than the storage window of the embodiment of the present disclosure in the first storage window curve 501b. This difference in the semiconductor device of the comparative example may be due to electrons flowing from the gate electrode layer through the gate insulating layer into the ferroelectric layer during the first write operation. Electrons may be pinned to ferroelectric domains or defect sites inside the ferroelectric layer, thereby hindering the polarization transition of the ferroelectric layer. However, according to embodiments of the present disclosure, a charge trapping layer, such as charge trapping layer 120, traps electrons injected from the gate electrode layer to effectively prevent electrons from moving into the ferroelectric layer. Therefore, the durability of the semiconductor device 1 according to an embodiment of the present disclosure can be improved.

[0065] Figure 5CA first threshold voltage curve 501c, a second threshold voltage curve 501d, a third threshold voltage curve 502c, and a fourth threshold voltage curve 502d of a semiconductor device are shown. The first threshold voltage curve 501c and the second threshold voltage curve 501d can be graphs characterizing a semiconductor device 1 including a charge trapping layer 120 according to an embodiment of the present disclosure. The third threshold voltage curve 502c and the fourth threshold voltage curve 502d can be graphs characterizing a semiconductor device in a comparative example in which the charge trapping layer is omitted from the comparative semiconductor device.

[0066] refer to Figure 5C In semiconductor device 1, it is possible to Figure 4A A first write voltage V1 is applied to the gate electrode layer 140 to write into the ferroelectric layer 110. Figure 4B The first residual polarization Pa. Subsequently, the change of the threshold voltage of semiconductor device 1 over time can be represented by the first threshold voltage curve 501c. The threshold voltage may be affected by the change of the first residual polarization Pa. The level of the threshold voltage along the first threshold voltage curve 501c can decrease over time from the initial threshold voltage V1c. In addition, by applying to the gate electrode layer 140 Figure 4C The second write voltage V2 can be used to write into the ferroelectric layer 110. Figure 4D The second residual polarization Pb. Subsequently, the change of the threshold voltage of semiconductor device 1 over time can be represented by the second threshold voltage curve 501d. The level of the threshold voltage along the second threshold voltage curve 501d increases over time from the initial threshold voltage V1d.

[0067] Simultaneously, in the semiconductor device according to the comparative example, a first write voltage with negative polarity is applied to the gate electrode layer to write a first residual polarization in the ferroelectric layer. Subsequently, the change of the threshold voltage of the semiconductor device according to the comparative example over time can be represented by a third threshold voltage curve 502c. The level of the threshold voltage along the third threshold voltage curve 502c decreases over time from the initial threshold voltage V2c. Furthermore, a second write voltage with positive polarity is applied to the gate electrode layer to write a second residual polarization in the ferroelectric layer. Subsequently, the change of the threshold voltage of the semiconductor device according to the comparative example over time can be represented by a fourth threshold voltage curve 502d. The level of the threshold voltage along the fourth threshold voltage curve 502d increases over time from the initial threshold voltage V2d.

[0068] Refer again Figure 5CThe change in threshold voltage of the semiconductor device 1 according to embodiments of the present disclosure can be less than the change in threshold voltage of the semiconductor device according to the comparative example. In embodiments of the present disclosure, the charge trapping layer 120 suppresses or reduces the formation of a depolarization electric field within the ferroelectric layer 110. Therefore, the polarization retention of the semiconductor device 1 according to embodiments of the present disclosure can be improved, and the result can be a relatively small change in threshold voltage.

[0069] Figure 6 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. Reference Figure 6 ,and Figure 1 Compared to semiconductor device 1, semiconductor device 2 may further include a channel layer 202 disposed between substrate 201 and ferroelectric layer 210. In addition, in semiconductor device 2, source electrode layer 203 and drain electrode layer 205, which correspond to source region 103 and drain region 105 of semiconductor device 1, respectively, may be disposed on substrate 201.

[0070] Semiconductor device 2 may include: a substrate 201, a channel layer 202 disposed on the substrate 201, a ferroelectric layer 210 disposed on the channel layer 202, a charge trapping layer 220 disposed on the ferroelectric layer 210, a gate insulating layer 230 disposed on the charge trapping layer 220, and a gate electrode layer 240 disposed on the gate insulating layer 230. Furthermore, semiconductor device 2 may include a source electrode layer 203 and a drain electrode layer 205, which are respectively configured to contact opposite ends of the channel layer 202.

[0071] The arrangement of substrate 201, ferroelectric layer 210, charge trapping layer 220, gate insulating layer 230, and gate electrode layer 240 can be consistent with... Figure 1 The substrate 101, ferroelectric layer 110, charge trapping layer 120, gate insulating layer 130 and gate electrode layer 140 are configured in essentially the same way.

[0072] refer to Figure 6 The channel layer 202 may include a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), or gallium arsenide (GaAs). As another example, the semiconductor material may include a two-dimensional (2D) semiconductor material. The 2D semiconductor material may include transition metal dichalcogenide (TMDC) or black phosphorus. The transition metal dichalcogenide may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), or gallium selenide (GaSe). The semiconductor material may include, for example, a metal oxide, such as indium gallium zinc oxide (IGZO). The channel layer 202 may be conductive. As an example, the channel layer 202 may be doped with n-type or p-type dopants.

[0073] exist Figure 6In this embodiment, the channel layer 202 is configured to contact the substrate 201, but embodiments of this disclosure are not limited to this configuration. In some embodiments, various functional layers may be disposed between the substrate 201 and the channel layer 202. As an example, at least one conductive pattern and at least one insulating pattern may be disposed between the substrate 201 and the channel layer 202.

[0074] exist Figure 6 In this embodiment, the channel layer 202 is disposed on a plane parallel to the surface 201S of the substrate 201, but the embodiments of this disclosure are not limited to this configuration. In some embodiments, the channel layer 202 may be disposed on a plane substantially perpendicular to the surface 201S of the substrate 201. That is, the channel layer 202 may extend in a direction substantially perpendicular to the surface 201S of the substrate 201.

[0075] The source electrode layer 203 and the drain electrode layer 205 may be disposed at different or opposite ends of the channel layer 202. Each of the source electrode layer 203 and the drain electrode layer 205 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof, doped with n-type or p-type dopants.

[0076] Figures 7 to 11 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 12A , Figure 12B , Figure 13A and Figure 13B This is a schematic diagram illustrating a method for forming a charge trapping layer according to an embodiment of the present disclosure.

[0077] refer to Figure 7 A substrate 101 may be provided. The substrate 101 may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs), etc. The substrate 101 may be doped with an N-type dopant or a P-type dopant to be conductive.

[0078] Next, a ferroelectric layer 110 may be formed on the substrate 101. The ferroelectric layer 110 may include a ferroelectric material. In one embodiment, the ferroelectric layer 110 may include a metal oxide having an orthorhombic crystal structure as the ferroelectric material. The metal oxide may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In one embodiment, the ferroelectric layer 110 may include a dopant doped into the ferroelectric material. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd), lanthanum (La), or a combination thereof.

[0079] The ferroelectric layer 110 can be formed by, for example, using a deposition method such as chemical vapor deposition or atomic layer deposition. Dopant can be implanted into the ferroelectric layer 110 during the deposition process.

[0080] refer to Figure 8 A metal-organic framework layer 122 can be formed on the ferroelectric layer 110. For example... Figure 12A and Figure 12B As shown, the metal-organic framework layer 122 can be formed by sequentially stacking multiple conductive metal-organic frameworks 122a, 122b, 122c, and 122d having a two-dimensional structure including cavities V. The cavities V of the multiple conductive metal-organic frameworks 122a, 122b, 122c, and 122d stacked on the ferroelectric layer 110 can overlap each other in the z-direction. Figure 12A This is a planar schematic diagram of the metal-organic framework layer 122, and Figure 12B This is a schematic three-dimensional view of metal-organic framework layer 122.

[0081] Each of the plurality of conductive metal-organic frameworks 122a, 122b, 122c, and 122d may include a metal node and an organic ligand bonded to the metal node. In one embodiment, each of the plurality of conductive metal-organic frameworks 122a, 122b, 122c, and 122d may be a bonded organic ligand. Figure 3A and Figure 3B The described conductive metal-organic framework M1 or M2.

[0082] In one embodiment, the metal-organic framework layer 122 can be formed by a deposition method using a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand. The deposition method may include, for example, atomic layer deposition or chemical vapor deposition. A first conductive metal-organic framework can be formed on the ferroelectric layer 110 by the deposition method, and then a second conductive metal-organic framework can be stacked on the first conductive metal-organic framework using the same deposition method. As described above, the metal-organic framework layer 122 can be formed by sequentially stacking conductive metal-organic frameworks using a deposition method.

[0083] In another embodiment, the process of forming the metal-organic framework layer 122 may include: a process of preparing a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand; a process of synthesizing a conductive metal-organic framework using the first and second precursors; and a process of coating the synthesized conductive metal-organic framework onto a ferroelectric layer. The process of synthesizing the conductive metal-organic framework may be carried out in a solution state or a vapor state.

[0084] refer to Figure 12A and Figure 12B Each of the multiple conductive metal-organic frameworks 122a, 122b, 122c, and 122d can have a 2D structure. For example, the conductive metal-organic frameworks can be arranged in a hexagonal lattice structure, which forms cavities V at regular intervals or spacings. Therefore, the shortest width d of the cavity V can be determined by the materials constituting the metal nodes and the organic ligands. The shortest width d of the cavity V can have a size of, for example, 1 nm to 10 nm.

[0085] Refer again Figure 9 The charge trapping layer 120 can be formed by positioning the metal particles 124 within the metal-organic framework layer 122. In one embodiment, such as Figure 13A and Figure 13B As shown, a charge trapping layer 120 can be formed by forming metal particles 124 in the interior space of the overlapping cavities V of multiple conductive metal-organic frameworks 122a, 122b, 122c and 122d. Figure 13A This is a schematic plan view of the charge trapping layer 120, and Figure 13B This is a schematic three-dimensional view of the charge trapping layer 120.

[0086] In one embodiment, the process of forming the charge trapping layer 120 may include: a process of providing a metal-organic framework layer 122 with a precursor comprising a metal, and a process of reducing the metal of the precursor and growing the metal into metal particles 124 in the interior space of the overlapping cavity V of the metal-organic framework layer 122.

[0087] In another embodiment, the process of forming the charge trapping layer 120 may include: a process of depositing a metal thin film to fill the interior space of the overlapping cavity V of the metal-organic framework layer 122 on the ferroelectric layer 110, and a process of forming metal particles 124 by removing portions of the metal thin film deposited outside the cavity V. The process of removing portions of the metal thin film may be performed, for example, by polishing.

[0088] The metal particles 124 formed by the above method can have an aggregated form of metal atoms. The metal particles 124 can have a three-dimensional shape, such as, for example, spherical. In one embodiment, the diameter D of the spherical metal particles 124 can, for example, be from 1 nm to 10 nm. The diameter D of the metal particles 124 can be smaller than the shortest width d of the cavity V. Therefore, the metal particles 124 can be located inside the cavity V and can be regularly arranged in the metal-organic framework layer 122. The metal particles 124 can include, for example, cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), manganese (Mn), or combinations of two or more of these.

[0089] refer to Figure 10 A gate insulating layer 130 can be formed on the charge trapping layer 120. The gate insulating layer 130 can be non-ferroelectric. The gate insulating layer 130 can include, for example, oxides, nitrides, oxynitrides, or combinations of two or more of these. In one embodiment, the gate insulating layer 130 can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The gate insulating layer 130 can be formed by, for example, using chemical vapor deposition or atomic layer deposition.

[0090] Subsequently, a gate electrode layer 140 can be formed on the gate insulating layer 130. The gate electrode layer 140 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The gate electrode layer 140 may be formed by, for example, using chemical vapor deposition or atomic layer deposition.

[0091] refer to Figure 11The ferroelectric layer 110, charge trapping layer 120, gate insulating layer 130 and gate electrode layer 140 can be patterned on the substrate 101 to selectively expose the substrate 101. As a patterning process, photolithography and etching processes can be applied, for example.

[0092] Subsequently, dopant I can be implanted into the exposed substrate 101 to form source region 103 and drain region 105. The type of dopant used in source region 103 and drain region 105 can be different from the type of dopant in substrate 101. For example, when substrate 101 is doped with a P-type dopant, source region 103 and drain region 105 can be doped with an N-type dopant. In another example, when substrate 101 is doped with an N-type dopant, source region 103 and drain region 105 can be doped with a P-type dopant. As an example, an ion implantation method can be used for the dopant I implantation process.

[0093] although Figures 7 to 11 As not shown, in some embodiments, an interface insulating layer may be formed between the substrate 101 and the ferroelectric layer 110. The interface insulating layer can act as a buffer layer to mitigate the difference in lattice constant between the substrate 101 and the ferroelectric layer 110. The interface insulating layer may include, for example, oxides, nitrides, or oxynitrides. The interface insulating layer can be formed by, for example, chemical vapor deposition or atomic layer deposition.

[0094] The semiconductor device according to the embodiments of this disclosure can be manufactured using the above-described process. The method for manufacturing the semiconductor device described above can be used to manufacture... Figure 1 Semiconductor devices 1.

[0095] Figures 14 to 16 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Figures 14 to 16 Can be used to manufacture Figure 6 2. Semiconductor devices.

[0096] refer to Figure 14 A substrate 201 can be provided. The substrate 201 can be with... Figure 7 The substrate 101 is substantially the same. Optionally, the substrate 201 may be an insulating substrate or a conductive substrate.

[0097] Next, a channel layer 202 can be formed on the substrate 201. The channel layer 202 may include a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), or gallium arsenide (GaAs). As another example, the semiconductor material may include a two-dimensional (2D) semiconductor material. The 2D semiconductor material may include transition metal dichalcogenide (TMDC) or black phosphorus. The transition metal dichalcogenide may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), or gallium selenide (GaSe). The semiconductor material may include, for example, a metal oxide, such as indium gallium zinc oxide (IGZO). The channel layer 202 may be conductive. As an example, the channel layer 202 may be doped with an n-type dopant or a p-type dopant. The channel layer 202 can be formed by, for example, applying chemical vapor deposition or atomic layer deposition.

[0098] Next, a ferroelectric layer 210 can be formed on the channel layer 202. The ferroelectric layer 210 can interact with... Figure 7 The ferroelectric layer 110 is essentially the same. The method for forming the ferroelectric layer 210 can be the same as... Figure 7 The method for forming the ferroelectric layer 110 is essentially the same.

[0099] refer to Figure 15 A charge trapping layer 220, a gate insulating layer 230, and a gate electrode layer 240 can be formed on the ferroelectric layer 210. The process for forming the charge trapping layer 220, the gate insulating layer 230, and the gate electrode layer 240 can be combined with the above. Figures 8 to 10 The processes for forming the charge trapping layer 120, the gate insulating layer 130, and the gate electrode layer 140 are substantially the same.

[0100] refer to Figure 16 The channel layer 202, ferroelectric layer 210, charge trapping layer 220, gate insulating layer 230, and gate electrode layer 240 can be patterned to selectively expose the substrate 201. The patterning process can be performed by applying, for example, photolithography and etching processes.

[0101] Next, a source electrode layer 203 and a drain electrode layer 205 can be formed on the exposed portion of the substrate 201. The source electrode layer 203 and the drain electrode layer 205 can be formed to contact the opposite ends of the channel layer 202, respectively. The source electrode layer 203 and the drain electrode layer 205 can be formed, for example, by applying chemical vapor deposition or atomic layer deposition.

[0102] Each of the source electrode layer 203 and the drain electrode layer 205 may include a conductive material. The conductive material may include, for example, a doped semiconductor, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more of these doped with n-type or p-type dopants. Using the above method, a semiconductor device according to another embodiment of this disclosure can be manufactured.

[0103] In some embodiments, in forming Figure 14 Before the channel layer 202, at least one conductive layer and at least one insulating layer may be formed. The conductive and insulating layers may form various functional layers in the semiconductor device. For example, functional layers may include interconnect layers.

[0104] Figure 17 This is a circuit diagram of a semiconductor device according to yet another embodiment of the present disclosure. Figure 18 Is with Figure 17 A schematic 3D diagram of the semiconductor device structure corresponding to the circuit diagram. Figure 19 yes Figure 18 A schematic cross-sectional view of a semiconductor device taken along line I-I'.

[0105] refer to Figure 17 The semiconductor device may include a memory element unit U. Each memory element unit U may include transistor-type first to fourth memory units MC1, MC2, MC3, and MC4. The first to fourth memory units MC1, MC2, MC3, and MC4 may be connected in series between the source line SL and the bit electrode BL. The memory element unit U may be a NAND type memory device, wherein the first to fourth memory units MC1, MC2, MC3, and MC4 are electrically connected in series.

[0106] The first to fourth memory cells MC1, MC2, MC3, and MC4 can be non-volatile memory elements, and can respectively include first to fourth ferroelectric elements FL1, FL2, FL3, and FL4 corresponding to the gate dielectric layer of the transistor. The first to fourth memory cells MC1, MC2, MC3, and MC4 can respectively include first to fourth gate electrodes GL1, GL2, GL3, and GL4 connected to different word lines.

[0107] refer to Figure 18 and Figure 19Semiconductor device 3 may include first to fourth memory cells MC1, MC2, MC3, and MC4, each memory cell having the form of a transistor with a three-dimensional structure. Semiconductor device 3 may have Figure 17 The circuit configuration of the storage element unit U.

[0108] Semiconductor device 3 may include a substrate 301 and a gate structure 320 disposed on the substrate 301. Furthermore, the gate structure 320 may include a via pattern 31. The via pattern 31 may expose the sidewall surfaces of the gate structure 320. Additionally, semiconductor device 3 may include: a gate insulating layer 330 disposed on the sidewall surfaces of the gate structure 320, a charge trapping layer 340 disposed on the gate insulating layer 330, a ferroelectric layer 350 disposed on the charge trapping layer, and a channel layer 360 disposed on the ferroelectric layer 350.

[0109] Furthermore, the semiconductor device 3 may include a substrate insulating layer 302 and a lower channel contact layer 310 disposed between the substrate 301 and the gate structure 320. The lower channel contact layer 310 may contact one end of the channel layer 360 and the substrate insulating layer 302. In addition, the semiconductor device 3 may include an upper channel contact layer 370 that contacts the other end of the channel layer 360.

[0110] refer to Figure 18 and Figure 19 The substrate 301 may include a semiconductor material. A substrate insulating layer 302 may be disposed on the substrate 301. The substrate insulating layer 302 may electrically insulate the under-channel contact layer 310 from the substrate 301. The substrate insulating layer 302 may include an insulating material. Although not shown, an integrated circuit may be disposed between the substrate 301 and the substrate insulating layer 302. The integrated circuit may include circuitry for driving and controlling a plurality of memory cells of the semiconductor device 3.

[0111] The under-channel contact layer 310 may be disposed on the substrate insulating layer 302. The under-channel contact layer 310 may be electrically connected to the channel layer 360. Although not shown, the under-channel contact layer 310 may be electrically connected to the source line. The under-channel contact layer 310 may include a conductive material.

[0112] A gate structure 320 may be disposed on the under-channel contact layer 310. The gate structure 320 may include first to fourth gate electrode layers 322a, 322b, 322c, and 322d, and first to fifth interlayer insulating layers 323a, 323b, 323c, 323d, and 323e, which are alternately stacked along a first direction (i.e., the z-direction) perpendicular to the surface 301S of the substrate 301. The first interlayer insulating layer 323a may be configured as the under-channel contact layer 310. The fifth interlayer insulating layer 323e may be configured as the uppermost layer of the gate structure 320. Each of the first to fourth gate electrode layers 322a, 322b, 322c, and 322d may include a conductive material. Each of the first to fifth interlayer insulating layers 323a, 323b, 323c, 323d, and 323e may include an insulating material.

[0113] like Figure 18 and Figure 19 As shown, the number of gate electrode layers in the gate structure 320 is not necessarily limited to four. In other embodiments, the number of gate electrode layers can be different, and the interlayer insulating layer can insulate different numbers of gate electrode layers from each other in the first direction (i.e., the z-direction).

[0114] refer to Figure 18 and Figure 19 A hole pattern 31 can be formed to penetrate the gate structure 320 and expose the contact layer 310 under the channel. The hole pattern 31 can be formed, for example, by photolithography and etching processes.

[0115] The gate insulating layer 330 can be configured to cover the sidewall surface inside the hole pattern 31 of the gate structure 320. The gate insulating layer 330 may include an insulating material. The configuration of the gate insulating layer 330 material can be as described above. Figure 1 , Figure 2A and Figure 2B The configuration of the gate insulating layer 130 material of the semiconductor device 1 described is substantially the same.

[0116] The charge trapping layer 340 may be disposed on the sidewall surface of the gate insulating layer 330. The charge trapping layer 340 may include a metal-organic framework layer 342 and metal particles 344 embedded in the metal-organic framework layer 342.

[0117] The diameter of the metal particle 344 can be substantially the same as the thickness of the metal-organic framework layer 342. Therefore, the metal particle 344 can penetrate or extend through the metal-organic framework layer 342 to contact the gate insulating layer 330 and the ferroelectric layer 350. The configuration of the metal-organic framework layer 342 and the metal particle 344 can be as described above. Figure 1 , Figure 2A and Figure 2BThe metal-organic framework layer 122 and the metal particles 124 of the semiconductor device 1 described are substantially the same.

[0118] The ferroelectric layer 350 can be disposed on the sidewall surface of the charge trapping layer 340. The configuration of the ferroelectric layer 350 can be the same as described above. Figure 1 , Figure 2A and Figure 2B The configuration of the ferroelectric layer 110 of the semiconductor device 1 described is substantially the same.

[0119] The channel layer 360 can be configured to contact the ferroelectric layer 350. The channel layer 360 can extend within the hole pattern 31 in a direction substantially perpendicular to the surface 301S of the substrate 301 (e.g., in the z-direction). The channel layer 360 can comprise a semiconductor material. The channel layer 360 can be doped with a dopant and can be conductive. The configuration of the channel layer 360 can be related to a reference... Figure 6 The configuration of the channel layer 202 of the semiconductor device 2 described is substantially the same.

[0120] refer to Figure 18 and Figure 19 The upper contact layer 370 may be disposed on the channel layer 360. The upper contact layer 370 may be electrically connected to a bit line (not shown). The upper contact layer 370 may include a conductive material. The upper contact layer 370 may be made of the same material as the lower contact layer 310.

[0121] As described above, semiconductor device 3 can have the same characteristics as... Figure 17The circuit configuration of the memory element cell U corresponds to the device structure. As an example, the first memory cell MC1 may include: a first gate electrode layer 322a, a portion of the gate insulating layer 330 electrically controlled by the first gate electrode layer 322a, a portion of the charge trapping layer 340 electrically controlled by the first gate electrode layer 322a, a portion of the ferroelectric layer 350 electrically controlled by the first gate electrode layer 322a, and a portion of the channel layer 360 electrically controlled by the first gate electrode layer 322a. As another example, the second memory cell MC2 may include: a second gate electrode layer 322b, a portion of the gate insulating layer electrically controlled by the second electrode layer 322b, a portion of the charge trapping layer 340 electrically controlled by the second gate electrode layer 322b, a portion of the ferroelectric layer 350 electrically controlled by the second electrode layer 322b, and a portion of the channel layer 360 electrically controlled by the second gate electrode layer 322b. As another example, the third memory cell MC3 may include: a third gate electrode layer 322c, a portion of the gate insulating layer 330 electrically controlled by the third gate electrode layer 322c, a portion of the charge trapping layer 340 electrically controlled by the third gate electrode layer 322c, a portion of the ferroelectric layer 350 electrically controlled by the third electrode layer 322c, and a portion of the channel layer 360 electrically controlled by the third gate electrode layer 322c. As yet another example, the fourth memory cell MC4 may include: a fourth gate electrode layer 322d, a portion of the gate insulating layer 330 electrically controlled by the fourth gate electrode layer 322d, a portion of the charge trapping layer 340 electrically controlled by the fourth gate electrode layer 322d, a portion of the ferroelectric layer 350 electrically controlled by the fourth gate electrode layer 322d, and a portion of the channel layer 360 electrically controlled by the fourth gate electrode layer 322d.

[0122] As described above, according to embodiments of the present disclosure, a semiconductor device including a charge trapping layer disposed between a ferroelectric layer and a gate insulating layer can be implemented in various forms. The charge trapping layer may include a metal-organic framework layer in which metal particles are embedded.

[0123] A charge-trapping layer can prevent the formation of a depolarization electric field in the ferroelectric layer and can increase the operating voltage range of the semiconductor device, i.e., the storage operating window, through electron trapping and detrapping operations. Furthermore, it can improve the robustness and polarization retention of the semiconductor device. As a result, the operating performance of ferroelectric semiconductor devices can be improved.

[0124] Embodiments of this disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure and the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A ferroelectric layer is disposed on the substrate; A charge trapping layer is disposed on the ferroelectric layer; A gate insulating layer is disposed on the charge trapping layer; as well as The gate electrode layer is disposed on the gate insulating layer. The charge trapping layer comprises a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

2. The semiconductor device according to claim 1, further comprising: The source and drain regions are respectively located in different regions of the substrate.

3. The semiconductor device according to claim 1, wherein, The ferroelectric layer includes at least one selected from hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

4. The semiconductor device according to claim 1, wherein, The metal-organic framework layer includes a two-dimensional conductive metal-organic framework with cavities.

5. The semiconductor device according to claim 4, in, The metal-organic framework layer comprises at least two conductive metal-organic frameworks stacked on the ferroelectric layer. Wherein, the cavities of the at least two conductive metal-organic frameworks are configured to overlap each other in the thickness direction of the metal-organic framework layer, and The metal particles are disposed inside overlapping cavities.

6. The semiconductor device according to claim 4, wherein, The conductive metal-organic framework includes at least one selected from hexahydroxybenzophenanthrene, hexaiminobenzophenanthrene, hexathiobenzophenanthrene, hexahydrobenzene, hexaaminobenzene, and hexathiobenzene.

7. The semiconductor device according to claim 1, wherein, The metal particles include at least one selected from cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mn).

8. The semiconductor device according to claim 1, wherein, The metal particles trap or detrap charges according to the polarity of the voltage applied between the gate electrode layer and the substrate.

9. The semiconductor device according to claim 1, wherein, The metal particles are regularly arranged in the metal-organic framework layer.

10. A semiconductor device, comprising: Substrate; A channel layer is disposed on the substrate in the vertical direction; A ferroelectric layer is disposed on the channel layer; A charge trapping layer is disposed on the ferroelectric layer; A gate insulating layer is disposed on the charge trapping layer; A gate electrode layer is disposed on the gate insulating layer; as well as The source electrode layer and the drain electrode layer are configured to contact opposite ends of the channel layer on the substrate. The charge trapping layer comprises a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

11. The semiconductor device according to claim 10, wherein, The channel layer comprises a semiconductor material.

12. The semiconductor device according to claim 10, wherein, The metal-organic framework layer includes a two-dimensional conductive metal-organic framework with cavities.

13. The semiconductor device according to claim 12, in, The metal-organic framework layer comprises at least two conductive metal-organic frameworks stacked on the ferroelectric layer. Wherein, the cavities of the at least two conductive metal-organic frameworks are configured to overlap each other in the thickness direction of the metal-organic framework layer, and The metal particles are disposed within the interior space of the overlapping cavities.

14. A method for manufacturing a semiconductor device, the method comprising: Provide substrate; A ferroelectric layer is formed on the substrate; A two-dimensional conductive metal-organic framework with cavities is stacked on the ferroelectric layer to form a metal-organic framework layer, wherein the cavities of the conductive metal-organic framework are arranged to overlap each other in the thickness direction of the metal-organic framework layer. Metal particles are placed in overlapping cavities to form a charge trapping layer; A gate insulating layer is formed on the charge trapping layer; as well as A gate electrode layer is formed on the gate insulating layer.

15. The method according to claim 14, wherein, Forming the metal-organic framework layer includes forming the conductive metal-organic framework by using atomic layer deposition or chemical vapor deposition, which involves a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand.

16. The method of claim 14, wherein, The formation of the metal-organic framework layer includes: The conductive metal-organic framework is synthesized using a first precursor comprising a metal constituting a metal node and a second precursor comprising an organic ligand; and The synthesized conductive metal-organic framework is coated onto the ferroelectric layer.

17. The method of claim 14, wherein, Forming the charge trapping layer includes: Provide the metal-organic framework layer with a precursor comprising a metal; and The metal of the precursor is reduced so that the metal of the precursor grows into the metal particles in the overlapping cavities of the metal-organic framework layer.

18. The method according to claim 14, wherein, Forming the charge trapping layer includes: Depositing a thin metal film to fill the internal space of the overlapping cavity of the metal-organic framework layer on the ferroelectric layer; and Remove the portion of the metal film outside the cavity.

19. The method of claim 14, further comprising: A source region and a drain region are formed, and the source region and the drain region are disposed in different regions of the substrate.

20. The method of claim 14, further comprising: A channel layer is formed between the substrate and the ferroelectric layer; as well as A source electrode layer and a drain electrode layer are formed, wherein the source electrode layer and the drain electrode layer are respectively configured to contact the opposite ends of the channel layer on the substrate.

21. A semiconductor device, comprising: Substrate; A gate structure on the substrate and including a hole pattern, the gate structure including gate electrode layers and interlayer insulating layers alternately stacked on the substrate; A gate insulating layer is disposed on the sidewall surface of the gate structure exposed by the hole pattern; A charge trapping layer is disposed on the gate insulating layer; A ferroelectric layer is disposed on the charge trapping layer; as well as A channel layer is disposed on the ferroelectric layer. The charge trapping layer comprises a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

22. The semiconductor device according to claim 21, wherein, The channel layer extends in a direction substantially perpendicular to the surface of the substrate.

23. The semiconductor device according to claim 21, further comprising: The source line and bit line are electrically connected to the opposite ends of the channel layer, respectively.

24. The semiconductor device according to claim 21, wherein, The metal-organic framework layer includes a two-dimensional conductive metal-organic framework forming a cavity.

25. The semiconductor device according to claim 24, in, The metal-organic framework layer includes at least two conductive metal-organic frameworks stacked on the gate insulating layer. Wherein, the cavities of the at least two conductive metal-organic frameworks are configured to overlap each other in the thickness direction of the metal-organic framework layer, and The metal particles are disposed inside overlapping cavities.

26. The semiconductor device according to claim 24, wherein, The conductive metal-organic framework includes at least one selected from hexahydroxybenzophenanthrene, hexaiminobenzophenanthrene, hexathiobenzophenanthrene, hexahydrobenzene, hexaaminobenzene, and hexathiobenzene.

27. The semiconductor device according to claim 21, wherein, The metal particles include at least one selected from cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mn).

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