Non-volatile antiferroelectric memory for polymorphic storage and method of making the same

Abstract

The application relates to a non-volatile antiferromagnetic memory for multi-state storage and a preparation method thereof. The non-volatile antiferromagnetic memory for multi-state storage comprises, from bottom to top, a substrate, a bottom electrode, a first intermediate layer, a second intermediate layer and a top electrode; wherein one of the first intermediate layer and the second intermediate layer is an antiferromagnetic layer, and the other is a semiconductor layer. The application introduces a bidirectional change built-in electric field, so that the storage capacity of 2-bit (4 states) can be realized in a single memory cell.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memories, and in particular to a non-volatile antiferroelectric memory for polymorphic storage and its fabrication method. Background Technology

[0002] Non-volatile ferroelectric memories have attracted widespread attention due to their advantages such as high speed, low power consumption, and radiation resistance. The storage principle of ferroelectric memories is based on the bistable spontaneous polarization of ferroelectric materials, possessing a single hysteresis loop. When the ferroelectric material is in an upward (or downward) polarization state, the information of the corresponding ferroelectric memory cell is 1 (or 0). For example... Figure 1 As shown, ferroelectric capacitors have different polarities under different applied electric fields. In the absence of an electric field, +P r and -P r They represent two states, 0 and 1, respectively, and can be stored in a single storage unit with a 1-bit capacity.

[0003] However, with the explosive growth of data volume, memory products are increasingly trending towards expanding the storage capacity of individual memory cells to improve overall storage capacity, processing power, and reduce costs. Multilevel storage technology is a promising solution. Multilevel storage technology differs from 1-bit / cell, which stores two bits of information in a single cell. In multilevel technology, the smallest information storage unit can store multiple bits of data, forming a multilevel cell. For example, 2-bit / cell, where each cell can store four bits of information, corresponding to "00", "01", "10", and "11" in logical language. Ferroelectric materials have a single hysteresis loop and are intrinsically bistable, which greatly limits the improvement of their storage capacity. Antiferroelectric memories, on the other hand, have a double hysteresis loop and intrinsically possess multi-state storage capabilities, enabling four different stable states. A single memory cell can store multiple bits, making it a strong contender for future high-capacity memories. For antiferroelectric materials, the residual polarization charge density is zero after the applied electric field is removed, indicating that antiferroelectric materials are volatile and cannot be used for non-volatile storage. To use antiferroelectric materials in non-volatile memory, a built-in electric field can be introduced by breaking the symmetry of the metal / antiferroelectric layer / metal structure by using a pair of metal electrodes with different work functions or by inserting a dielectric layer between the electrodes and the antiferroelectric layer. This causes the hysteresis loop of the antiferroelectric material to drift along the voltage axis. However, the built-in electric field introduced by these two methods is unidirectional, and its direction does not change with the direction of the applied electric field. Therefore, its hysteresis loop can only drift left or right, and non-volatility can only be achieved in one of the sub-hysteresis loops. That is, this method can only enable antiferroelectric materials to achieve non-volatile storage in two states.

[0004] Therefore, this invention is proposed. Summary of the Invention

[0005] The main objective of this invention is to provide a non-volatile antiferroelectric memory for multi-state storage and its fabrication method, which introduces a bidirectional variable built-in electric field, thereby enabling 2-bit (4-state) storage capability within a single memory cell.

[0006] To achieve the above objectives, the present invention provides the following technical solutions.

[0007] A first aspect of the present invention provides a non-volatile antiferroelectric memory for polymorphic storage, comprising, from bottom to top:

[0008] Substrate,

[0009] Bottom electrode,

[0010] First intermediate layer,

[0011] Second intermediate layer,

[0012] Top electrode;

[0013] In this process, one of the first intermediate layer and the second intermediate layer is an antiferroelectric layer, and the other is a semiconductor layer.

[0014] This invention utilizes a composite stacked structure of semiconductor and antiferroelectric layers to replace independent antiferroelectric layers. The asymmetry of the stacked structure can be used to introduce a built-in electric field, and the direction of the built-in electric field can be modulated by the accumulation and depletion of the semiconductor layer. This allows a bidirectional built-in electric field to be achieved within a single stacked structure, enabling the double hysteresis loops to drift to the left or right, thereby achieving non-volatility of the two sub-hysteresis loops and realizing 2-bit storage capability within a single cell.

[0015] Based on the above, the dimensions and materials of each layer in the memory can be further improved to enhance overall performance, as listed below.

[0016] Furthermore, the thickness of the semiconductor layer is 1–10 nm.

[0017] Furthermore, the semiconductor layer employs at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.

[0018] Furthermore, the antiferroelectric layer adopts at least one of the following: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric materials.

[0019] Furthermore, the HfO2-based antiferroelectric material includes at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.

[0020] Furthermore, the bottom electrode and the top electrode are metal electrodes.

[0021] Furthermore, the first intermediate layer is an antiferroelectric layer, and the second intermediate layer is a semiconductor layer.

[0022] Furthermore, the first intermediate layer is a semiconductor layer, and the second intermediate layer is an antiferroelectric layer.

[0023] A second aspect of the present invention provides a method for fabricating the non-volatile antiferroelectric memory for polymorphic storage described above, comprising:

[0024] Provide substrate;

[0025] A bottom electrode, a first intermediate layer, a second intermediate layer, and a top electrode are formed sequentially from bottom to top on the substrate.

[0026] This method is compatible with existing memory technologies and does not involve any complex or demanding steps.

[0027] Preferably, the semiconductor layer is formed using a low-temperature deposition method.

[0028] Compared with the prior art, the present invention achieves the following technical effects:

[0029] (1) A technology is developed that can introduce a bidirectional variable built-in electric field, thereby enabling the antiferroelectric double hysteresis loop to move to the left and right along the voltage axis, thereby enabling two-state storage in the two sub-hysteresis loops, and thus enabling 2-bit (4-state) storage capability in a single storage cell.

[0030] (2) The preparation method is simple. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0032] Figure 1 The polarization intensity-electric field hysteresis loop of ferroelectric materials;

[0033] Figure 2 A schematic diagram of the structure of a non-volatile antiferroelectric memory with polymorphic storage provided by the present invention;

[0034] Figure 3A schematic diagram of another non-volatile antiferroelectric memory with polymorphic storage provided by the present invention;

[0035] Figure 4 A schematic diagram illustrating how the built-in electric field is modulated by the depletion of the semiconductor layer, thereby causing the hysteresis loop to drift to the right.

[0036] Figure 5 A schematic diagram illustrating how the built-in electric field is modulated by the accumulation of semiconductor layers, thereby causing the hysteresis loop to drift to the left;

[0037] Figure 6 For preparation Figure 1 A flowchart illustrating the structure shown;

[0038] Figure 7 For preparation Figure 2 The flowchart shown is a schematic diagram of the structure. Detailed Implementation

[0039] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0040] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0042] The built-in electric field of current antiferroelectric nonvolatile memory is unidirectional, and its direction does not change with the direction of the applied electric field. Therefore, its hysteresis loop can only drift to the left or right, and non-volatility can only be achieved in one of the sub-hysteresis loops.

[0043] This invention designs such as Figure 2 and 3The non-volatile memory shown features a composite stacked structure of semiconductor and antiferroelectric layers between the bottom and top electrodes. This structure not only enables non-volatile storage but also introduces an asymmetric built-in electric field. The direction of the built-in electric field can be modulated by the accumulation and depletion of the semiconductor layers, thereby achieving a bidirectional built-in electric field within a single stacked structure. This allows the double hysteresis loops to drift to the left or right, thus achieving non-volatility of the two sub-hysteresis loops and enabling 2-bit storage capability within a single cell.

[0044] In this invention, the order of the semiconductor layer and the antiferroelectric layer can be interchanged. For example, Figure 2 The memory shown comprises, from bottom to top, a substrate, a bottom electrode, an antiferroelectric layer, a semiconductor layer, and a top electrode. Or, as... Figure 3 The memory shown comprises, from bottom to top, a substrate, a bottom electrode, a semiconductor layer, an antiferroelectric layer, and a top electrode. Both types of memory can achieve 2-bit storage capability within a single cell, thus exhibiting polymorphic storage characteristics. The semiconductor layer is preferably ultra-thin, with a thickness ranging from 1 to 10 nm.

[0045] Figure 2 and 3 The working principle of the polymorphic non-volatile antiferroelectric memory shown is as follows: Figure 4 and 5 As shown, the built-in electric field is modulated by the accumulation or depletion of the semiconductor layer, thereby causing the hysteresis loop to drift to the left or right.

[0046] The substrate in the memory of this invention can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide, etc.

[0047] The bottom and top electrodes in the memory can be made of any suitable conductor or semiconductor material, preferably a metal electrode.

[0048] For the antiferroelectric layer in the memory, it can be made of at least one of the following materials: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric materials; the HfO2-based antiferroelectric materials include at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.

[0049] The semiconductor layer in the memory uses at least one of metal oxide semiconductors, ionic oxide semiconductors, and low-dimensional semiconductor materials. The metal oxide semiconductor includes at least one of ZnO and SnO; the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO; and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP. These semiconductors can all be formed through low-temperature deposition, reducing device defects.

[0050] The aforementioned non-volatile antiferroelectric memory with polymorphic storage can be obtained using a simple fabrication method. The steps involved in this method can be implemented using existing equipment and processes, making it easier to achieve industrial-scale production. Figure 6 The formation shown is as follows Figure 1 The structure shown includes the following steps:

[0051] Provide substrate;

[0052] A bottom electrode, an antiferroelectric layer, a semiconductor layer, and a top electrode are deposited sequentially from bottom to top on the surface of the substrate.

[0053] The deposition methods for the above layers include, but are not limited to, in-situ oxidation, PECVD, ALCVD, magnetron sputtering, low-temperature deposition, and arc ion plating. The deposition method should be selected according to the material type.

[0054] The channel layer is preferably formed using a low-temperature deposition method.

[0055] In addition, the formation of each material layer may involve multiple specific steps, such as thin film deposition, cleaning, patterning, etc., and may involve the deposition and removal of mask or sacrificial layers if necessary. The present invention does not impose any particular limitations on these aspects.

[0056] Or adopt such as Figure 7 The method shown forms as follows Figure 2 The structure shown includes the following steps:

[0057] Provide substrate;

[0058] A bottom electrode, a semiconductor layer, an antiferroelectric layer, and a top electrode are deposited sequentially from bottom to top on the surface of the substrate.

[0059] The deposition methods for the above layers include, but are not limited to, in-situ oxidation, PECVD, ALCVD, magnetron sputtering, low-temperature deposition, and arc ion plating. The deposition method should be selected according to the material type.

[0060] The channel layer is preferably formed using a low-temperature deposition method.

[0061] In addition, the formation of each material layer may involve multiple specific steps, such as thin film deposition, cleaning, patterning, etc., and may involve the deposition and removal of mask or sacrificial layers if necessary. The present invention does not impose any particular limitations on these aspects.

[0062] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A non-volatile antiferroelectric memory for polymorphic storage, characterized in that, Including from bottom to top: Substrate, Bottom electrode, First intermediate layer, Second intermediate layer, Top electrode; In this configuration, one of the first intermediate layer and the second intermediate layer is an antiferroelectric layer, and the other is a semiconductor layer. The thickness of the semiconductor layer is 1~10nm; By utilizing the asymmetry of the stacked structure to introduce a built-in electric field, the direction of which is modulated by the accumulation and depletion of the semiconductor layer, a bidirectional built-in electric field is achieved within a single stacked structure, causing the double hysteresis loop to drift to the left or right, thus realizing the non-volatility of the two sub-hysteresis loops.

2. The non-volatile antiferroelectric memory for polymorphic storage according to claim 1, characterized in that, The semiconductor layer is made of at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.

3. The non-volatile antiferroelectric memory for polymorphic storage according to claim 1, characterized in that, The antiferroelectric layer adopts at least one of the following: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric materials.

4. The non-volatile antiferroelectric memory for polymorphic storage according to claim 3, characterized in that, The HfO2-based antiferroelectric material includes at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.

5. The non-volatile antiferroelectric memory for polymorphic storage according to claim 1, characterized in that, The bottom electrode and the top electrode are metal electrodes.

6. The non-volatile antiferroelectric memory for polymorphic storage according to claim 1, characterized in that, The first intermediate layer is an antiferroelectric layer, and the second intermediate layer is a semiconductor layer.

7. The non-volatile antiferroelectric memory for polymorphic storage according to claim 1, characterized in that, The first intermediate layer is a semiconductor layer, and the second intermediate layer is an antiferroelectric layer.

8. The method for fabricating a non-volatile antiferroelectric memory for polymorphic storage according to any one of claims 1-7, characterized in that, include: Provide substrate; A bottom electrode, a first intermediate layer, a second intermediate layer, and a top electrode are formed sequentially from bottom to top on the substrate.

9. The preparation method according to claim 8, characterized in that, The semiconductor layer is formed using a low-temperature deposition method.

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