Semiconductor integrated circuit device and manufacturing method thereof

Abstract

This application discloses a semiconductor integrated circuit device and its manufacturing method. By controlling the number of etching operations and the depth of each etching operation during the formation of the sidewall layer, the sidewall layer, while ensuring coverage of the resistive switching layer, is optimized by ensuring that the top of the sidewall layer is lower than the top of the upper electrode and / or the bottom of the sidewall layer is higher than the bottom of the lower electrode. When the top of the sidewall layer is lower than the top of the upper electrode, a deposition space that is wider at the top and narrower at the bottom is formed, reducing the voids formed during dielectric layer deposition. When the bottom of the sidewall layer is higher than the bottom of the lower electrode, the lower electrode can form a structure that is narrower at the top and wider at the bottom, better supporting the resistive switching layer and the upper electrode, making the overall device structure more stable. This makes the semiconductor integrated circuit device easier to meet miniaturization requirements and results in better quality.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor integrated circuit device and a method for manufacturing the same. Background Technology

[0002] Resistive variable memory (RVRAM) typically consists of multiple RVRAM cells, which are usually arranged in a sandwich structure with a bottom electrode, a resistive switching layer, and a top electrode stacked layer by layer from bottom to top.

[0003] To further protect the resistive switching layer, a sidewall layer is often added to its outer side. For simplified manufacturing, this sidewall layer completely covers the entire component, including the lower electrode, resistive switching layer, and upper electrode, from top to bottom, rather than just covering the outer side of the resistive switching layer. However, components with this structure (including the lower electrode, resistive switching layer, and upper electrode) have poor stability. As the size of resistive switching memory cells continues to shrink, these components are prone to collapse; and during dielectric layer deposition, voids are easily created.

[0004] All of the above problems can cause defects in the function and quality of semiconductor integrated circuit devices. Summary of the Invention

[0005] In response to the aforementioned technical problems, the applicant has creatively provided a semiconductor integrated circuit device and a method for manufacturing the same.

[0006] According to a first aspect of the embodiments of this application, a semiconductor integrated circuit device is provided, the semiconductor integrated circuit device including at least one resistive switching memory cell, the resistive switching memory cell including an upper electrode, a resistive switching layer and a lower electrode, the upper electrode and the lower electrode being located on the upper and lower sides of the resistive switching layer respectively, the resistive switching memory cell being provided with a first sidewall layer, the first sidewall layer covering the outside of the resistive switching layer, the top of the first sidewall layer being lower than the top of the upper electrode and / or the bottom of the first sidewall layer being higher than the bottom of the lower electrode.

[0007] According to one embodiment of this application, the resistive switching memory cell is further provided with at least one second sidewall layer, which covers the outside of the upper electrode.

[0008] According to one embodiment of this application, the second sidewall layer is sleeved with the first sidewall layer, and the second sidewall layer is located inside the first sidewall layer.

[0009] According to one embodiment of this application, the material used in the sidewall layer includes aluminum oxide (Al2O3).

[0010] According to a second aspect of the present application, a method for manufacturing a semiconductor integrated circuit device is provided. The method includes: forming a lower electrode on a substrate; forming a resistive switching layer; forming an upper electrode; and forming a first sidewall layer such that the first sidewall layer covers the outside of the resistive switching layer, the top of the first sidewall layer is lower than the top of the upper electrode and / or the bottom of the sidewall layer is higher than the bottom of the lower electrode.

[0011] According to one embodiment of this application, forming a first sidewall layer includes: etching to a designated position of the lower electrode, the designated position being higher than the bottom of the lower electrode; depositing a sidewall layer material and etching the sidewall layer material to form the first sidewall layer.

[0012] According to one embodiment of this application, before forming the first sidewall layer, the manufacturing method further includes: forming at least one second sidewall layer, the second sidewall layer covering the outer side of the upper electrode.

[0013] According to one embodiment of this application, forming at least one second sidewall layer includes: performing at least one etching to a designated location of the upper electrode; after each etching to the designated location of the upper electrode, depositing a sidewall layer material and etching the sidewall layer material to form one of the at least one second sidewall layers.

[0014] According to one embodiment of this application, forming a first sidewall layer includes: etching down to the bottom of the lower electrode; depositing a sidewall layer material and etching the sidewall layer material to form the first sidewall layer.

[0015] According to one embodiment of this application, etching the sidewall layer material includes: performing anisotropic etching on the sidewall layer material.

[0016] This application discloses a semiconductor integrated circuit device and its manufacturing method. The semiconductor integrated circuit device controls the number of etchings and the depth of each etching during the etching process to form a sidewall layer, so that the sidewall layer, while ensuring that it covers the resistive switching layer, makes the top of the sidewall layer lower than the top of the upper electrode and / or the bottom of the sidewall layer higher than the bottom of the lower electrode, thereby forming a more optimized structure.

[0017] When the top of the sidewall layer is lower than the top of the top electrode, a dielectric layer deposition space that is wider at the top and narrower at the bottom can be formed, reducing the potential for voids during dielectric layer deposition.

[0018] When the bottom of the sidewall layer is higher than the bottom of the lower electrode, the lower electrode can form a structure that is narrow at the top and wide at the bottom, which can better support the resistive switching layer and the upper electrode, making the structure of the entire device more stable.

[0019] When the top of the sidewall layer is lower than the top of the upper electrode and the bottom of the sidewall layer is higher than the bottom of the lower electrode, all the above-mentioned benefits can be achieved. This makes it easier for semiconductor integrated circuit devices to meet miniaturization requirements and further reduces functional or quality defects.

[0020] It should be understood that the implementation of the embodiments of this application does not need to achieve all the above-mentioned beneficial effects, but a specific technical solution can achieve a specific technical effect, and other implementation methods of the embodiments of this application can also achieve beneficial effects not mentioned above. Attached Figure Description

[0021] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0022] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0023] Figure 1 This diagram shows a cross-sectional view of the structure of a resistive variable memory in the prior art;

[0024] Figure 2 This diagram illustrates the principle that voids may be generated during the deposition of dielectric layers in the prior art.

[0025] Figure 3 A schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device of this application is shown;

[0026] Figure 4 A schematic cross-sectional view of another embodiment of the semiconductor integrated circuit device of this application is shown;

[0027] Figure 5 A schematic cross-sectional view of another embodiment of the semiconductor integrated circuit device of this application is shown;

[0028] Figure 6 A schematic flowchart of the manufacturing method of the semiconductor integrated circuit device of this application is shown;

[0029] Figure 7 This application shows Figure 3 A schematic diagram of the manufacturing process of the embodiment shown;

[0030] Figure 8 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0031] Figure 9 This application shows Figure 3A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0032] Figure 10 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0033] Figure 11 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0034] Figure 12 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0035] Figure 13 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0036] Figure 14 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0037] Figure 15 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0038] Figure 16 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0039] Figure 17 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown;

[0040] Figure 18 This application shows Figure 3 A cross-sectional view of the structure at a certain stage of the manufacturing process of the embodiment shown. Detailed Implementation

[0041] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] In order to describe the three-dimensional structure of semiconductor integrated circuit devices from multiple perspectives, this application refers to the structural schematic diagram obtained by vertically cutting the semiconductor integrated circuit device as a structural cross-sectional schematic diagram; and the structural schematic diagram obtained by horizontally cutting the semiconductor integrated circuit device as a structural section schematic diagram.

[0045] Currently, the most common resistive switching memory cells, such as Figure 1 As shown, a sandwich structure is often used, which is stacked layer by layer from bottom to top, including: a substrate 101, a via 102 connected to the first metal layer of the substrate, a lower electrode 103, a resistive switching layer 104, an oxygen storage layer 105, an upper electrode 106, and a metal layer 107. In addition, in order to protect the resistive switching layer 104 and enable it to generate conductive filaments more stably, a sidewall layer 108 is also covered on the outside of the resistive switching layer to avoid interference from the dielectric layer 109 to the resistive switching layer 104.

[0046] like Figure 1 As shown, for the purpose of simplifying the manufacturing process, the sidewall layer 108 will fully cover the element formed by the lower electrode 103, resistive switching layer 104, oxygen storage layer 105 and upper electrode 106 from top to bottom. That is, the top of the sidewall layer 108 is flush with the top of the upper electrode 106, and the bottom of the sidewall layer 108 is flush with the bottom of the lower electrode 103.

[0047] However, the components of the above structure (including the lower electrode 103, resistive switching layer 104, oxygen storage layer 105, and upper electrode 106) are columnar structures without a base, which have poor stability. As the size of the resistive switching memory cell continues to shrink, especially as the area shrinks, the component will become thinner and will easily collapse.

[0048] Furthermore, the above structure can lead to some functional or quality defects in the manufacturing process of resistive variable memory cells.

[0049] For example, since the sidewall layer 108 is almost perpendicular to the substrate at a 90-degree angle, this necessitates the application of materials such as plastics to the substrate during the formation of the dielectric layer 109. Figure 2 A dielectric layer 109 is deposited in the vertical trench 201 shown on the left (a). Because overhangs may occur initially during the deposition of the dielectric layer 109, the upper dielectric layer may seal the bottom layer before the bottom layer is completely filled, potentially leading to… Figure 2 Hole 202 shown on the left (b).

[0050] For example, when forming the sidewall layer 108, etching needs to start from the upper electrode 106 and continue until the lower electrode 103. Dry etching is the most commonly used etching process for forming sidewall layers. Dry etching refers to an etching technique that uses glow discharge to generate plasma containing charged particles such as particles and electrons, as well as highly chemically active neutral atoms, molecules, and free radicals, to transfer patterns.

[0051] During the process of forming the sidewall layer using dry etching, the area of ​​the exposed metal portion on the outside of the upper electrode continuously increases. The exposed metal portion absorbs charged particles in the plasma, which leads to the upper electrode receiving more and more charged particles. When it receives enough charged particles, it will cause an excessive voltage difference between the upper and lower electrodes, forming a strong current that breaks down the resistive switching layer and causes plasma damage.

[0052] Therefore, when etching starts from the upper electrode 106 and continues to the lower electrode 103, the exposed metal part on the outside of the upper electrode 106 will continuously absorb charged particles in the plasma, resulting in an excessive voltage difference between the upper electrode 106 and the lower electrode 103. This will cause a strong current to break down the resistive switching layer 104, resulting in plasma damage.

[0053] Therefore, the inventors of this application creatively conceived that the main function of the sidewall layer 108 is to protect the resistive switching layer 104. If the etching is performed in several stages during the manufacturing process and the depth of each etching is controlled, it is very likely that the top of the sidewall layer will be lower than the top of the upper electrode and / or the bottom of the sidewall layer will be higher than the bottom of the lower electrode, thereby solving the above-mentioned problem.

[0054] Based on the above inventive concept, this application provides a semiconductor integrated circuit device and its manufacturing method.

[0055] Figure 3 A schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device of this application is shown. Figure 3The semiconductor integrated circuit device includes at least one resistive switching memory cell, wherein each resistive switching memory cell includes an upper electrode 306, a resistive switching layer 304 and a lower electrode 303, the upper electrode 306 and the lower electrode 303 are respectively located on the upper and lower sides of the resistive switching layer 304, the resistive switching memory cell is provided with a first sidewall layer 308, the first sidewall layer 308 covers the outside of the resistive switching layer 304, the top of the first sidewall layer 308 is lower than the top of the upper electrode 306, and the bottom of the first sidewall layer 308 is higher than the bottom of the lower electrode 303.

[0056] Since the top of the first sidewall layer 308 is lower than the top of the upper electrode 306, a deposition space that is wider at the top and narrower at the bottom can be formed, which can reduce the pores that may be formed when depositing the dielectric layer 310.

[0057] Moreover, since the bottom of the first sidewall layer 308 is higher than the bottom of the lower electrode 303, the lower electrode 303 can form a more stable structure that is narrower at the top and wider at the bottom, similar to a step. This can better support the resistive switching layer 304 and the upper electrode 306, making the structure of the entire device (including the lower electrode 303, the resistive switching layer 304 and the upper electrode 306) more stable and better meet the miniaturization requirements.

[0058] Thus, adopt Figure 3 The structure used in the semiconductor integrated circuit device embodiments shown in this application makes it easier for semiconductor integrated circuit devices to meet miniaturization requirements and further reduce functional or quality defects.

[0059] In addition, Figure 3 In the semiconductor integrated circuit device embodiment shown in this application, in addition to the first sidewall layer 308, a second sidewall layer 309 is also provided. The second sidewall layer 309 covers the outer side of the upper electrode 306, is located inside the first sidewall layer 308, and is sleeved with the first sidewall layer 308.

[0060] In this way, on the one hand, the metal part on the outside of the upper electrode 306 can be prevented from being exposed to the plasma used for subsequent etching after the first etching, thus avoiding plasma damage that may occur during subsequent etching; on the other hand, the second sidewall layer 309 is located inside the first sidewall layer 308 and is sleeved with the first sidewall layer 308, which can also form a more stable sleeve structure with the first sidewall layer 308, making the structure of the entire component (including the lower electrode 303, resistive switching layer 304 and upper electrode 306) more stable and better meeting the miniaturization requirements.

[0061] The second sidewall layer 309 is a gain structure. In other embodiments of the semiconductor integrated circuit device of this application, the second sidewall layer 309 may not be provided to simplify the manufacturing process.

[0062] Except for the second sidewall layer 309, in Figure 3The semiconductor integrated circuit device embodiment shown in this application also includes a common structure for the operation of resistive switching memory cells, including: a substrate 301, a via 302 for connecting the resistive switching memory cells and the substrate 301, an oxygen storage layer 305 for attracting oxygen to generate more oxygen vacancies, a metal layer 307 connected to the upper electrode 306, and a dielectric layer 310 for filling the gaps between resistive switching cells and blocking the electrical connection between resistive switching cells. The oxygen storage layer 305 is also a gain structure, and implementers may or may not include it depending on actual needs.

[0063] It should be noted that in specific application scenarios, the above problems will not occur simultaneously. For example, in applications where miniaturization requirements are not high, the risk of collapse is relatively small; when device height is limited and trenches are wide, the probability of voids appearing in the deposited dielectric layer is correspondingly reduced; and when the antenna ratio is appropriate, plasma damage can also be avoided. In the above situations, it is possible to... Figure 3 The structure of the semiconductor integrated device shown in this application has been modified to further simplify the manufacturing process.

[0064] Figure 4 Another embodiment of the semiconductor integrated device of this application is shown. This semiconductor integrated circuit device is mainly used in scenarios where miniaturization requirements are not high and the risk of collapse is low.

[0065] like Figure 4 As shown, the semiconductor integrated circuit device includes at least one resistive switching memory cell, wherein each resistive switching memory cell includes an upper electrode 406, a resistive switching layer 404 and a lower electrode 403. The upper electrode 406 and the lower electrode 403 are located on the upper and lower sides of the resistive switching layer 404, respectively. The resistive switching memory cell is provided with a first sidewall layer 408, which covers the outside of the resistive switching layer 404. The top of the first sidewall layer 408 is lower than the top of the upper electrode 406, but the bottom of the first sidewall layer 408 is flush with the bottom of the lower electrode 403.

[0066] In addition, Figure 4 The illustration shows an embodiment of the semiconductor integrated device of this application, which also includes a second sidewall layer 409, a substrate 401, a via 402 for connecting the resistive switching memory cell and the substrate 401, an oxygen storage layer 405 for attracting oxygen to generate more oxygen vacancies, a metal layer 407 connected to the upper electrode 406, and a dielectric layer 410 for filling the gaps between the resistive switching cells and blocking the electrical connection between the resistive switching cells.

[0067] Since the top of the first sidewall layer 408 is lower than the top of the upper electrode 406, a deposition space that is wider at the top and narrower at the bottom can be formed, which can reduce the holes that may be formed when depositing the dielectric layer 410. Similarly, by etching multiple times, the time for the upper electrode 406 to expose the metal area during each etching can be shortened, thereby reducing the number of absorbed electric particles and thus avoiding or reducing plasma loss to the resistive switching layer 404.

[0068] because Figure 4 The semiconductor integrated circuit device embodiments shown in this application are used in scenarios where miniaturization requirements are not high and the risk of collapse is low. In such cases, the step of etching the lower electrode 403 multiple times can be omitted, thereby simplifying the manufacturing process.

[0069] Figure 5 Another embodiment of the semiconductor integrated device of this application is shown. This semiconductor integrated circuit device is mainly used in scenarios where the antenna ratio is acceptable, there is no risk of plasma damage, but there is a high requirement for miniaturization and there may be a risk of collapse.

[0070] like Figure 5 As shown, the semiconductor integrated circuit device includes at least one resistive switching memory cell, wherein each resistive switching memory cell includes an upper electrode 506, a resistive switching layer 504 and a lower electrode 503. The upper electrode 506 and the lower electrode 503 are located on the upper and lower sides of the resistive switching layer 504, respectively. The resistive switching memory cell is provided with a first sidewall layer 508, which covers the outside of the resistive switching layer 504. The bottom of the first sidewall layer 508 is higher than the bottom of the lower electrode 503, but the top of the first sidewall layer 508 is flush with the top of the upper electrode 506.

[0071] In addition, Figure 5 The semiconductor integrated device embodiment shown in this application also includes common structures such as a substrate 501, a via 502 for connecting the resistive switching memory cell and the substrate 501, an oxygen storage layer 505 for attracting oxygen to generate more oxygen vacancies, a metal layer 507 connected to the upper electrode 506, and a dielectric layer 510 for filling the gaps between the resistive switching cells and blocking the electrical connection between the resistive switching cells.

[0072] Since the bottom of the first sidewall layer 508 is higher than the bottom of the lower electrode 503, the lower electrode 503 can form a more stable structure that is narrower at the top and wider at the bottom, similar to a step. This can better support the resistive switching layer 504 and the upper electrode 506, making the structure of the entire device (including the lower electrode 503, the resistive switching layer 504 and the upper electrode 506) more stable and better meet the miniaturization requirements.

[0073] And due to Figure 5The semiconductor integrated device shown in this application is mainly used in scenarios where the antenna ratio is acceptable and there is no risk of plasma damage. Therefore, the step of etching the upper electrode 506 multiple times can be omitted, and there is no need to form a second sidewall layer, which makes the manufacturing process simpler.

[0074] Furthermore, this application also provides a method for manufacturing a semiconductor integrated circuit device, such as... Figure 6 As shown, the manufacturing method includes:

[0075] Operate S610 to form the lower electrode on the substrate;

[0076] The substrate refers to the electronic components on which the semiconductor integrated circuit device embodiments of this application are based, and typically includes a base plate, a dielectric material layer above the base plate, through holes in the dielectric material layer with deposited metal material, and metal layers and circuits connected to the through holes.

[0077] The lower electrode is formed on the substrate by depositing electrode material. Any suitable deposition process can be used to deposit the electrode material, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0078] Operate S620 to form a resistive switching layer;

[0079] The formation of the resistive switching layer can be achieved by depositing resistive switching layer materials. Any suitable deposition process can be used to deposit the resistive switching layer materials, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0080] Operate S630 to form the upper electrode;

[0081] The upper electrode is formed by depositing electrode material. Any suitable deposition process can be used, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0082] In operation S640, a first sidewall layer is formed such that the first sidewall layer covers the outside of the resistive switching layer, and the top of the first sidewall layer is lower than the top of the upper electrode and / or the bottom of the sidewall layer is higher than the bottom of the lower electrode.

[0083] To ensure that the first sidewall layer covers the outside of the resistive switching layer, with the top of the first sidewall layer lower than the top of the upper electrode and / or the bottom of the sidewall layer higher than the bottom of the lower electrode, this can be achieved through multiple etching processes. Specifically, after each etching to a specified depth, etching is stopped, material is deposited, and then the next etching process is performed, etching to an even deeper specified depth.

[0084] In this way, by controlling the number and depth of etching, a better structure can be obtained in which the top of the top electrode is lower than the top of the upper electrode and / or the bottom of the sidewall layer is higher than the bottom of the lower electrode. This reduces the functional or quality defects that may be caused to semiconductor integrated circuit devices during the manufacturing process, resulting in better quality and longer lifespan of semiconductor integrated circuit devices.

[0085] The above etching is mainly achieved through dry etching process.

[0086] It should be noted that, Figure 6 The steps shown above are only the main steps in manufacturing the semiconductor integrated circuit device according to the embodiments of this application, and not all steps. In the process of manufacturing the semiconductor integrated circuit device, other steps may also be included, depending on the product design of the semiconductor integrated circuit device, such as grinding and removing top coatings, depositing an oxide storage layer, depositing a dielectric layer, wiring, and soldering.

[0087] Figure 7 Manufacturing process is shown Figure 3 The manufacturing method used in the semiconductor integrated circuit device embodiments shown in this application, such as Figure 7 As shown, the manufacturing method mainly includes:

[0088] Step S7010, in Figure 8 Above the substrate 301 and via 302, electrode material 303, resistive switching layer material 304, oxygen storage layer material 305, upper electrode material 306, and hard mask layer material 311 are sequentially deposited to obtain... Figure 9 The structure shown;

[0089] The through-hole 302 is connected to the first metal layer on the substrate 301 and can be used as the lower terminal of the resistive switching memory cell. The terminal refers to the component used to connect external wires.

[0090] Step S7020: Coat photoresist 312 and expose to obtain... Figure 10 The structure shown;

[0091] Step S7030: Etch hard mask 311, remove photoresist 312, and obtain... Figure 11 The structure shown;

[0092] Both etching the hard mask 311 and removing the photoresist 312 can be done using a dry etching process.

[0093] It should be noted that in this step, etching will stop only when the hard mask is etched to the bottom. It will not continue etching to the upper electrode 306, nor will it be etched to the bottom of the lower electrode 303 in one go.

[0094] This avoids exposing the metal on the side of the upper electrode to the plasma, reducing the absorption of charged particles.

[0095] Step S7040: Etch the upper electrode 306 to a specified location with a specific depth to obtain... Figure 12 The structure shown;

[0096] As the etching depth increases, the area of ​​the metal portion of the upper electrode 306 exposed to the plasma becomes larger, resulting in a higher antenna ratio. When the antenna ratio reaches a certain level, a strong current will penetrate the resistive switching layer, causing plasma damage. The antenna ratio refers to the ratio of the area of ​​the upper electrode in contact with the plasma (including the side surface without the upper sidewall) to the area of ​​the resistive switching layer.

[0097] Therefore, a specific depth can be determined by the antenna ratio, which is sufficient to keep the antenna ratio within a safe range.

[0098] To reduce plasma damage, multiple depositions and etchings can be performed until the etching depth is below the bottom of the upper electrode 306.

[0099] Step 7050: Deposit the second sidewall layer 309 and perform anisotropic etching to obtain... Figure 13 The structure shown;

[0100] The second sidewall layer 309 formed in this step can protect the upper electrode 306. During the subsequent etching process, the metal part outside the upper electrode 306 will no longer be exposed to the plasma, and plasma damage will no longer occur.

[0101] Instead of isotropic etching, a longer etching time can create better openings and reduce the formation of pores during dielectric layer deposition.

[0102] Step S7060: Etch again, etching to a specific depth and designated position in the lower electrode 303 (the designated position is higher than the bottom of the lower electrode), to obtain... Figure 14 The structure shown;

[0103] Specifically, the specific depth here needs to exceed the resistive switching layer, and the optimal value of the specific depth needs to be greater than the thickness of the sidewall layer, so that the protection effect of the sidewall layer can be better; while the optimal value of the specific depth can be as small as possible while satisfying the protection effect of the sidewall layer, so as to prevent the components (including the lower electrode 303, resistive switching layer 304 and upper electrode 306) from collapsing.

[0104] Step S7070: Deposit the first sidewall layer 308, and perform anisotropic etching to obtain... Figure 15 The structure shown;

[0105] During the deposition and etching of the first sidewall layer 308, the deposition and etching amounts can be controlled so that the top of the first sidewall layer 308 is lower than the top of the second sidewall layer 309 outside the first electrode. This allows for the formation of a layer between two adjacent resistive switching memory cells, such as... Figure 16As shown, the space of the deposited dielectric layer is wider at the top and narrower at the bottom (W1>W2), thereby reducing the porosity that may be generated during the deposition of the dielectric layer.

[0106] Step S7080: Etch the lower electrode 303 to distinguish the independent resistive switching memory cells, thus obtaining... Figure 17 The structure shown;

[0107] Step S7090: Deposit dielectric layer 310, remove hard mask layer 311, and obtain... Figure 18 The structure shown;

[0108] Step S7100: Prepare metal layer 307 and perform wiring to obtain... Figure 4 The semiconductor integrated circuit device embodiment shown in this application.

[0109] If the semiconductor integrated circuit device is mainly used in scenarios where miniaturization requirements are not high and the risk of collapse is low, in step S7060 above, etching can be performed to the bottom of the lower electrode and the first sidewall layer can be deposited. Then, step 7080 can be skipped, and step 7090 can be continued to obtain the desired result. Figure 4 The semiconductor integrated circuit device embodiment shown in this application.

[0110] If the semiconductor integrated circuit device is mainly used in scenarios where the antenna ratio is acceptable and there is no risk of plasma damage, but the miniaturization requirements are high and there may be a risk of collapse, then in step 7030 above, the etching can be performed in one go to the bottom of the lower electrode, and steps S7040-S7060 can be skipped, and steps S7070-S7100 can be continued to obtain the desired result. Figure 5 The semiconductor integrated circuit device embodiment shown in this application.

[0111] It should be noted that, in the above embodiments of the semiconductor integrated circuit device of this application, including the process of manufacturing each embodiment using the semiconductor integrated circuit device manufacturing method of this application, the materials used for each component are not limited.

[0112] For example, the first electrode and the second electrode may use any applicable one or more electrode materials, including but not limited to: aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) and tungsten nitride (WN), etc.

[0113] The resistive switching layer can be any suitable resistive switching layer material, including but not limited to: aluminum oxide (Al₂O₃). x O y ), copper oxide (Cu) x O y ), hafnium oxide (Hf) x O yTransition metal oxides (TMOs) and other transition metal oxides.

[0114] The sidewall layer can be any suitable one or more dielectric materials, including but not limited to: aluminum oxide (Al2O3), etc.

[0115] The oxygen storage layer can use any suitable oxygen storage layer material or one or more, including but not limited to: titanium (Ti) and tantalum (Ta).

[0116] The hard mask layer can use any suitable one or more hard mask layer materials, including but not limited to: SiN or other materials that have a selectivity ratio to the oxygen storage layer. Here, a material with a selectivity ratio to the oxygen storage layer refers to a material that is different from the material used for the oxygen storage layer, resulting in a different ratio between the etching rates of the hard mask and the oxygen storage layer.

[0117] The dielectric material can be any applicable one or more dielectric materials, including but not limited to: ultra-low K (ULK) materials or other dielectric materials, such as nitride, oxide, etc.

[0118] The metal layer may be made of any suitable one or more metallic materials, including but not limited to: aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and tungsten nitride (WN).

[0119] Furthermore, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another device, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0121] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor integrated circuit device, the semiconductor integrated circuit device comprising at least one resistive switching memory cell, the resistive switching memory cell comprising an upper electrode, a resistive switching layer, and a lower electrode, the upper electrode and the lower electrode being respectively located on the upper and lower sides of the resistive switching layer, characterized in that, The resistive switching memory cell is provided with a first sidewall layer, which covers the outside of the resistive switching layer. The top of the first sidewall layer is lower than the top of the upper electrode and / or the bottom of the first sidewall layer is higher than the bottom of the lower electrode. When the top of the first sidewall layer is lower than the top of the upper electrode, a deposition space that is wider at the top and narrower at the bottom is formed. When the bottom of the first sidewall layer is higher than the bottom of the lower electrode, the lower electrode forms a structure that is narrower at the top and wider at the bottom. The resistive switching memory cell is further provided with at least one second sidewall layer, which covers the outside of the upper electrode.

2. The semiconductor integrated circuit device according to claim 1, characterized in that, The second sidewall layer is sleeved with the first sidewall layer, and the second sidewall layer is located inside the first sidewall layer.

3. The semiconductor integrated circuit device according to any one of claims 1-2, characterized in that, The material used in the sidewall layer includes aluminum oxide (Al2O3).

4. A method for manufacturing a semiconductor integrated circuit device, characterized in that, The method includes: A lower electrode is formed on the substrate; Forming a resistive switching layer; Form the upper electrode; At least one second sidewall layer is formed, the second sidewall layer covering the outside of the upper electrode; A first sidewall layer is formed such that the first sidewall layer covers the outside of the resistive switching layer, and the top of the first sidewall layer is lower than the top of the upper electrode and / or the bottom of the sidewall layer is higher than the bottom of the lower electrode; wherein, when the top of the first sidewall layer is lower than the top of the upper electrode, a deposition space that is wider at the top and narrower at the bottom is formed; when the bottom of the first sidewall layer is higher than the bottom of the lower electrode, the lower electrode forms a structure that is narrower at the top and wider at the bottom.

5. The manufacturing method according to claim 4, characterized in that, The formation of at least one second sidewall layer includes: The upper electrode is etched at least once, until the specified position of the upper electrode is reached; After each etching to a designated location on the upper electrode, a sidewall layer material is deposited and etched to form the at least one second sidewall layer.

6. The manufacturing method according to claim 5, characterized in that, The formation of the first sidewall layer includes: The resistive switching layer and the lower electrode are etched to a designated position on the lower electrode, the designated position being higher than the bottom of the lower electrode; A sidewall layer material is deposited and etched to form a first sidewall layer.

7. The manufacturing method according to claim 5, characterized in that, The formation of the first sidewall layer includes: The resistive switching layer and the lower electrode are etched down to the bottom of the lower electrode. A sidewall layer material is deposited and etched to form a first sidewall layer.

8. The manufacturing method according to any one of claims 5, 6, and 7, characterized in that, The etching of the sidewall layer material includes: The sidewall layer material is etched anisotropically.

Images