Thin film transistor substrate and display device including the same

Abstract

A thin film transistor substrate and a display device including the same are provided. The thin film transistor substrate includes a first thin film transistor and a second thin film transistor on a base substrate, wherein the first thin film transistor includes a first active layer on the base substrate, and a first gate separated from the first active layer, wherein the second thin film transistor includes a second active layer on the base substrate, a second gate separated from the second active layer, and an auxiliary gate between the second active layer and the second gate, wherein the first active layer and the second active layer are formed in one body and connected to each other, the auxiliary gate is formed in one body with the first gate and separated from the second active layer and the second gate, and the second gate overlaps at least a portion of the auxiliary gate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0117990, filed September 3, 2021, and Korean Patent Application No. 10-2021-0194208, filed December 31, 2021, which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin-film transistor substrate and a display device including the thin-film transistor substrate. Background Technology

[0004] With the development of multimedia, display devices have become increasingly important, and flat panel display devices such as liquid crystal displays, plasma displays, and organic light-emitting diode displays have been put into commercial use.

[0005] Thin-film transistors (TFTs) with various functions are incorporated into flat panel display devices. For example, organic light-emitting display devices include driving transistors for driving pixels and switching transistors for controlling the driving transistors. To improve display quality and effectively control pixel emission, various TFTs, such as transistors for controlling emission and transistors for sensing, can be incorporated into the display device.

[0006] Recently, in order to achieve high quality and high resolution in display devices, thin-film transistors (TFTs) have been integrated into display devices at high density. However, due to the large number of TFTs placed in a limited area, there may be a problem of insufficient capacitor area. Therefore, when a large number of TFTs are placed in a display device, it is necessary to efficiently arrange the TFTs and the lines connecting them. Summary of the Invention

[0007] The present invention was made in view of the above problems. One object of the present invention is to provide a thin-film transistor substrate in which a large number of thin-film transistors and lines connected to the thin-film transistors can be efficiently disposed.

[0008] Another object of the present invention is to provide a thin-film transistor substrate that allows for efficient implementation of the thin-film transistor function even when the signal line overlaps with the gate of the thin-film transistor.

[0009] Another object of the present invention is to provide a display device comprising a thin-film transistor substrate as described above.

[0010] Another object of the present invention is to provide a display device that can actively control the driving of the driving transistor even when the light emission control line used for light emission control overlaps with the gate of the driving transistor.

[0011] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0012] According to one aspect of the present invention, the above and other objectives can be achieved by providing a thin-film transistor substrate comprising: a first thin-film transistor and a second thin-film transistor on a base substrate, wherein the first thin-film transistor comprises: a first active layer on the base substrate; and a first gate spaced apart from the first active layer, wherein the second thin-film transistor comprises: a second active layer on the base substrate; a second gate spaced apart from the second active layer; and an auxiliary gate between the second active layer and the second gate, wherein the first active layer and the second active layer are integrally formed and connected to each other, the auxiliary gate is integrally formed with the first gate and spaced apart from the second active layer and the second gate, and at least a portion of the second gate overlaps with the auxiliary gate.

[0013] The same voltage applied to the first gate can be applied to the auxiliary gate.

[0014] The first thin-film transistor can be configured to turn on when the second thin-film transistor is turned on.

[0015] When a second gate voltage is applied to the second gate, a first gate voltage can be applied to the first gate.

[0016] The second active layer may include: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein a portion of the channel portion may overlap with the auxiliary gate, and another portion of the channel portion may not overlap with the auxiliary gate.

[0017] The other portion of the channel that does not overlap with the auxiliary gate may overlap with the second gate.

[0018] The portion of the channel facing the first connection portion may overlap with the auxiliary gate, but may not overlap with the second gate.

[0019] The portion of the channel facing the second connection portion may overlap with the auxiliary gate, or may not overlap with the second gate.

[0020] The first active layer and the second active layer may comprise at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, ZnON (Zn oxynitride) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, and GZTO (GaZnSnO) based oxide semiconductor material.

[0021] Each of the first active layer and the second active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0022] The thin-film transistor may further include: a first light-shielding layer on the base substrate; and a second light-shielding layer on the first light-shielding layer, wherein the first light-shielding layer and the second light-shielding layer are separated from each other and overlap each other, one of the first light-shielding layer and the second light-shielding layer is connected to the second active layer, and the other of the first light-shielding layer and the second light-shielding layer is connected to the second gate.

[0023] The first light-shielding layer and the second light-shielding layer can form a capacitor.

[0024] According to another aspect of the invention, the above and other objectives can be achieved by providing a display device including the aforementioned thin-film transistors.

[0025] The first thin-film transistor can be a light-emitting control transistor, and the second thin-film transistor can be a driving transistor.

[0026] A light emission control signal can be applied to the first gate and the auxiliary gate.

[0027] The first gate and the auxiliary gate can be corresponding portions of the light-emitting control line.

[0028] A storage capacitor can be formed by overlapping the first light-shielding layer and the second light-shielding layer.

[0029] The display device may further include a driving transistor, a light-emitting control transistor, and a switching transistor, wherein the active layer of the driving transistor and the active layer of the light-emitting control transistor may be formed integrally, and the active layers of the driving transistor and the light-emitting control transistor may be distinguishable from the active layer of the switching transistor.

[0030] The display device may further include a sensing transistor, wherein the active layer of the sensing transistor may be integrally formed with the active layer of the driving transistor and the active layer of the light-emitting control transistor, and the active layer of the sensing transistor may be distinguishable from the active layer of the switching transistor. Attached Figure Description

[0031] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0032] Figure 1A This is a plan view illustrating a thin-film transistor substrate according to an embodiment of the present invention;

[0033] Figure 1B It is along Figure 1A A sectional view taken by line I-I';

[0034] Figure 1C This is a partially enlarged view illustrating the channel portion, second gate, and auxiliary gate of the second active layer;

[0035] Figure 2 This is a cross-sectional view illustrating a thin-film transistor substrate according to another embodiment of the present invention;

[0036] Figure 3A This is a plan view illustrating a thin-film transistor substrate according to another embodiment of the present invention;

[0037] Figure 3B It is along Figure 3A A sectional view taken from line II-II';

[0038] Figure 4 This is a cross-sectional view illustrating a thin-film transistor substrate according to yet another embodiment of the present invention;

[0039] Figure 5 This is a cross-sectional view illustrating a thin-film transistor substrate according to yet another embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram illustrating a display device according to yet another embodiment of the present invention;

[0041] Figure 7 It is a diagram Figure 6 The circuit diagram of any pixel;

[0042] Figure 8 It is a diagram Figure 7 A planar image of pixels;

[0043] Figure 9 It is along Figure 8 A sectional view taken from line III-III';

[0044] Figure 10 It is along Figure 8 A sectional view taken from line IV-IV'. Detailed Implementation

[0045] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0046] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0047] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0048] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0049] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0050] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0051] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0052] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0053] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0054] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0055] In the accompanying drawings, even when depicted in different figures, the same or similar elements are referred to by the same reference numerals.

[0056] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0057] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0058] Figure 1A This is a plan view illustrating a thin-film transistor substrate according to an embodiment of the present invention; Figure 1B It is along Figure 1A A sectional view taken from line I-I'.

[0059] According to one embodiment of the present invention, a thin-film transistor substrate 100 includes a first thin-film transistor TFT1 and a second thin-film transistor TFT2 on a base substrate 110.

[0060] Reference Figure 1A and1B The first thin-film transistor TFT1 may include a first active layer 130 on the base substrate 110 and a first gate 150 separated from the first active layer 130. The second thin-film transistor TFT2 may include a second active layer 230 on the base substrate 110, a second gate 250 separated from the second active layer 230, and an auxiliary gate 240 between the second active layer 230 and the second gate 250.

[0061] The following will describe in detail each component of the thin-film transistor substrate 100 according to one embodiment of the present invention.

[0062] Glass or plastic can be used as the base substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as the plastic. When polyimide is used as the base substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on the base substrate 110.

[0063] Light-shielding layers 111 and 112 may be disposed on the base substrate 110. Light-shielding layers 111 and 112 can block light incident from the outside to protect thin-film transistors TFT1 and TFT2. Light-shielding layers 111 and 112 may be omitted.

[0064] According to one embodiment of the present invention, light-shielding layers 111 and 112 may overlap with at least one of the first thin-film transistor TFT1 and the second thin-film transistor TFT2. In particular, light-shielding layers 111 and 112 may overlap with the second thin-film transistor TFT2.

[0065] Reference Figure 1A and 1B The first light-shielding layer 111 can be disposed on the base substrate 110, and the first buffer layer 121 can be disposed on the first light-shielding layer 111. The second light-shielding layer 112 can be disposed on the first buffer layer 121, and the second buffer layer 122 can be disposed on the second light-shielding layer 112.

[0066] Buffer layers 121 and 122 may be made of an insulating material. For example, buffer layers 121 and 122 may include at least one of silicon oxide, silicon nitride, and insulating materials such as metal-based oxides. Buffer layers 121 and 122 may have a single-layer structure or may have a multi-layer structure.

[0067] Buffer layers 121 and 122 can protect active layers 130 and 230 by blocking air and moisture. In addition, the surface of the base substrate 110 on which the light-shielding layers 111 and 112 are disposed can be made uniform by buffer layers 121 and 122.

[0068] The first light-shielding layer 111 and the second light-shielding layer 112 are separated from and overlap each other. One of the first light-shielding layer 111 and the second light-shielding layer 112 can be connected to the second active layer 230, and the other of the first light-shielding layer 111 and the second light-shielding layer 112 can be connected to the second gate 250. Specifically, the first light-shielding layer 111 can be connected to the second gate 250, and the second light-shielding layer 112 can be connected to the second active layer 230.

[0069] exist Figure 1A and 1B In the process, the first light-shielding layer 111 is connected to the second gate 250 via a contact hole, and the second light-shielding layer 112 is connected to the second connection portion 230b of the second active layer 230 via a contact hole.

[0070] According to one embodiment of the present invention, the first light-shielding layer 111 and the second light-shielding layer 112 may form a capacitor.

[0071] Reference Figure 1B The first active layer 130 and the second active layer 230 can be disposed on the second buffer layer 122.

[0072] Reference Figure 1A and 1B The first active layer 130 and the second active layer 230 can be formed as one unit and connected to each other.

[0073] According to one embodiment of the present invention, the first active layer 130 and the second active layer 230 may be formed of the same semiconductor material. The first active layer 130 and the second active layer 230 may comprise an oxide semiconductor material.

[0074] The first active layer 130 and the second active layer 230 may, for example, include at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, FIZO (FeInZnO) based oxide semiconductor material, ZnO based oxide semiconductor material, SIZO (SiInZnO) based oxide semiconductor material, ZnON (Zn oxynitride) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, and GZTO (GaZnSnO) based oxide semiconductor material.

[0075] However, one embodiment of the present invention is not limited to the above example, and the first active layer 130 and the second active layer 230 may be formed by other semiconductor materials known in the art.

[0076] The first active layer 130 may include a channel portion 130n, a first connecting portion 130a, and a second connecting portion 130b. The first connecting portion 130a of the first active layer 130 may be connected to one side of the channel portion 130n, and the second connecting portion 130b may be connected to the other side of the channel portion 130n.

[0077] The second active layer 230 may include a channel portion 230n, a first connecting portion 230a, and a second connecting portion 230b. The first connecting portion 230a of the second active layer 230 may be connected to one side of the channel portion 230n, and the second connecting portion 230b may be connected to the other side of the channel portion 230n.

[0078] The first connecting portions 130a and 230a and the second connecting portions 130b and 230b can be formed by selectively conductiveizing the first active layer 130 and the second active layer 230.

[0079] Reference Figure 1B The second connecting portion 130b of the first active layer 120 and the first connecting portion 230a of the second active layer 230 can be connected to each other. Since the first active layer 130 and the second active layer 230 are made of the same material, the boundary between the second connecting portion 130b of the first active layer 130 and the first connecting portion 230a of the second active layer 230 is not clear.

[0080] For ease of description, the first connecting parts 130a and 230a and the second connecting parts 130b and 230b are distinguished from each other, and their positions can be exchanged independently.

[0081] Reference Figure 1B A first gate insulating layer 141 is disposed on the first active layer 130 and the second active layer 230. The first gate insulating layer 141 may be disposed above the first active layer 130 and the second active layer 230 and above the second buffer layer 122.

[0082] The first gate insulating layer 141 has insulating properties and protects the first active layer 130 and the second active layer 230. The first gate insulating layer 141 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The first gate insulating layer 141 may have a single-layer structure or a multi-layer structure.

[0083] The first gate 150 and the auxiliary gate 240 are disposed on the first gate insulating layer 141. (Refer to...) Figure 1A and 1B The auxiliary gate 240 may be integrally formed with the first gate 150. The auxiliary gate 240 may be connected to the first gate 150.

[0084] According to one embodiment of the present invention, the same voltage as that applied to the first gate 150 may be applied to the auxiliary gate 240. Specifically, when the first gate voltage is applied to the first gate 150, the first gate voltage may also be applied to the auxiliary electrode 240.

[0085] According to one embodiment of the present invention, the first gate 150 and the auxiliary gate 240 may be formed by lines passing through the first active layer 130 and the second active layer 230. For example, a portion of the line overlapping the first active layer 130 may be the first gate 150.

[0086] The first gate 150 is separated from the first active layer 130 and at least partially overlaps with the first active layer 130. The first gate 150 overlaps with the channel portion 130n of the first active layer 130.

[0087] The portion of the line passing through the upper part of the first active layer 130 and the second active layer 230, overlapping with the second active layer 230, can be an auxiliary gate 240. (Refer to...) Figure 1B The auxiliary gate 240 is configured to be separated from the second active layer 230 and the second gate 250.

[0088] A second gate insulating layer 142 is disposed on the first gate 150 and the auxiliary gate 240. The second gate insulating layer 142 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The second gate insulating layer 142 may have a single-layer structure or a multi-layer structure.

[0089] Reference Figure 1B The second gate insulating layer 142 can cover the entire area of ​​the upper portion of the base substrate 110.

[0090] The second gate 250 is disposed on the second gate insulating layer 142.

[0091] The second gate 250 is separated from the second active layer 230 and at least partially overlaps with the second active layer 230. The second gate 250 overlaps with the channel portion 230 of the second active layer 230.

[0092] According to one embodiment of the present invention, an auxiliary gate 240 is disposed between the second active layer 230 and the second gate 250.

[0093] According to one embodiment of the present invention, the second gate 250 at least partially overlaps with the auxiliary gate 240. The second gate 250 may cover the auxiliary gate 240. (See also...) Figure 1A and 1B The second gate 250 can cover the entire auxiliary gate 240 on the plane.

[0094] Reference Figure 1BThe second gate 250 may completely cover the auxiliary gate 240 on the plane, but one embodiment of the present invention is not limited thereto, and the second gate 250 may cover a portion of the auxiliary gate 240 on the plane.

[0095] According to one embodiment of the present invention, the first connection portions 130a, 230a and the second connection portions 130b, 230b can be formed by performing conductivity using the first gate 150 and the second gate 250 as masks. For example, after forming the second gate 250, doping can be performed using the first gate 150 and the second gate 250 as masks to selectively conduct the first active layer 130 and the second active layer 230. As a result, the first connection portions 130a and 130b of the first active layer 130 can be formed, and the first connection portions 230a and 230b of the second active layer 230 can also be formed.

[0096] However, the conductivity method according to one embodiment of the present invention is not limited to doping, and can be performed by other methods known in the art. For example, conductivity can be performed by etching and plasma treatment of the gate insulating layers 141 and 142.

[0097] An interlayer insulating layer 170 may be disposed on the second gate 250. The interlayer insulating layer 170 is an insulating layer made of insulating material. The interlayer insulating layer 170 may be made of organic material, may be made of inorganic material, or may be made of a stack of organic and inorganic layers.

[0098] The source 161 of the first thin-film transistor TFT1 and the drain 262 of the second thin-film transistor TFT2 can be disposed on the interlayer insulating layer 170. The source 161 of the first thin-film transistor TFT1 can be connected to the first active layer 130. The drain 262 of the second thin-film transistor TFT2 can be connected to the second active layer 230.

[0099] However, one embodiment of the present invention is not limited to the above example; according to one embodiment of the present invention, reference numeral "161" may be the drain of the first thin-film transistor TFT1. Furthermore, reference numeral "262" may be the source of the second thin-film transistor TFT2.

[0100] Each of the source 161 of the first thin-film transistor TFT1 and the drain 262 of the second thin-film transistor TFT2 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the source 161 of the first thin-film transistor TFT1 and the drain 262 of the second thin-film transistor TFT2 may be constituted by a single layer made of metal or metal alloy, or may be formed as two or more layers.

[0101] Generally, multiple thin-film transistors operate by interconnecting with each other in an electronic device. In an electronic device employing a first thin-film transistor TFT1 and a second thin-film transistor TFT2 according to an embodiment of the present invention, a first active layer 130 and a second active layer 230 may be designed to be interconnected. In this case, since the first active layer 130 and the second active layer 230 are interconnected, separate electrodes or pads for connecting the first active layer 130 to the second active layer 230 are not required. Therefore, contact holes for connecting the first active layer 130 to the second active layer 230 do not need to be formed.

[0102] According to one embodiment of the present invention, one of the first connection portions 130a, 230a and the second connection portions 130b, 230b can be a source region and the other can be a drain region. The first connection portion 130a, 230a or the second connection portion 130b, 230b can be used as a source or drain without the need for a separate electrode or a separate pad component.

[0103] Figure 1C This is a partial enlarged view of the channel portion 230n, the second gate 250, and the auxiliary gate 240 of the second active layer 230.

[0104] Reference Figure 1C The auxiliary gate 240 may be disposed between the second active layer 230 and the second gate 250, and may be covered by the second gate 250.

[0105] The length L2 of the second gate 250 is greater than the length L1 of the auxiliary gate 240. The length L2 of the second gate 250 can be approximately equal to the length of the channel portion 230n of the second active layer 230.

[0106] A portion ar1 of the channel portion 230n of the second active layer 230 may overlap with the auxiliary gate 240, while other portions ar2 and ar3 of the channel portion 230n of the second active layer 230 may not overlap with the auxiliary gate 240. Specifically, the channel portion 230n of the second active layer 230 may include a first region ar1 that overlaps with both the auxiliary gate 240 and the second gate 250, and a second region ar2 and a third region ar3 that overlap with the second gate 250 but not with the auxiliary gate 240. The second region ar2 and the third region ar3 of the channel portion 230n of the second active layer 230 overlap with the second gate 250 but not with the auxiliary gate 240.

[0107] Reference Figure 1CThe second region ar2 of the channel portion 230n of the second active layer 230, which is a portion facing the first connection portion 230a, overlaps with the second gate 250 but does not overlap with the auxiliary gate 240. Furthermore, the third region ar3 of the channel portion 230n of the second active layer 230, which is a portion facing the second connection portion 230b, overlaps with the second gate 250 but does not overlap with the auxiliary gate 240.

[0108] The lengths of the second region ar2 and the third region ar3 may be the same or different from each other. One of the second region ar2 and the third region ar3 may have a larger length than the other.

[0109] Either the length of the second region ar2 or the length of the third region ar3 can be zero (0). Specifically, either the second region ar2 or the third region ar3 may not exist. In this case, the other of the second region ar2 and the third region ar3 must exist.

[0110] Since the auxiliary gate 240 is connected to the first gate 150, when an on-state voltage is applied to the first gate 150, the same on-state voltage is also applied to the auxiliary gate 240.

[0111] Since the second region ar2 and the third region ar3 of the channel portion 230n of the second active layer 230 do not overlap with the second gate 240, the channel portion 230n of the second active layer 230 does not have current characteristics when no on-state voltage is applied to the second gate 250, even if an on-state voltage is applied to the auxiliary gate 240. Therefore, even if the auxiliary gate 240 is set to be closer to the second active layer 230 than the second gate 250, the auxiliary gate 240 will not independently control the driving of the second thin-film transistor TFT2.

[0112] Furthermore, the electric field applied by the second gate 250 can be covered by the auxiliary gate 240. Therefore, even if a conduction voltage is applied to the second gate 250, the channel portion 230n of the second active layer 230 does not have current characteristics if the conduction voltage is not applied to the auxiliary gate 240. Therefore, according to one embodiment of the present invention, when a conduction voltage is applied to the second gate 250 to drive the second thin-film transistor TFT2, the conduction voltage is also applied to the auxiliary gate 240. When a conduction voltage is applied to the auxiliary gate 240, the conduction voltage can be applied to the second gate 250.

[0113] According to one embodiment of the present invention, the first thin-film transistor TFT1 is configured to be turned on during the time when the second thin-film transistor TFT2 is turned on. The second thin-film transistor TFT2 is turned on when the first thin-film transistor TFT1 is in the on state.

[0114] Furthermore, according to one embodiment of the present invention, when a second gate voltage is applied to the second gate 250, a first gate voltage is applied to the first gate 150. As a result, the driving of the second thin-film transistor TFT2 can be controlled by the second gate 250.

[0115] According to one embodiment of the present invention, when the first thin-film transistor TFT1 is turned on, the second thin-film transistor TFT2 is not always turned on. On the other hand, the first thin-film transistor TFT1 is turned on during the period when the second thin-film transistor TFT2 is turned on. Furthermore, even if the first thin-film transistor TFT1 is in the turned-on state and a turn-on voltage is applied to the auxiliary gate 240, the second thin-film transistor TFT can be turned off by applying a cutoff voltage to the second gate 250. Therefore, the turning on and off of the second thin-film transistor TFT can be controlled by the second gate 250.

[0116] Figure 2 This is a cross-sectional view illustrating a thin-film transistor substrate 200 according to another embodiment of the present invention. To avoid repetition, descriptions of previously described components will be omitted.

[0117] Reference Figure 2 The first gate insulating layer 141 and the second gate insulating layer 142 can be patterned. The first gate insulating layer 141 and the second gate insulating layer 142 can be patterned by etching or ashing.

[0118] For example, after forming the first gate 150, the auxiliary gate 240, and the second gate 250, the first gate 150 and the second gate 250 can be used as masks to pattern the first gate insulating layer 141 and the second gate insulating layer 142. As a result, the first gate insulating layer 141 can remain below the first gate 150, and the first gate insulating layer 141 and the second gate insulating layer 142 can remain below the second gate 250.

[0119] Figure 3A This is a plan view illustrating a thin-film transistor substrate 300 according to another embodiment of the present invention. Figure 3B It is along Figure 3A The sectional view taken from line II-II'.

[0120] Reference Figure 3A and 3B A first light-shielding layer 111 may be disposed on a base substrate 110, a first buffer layer 121 may be disposed on the first light-shielding layer 111, and a second light-shielding layer 112 may be disposed on the first buffer layer 121. In addition, an auxiliary light-shielding layer 115 may be disposed on the first buffer layer 121.

[0121] Reference Figure 3A and 3BThe first light-shielding layer 111 can be connected to the second gate 250 of the second thin film transistor TFT2 via a contact hole, and the second light-shielding layer 112 can be connected to the second active layer 230 of the second thin film transistor TFT2 via a contact hole.

[0122] The first light-shielding layer 111 and the second light-shielding layer 112 can be separated from each other and overlap each other to form a capacitor cap.

[0123] Reference Figure 3A and 3B The auxiliary light-shielding layer 115 can be connected to the gate 150 of the first thin-film transistor TFT1 via the connecting electrode 117. In this case, the auxiliary light-shielding layer 115 can be used as the gate of the first thin-film transistor TFT1. As a result, the first thin-film transistor TFT1 can have a dual-gate structure.

[0124] Figure 4 This is a cross-sectional view illustrating a thin-film transistor substrate 400 according to another embodiment of the present invention.

[0125] Reference Figure 4 The auxiliary gate 240 may be disposed on one side of the channel portion 230n of the second active layer 230. The second gate 250 may cover at least a portion of the auxiliary gate 240 and may extend to the other side of the channel portion 230n of the second active layer 230. The second gate 250 may not completely cover the auxiliary gate 240.

[0126] According to another embodiment of the present invention, the channel portion 230n of the second active layer 230 may overlap with at least one of the second gate 250 and the auxiliary gate 240. At least a portion of the channel portion 230n of the second active layer 230 may overlap with the second gate 250 and the auxiliary gate 240.

[0127] The portion of the channel portion 230n of the second active layer 230 facing the first connection portion 230a overlaps with the auxiliary gate 240, but may not overlap with the second gate 250. Although Figure 4 Not shown, but the portion of the channel portion 230n of the second active layer 230 facing the second connection portion 230b may overlap with the auxiliary gate 240, but may not overlap with the second gate 250.

[0128] Figure 4 Can correspond to Figure 1C The case where the length of the second region ar2 is zero (0). Although the second gate 250 and the auxiliary gate 240 are as... Figure 4 The setup is as shown, but since the first thin-film transistor TFT1 remains in the on state during the period when the second thin-film transistor TFT2 is on, the driving of the second thin-film transistor TFT2 can be controlled by the second gate 250.

[0129] Figure 5 This is a cross-sectional view illustrating a thin-film transistor substrate 500 according to another embodiment of the present invention.

[0130] Reference Figure 5 The first active layer 130 and the second active layer 230 may have a multilayer structure. According to another embodiment of the present invention, the first active layer 130 and the second active layer 230 may include a first oxide semiconductor layer 131, 231 and a second oxide semiconductor layer 132, 232 on the first oxide semiconductor layer 131, 231.

[0131] Since the first active layer 130 and the second active layer 230 can be formed together with the same composition, the first oxide semiconductor layer 131 of the first active layer 130 and the first oxide semiconductor layer 231 of the second active layer 230 can be identical to each other. Furthermore, the second oxide semiconductor layer 132 of the first active layer 130 and the second oxide semiconductor layer 232 of the second active layer 230 can be identical to each other.

[0132] The first oxide semiconductor layers 131 and 231 may have higher mobility than the second oxide semiconductor layers 132 and 232. Therefore, the first oxide semiconductor layers 131 and 231 can be used as the main channel layer. The second oxide semiconductor layers 132 and 232 can be used as the support layer.

[0133] The first oxide semiconductor layers 131 and 231 may be made of an oxide semiconductor material with high mobility characteristics. The second oxide semiconductor layers 132 and 232 may be made of an oxide semiconductor material with excellent film stability, but one embodiment of the present invention is not limited thereto. The first oxide semiconductor layers 131 and 231 may have excellent film stability, while the second oxide semiconductor layers 132 and 232 may have high mobility characteristics.

[0134] like Figure 5 As shown, the structure formed by stacking two semiconductor layers to form active layers 130 and 230 will be called a bi-layer structure.

[0135] Although not shown, a third oxide semiconductor layer may be disposed on the second oxide semiconductor layers 132, 232.

[0136] The following will describe in detail the display devices using the above-described thin-film transistor substrates 100, 200, 300, 400 and 500.

[0137] Figure 6 This is a schematic diagram illustrating a display device 600 according to another embodiment of the present invention.

[0138] like Figure 6As shown, a display device 600 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0139] The display panel 310 includes gate lines GL and data lines DL, and a plurality of pixels P are disposed in the intersection area of ​​the gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0140] The controller 340 controls the gate driver 320 and the data driver 330.

[0141] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0142] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0143] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0144] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0145] According to one embodiment of the present invention, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0146] Gate driver 320 may include shift register 350.

[0147] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage that enables the switching elements (thin-film transistors) disposed in the pixel P.

[0148] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0149] Figure 7 It is a diagram Figure 6 The circuit diagram of any pixel P. Figure 8 It is a diagram Figure 7 A planar image of pixel P. Figure 9 It is along Figure 8 The sectional view taken from line III-III'. Figure 10 It is along Figure 8 A sectional view taken from line IV-IV'.

[0150] Figure 7 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 600, which includes an organic light-emitting diode (OLED) as a display element 710.

[0151] According to another embodiment of the present invention, the pixel P of the display device 600 includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit (PDC) for driving the display element 710. The display element 710 is connected to the pixel driving circuit (PDC).

[0152] The pixel driving circuit PDC may include thin-film transistors TR1, TR2, TR3, and TR4.

[0153] Specifically, Figure 7 The pixel driving circuit PDC may include a first thin-film transistor TR1 as a light-emitting control transistor, a second thin-film transistor TR2 as a driving transistor, a third thin-film transistor TR3 as a sensing transistor, and a fourth thin-film transistor TR4 as a switching transistor.

[0154] According to another embodiment of the present invention, the pixel driving circuit PDC may include the first thin film transistor TFT1 and the second thin film transistor TFT2 of the thin film transistor substrates 100, 200, 300, 400 and 500.

[0155] For example, the first thin-film transistor TR1, which serves as a light-emitting control transistor, can be the first thin-film transistor TFT1 of the aforementioned thin-film transistor substrates 100, 200, 300, 400, and 500. The second thin-film transistor TR2, which serves as a driving transistor, can be the second thin-film transistor TFT2 of the aforementioned thin-film transistor substrates 100, 200, 300, 400, and 500.

[0156] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0157] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for the driving pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL. Additionally, the emission control signal EM is provided to the emission control line EL.

[0158] The first thin-film transistor TR1 serves as a light-emitting control transistor for controlling the light-emitting time of the second thin-film transistor TR2. The first thin-film transistor TR1 transmits a drive voltage Vdd or a shielding drive voltage Vdd to the second thin-film transistor TR2 according to the light-emitting control signal EM. When the first thin-film transistor TR1 is turned on, current is supplied to the second thin-film transistor TR2 to output light from the display element 710.

[0159] The fourth thin-film transistor TR4, acting as a switching transistor, is connected to the gate line GL and the data line DL. The second thin-film transistor TR2, acting as a driving transistor, controls the amplitude of the current output to the display element 710 based on the data voltage Vdata transmitted via the fourth thin-film transistor TR4. The third thin-film transistor TR3, acting as a sensing transistor, senses the characteristics of the second thin-film transistor TR2.

[0160] The storage capacitor Cst is disposed between the gate of the second thin-film transistor TR2 and the display element 710.

[0161] Specifically, the fourth thin-film transistor TR4 is turned on by the scan signal SS provided to the gate line GL, and transmits the data voltage Vdata provided to the data line DL to the gate of the second thin-film transistor TR2.

[0162] The third thin-film transistor TR3 is connected to the reference line RL and is turned on or off by the sensing control signal SCS, and senses the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0163] The fourth thin-film transistor TR4 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0164] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0165] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0166] When the fourth thin-film transistor TR4 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gate of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata is charged into the storage capacitor Cst formed between the gate (i.e., the second node n2) and the source (i.e., the first node n1) of the second thin-film transistor TR2.

[0167] The amount of current supplied to the organic light-emitting diode (OLED) 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light output from the display element 710.

[0168] According to another embodiment of the present invention, the pixel driving circuit PDC can be formed in various structures other than those described above. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0169] Reference Figure 8 , 9 10. A first thin-film transistor TR1, a second thin-film transistor TR2, a third thin-film transistor TR3, and a fourth thin-film transistor TR4 are disposed on a base substrate 110.

[0170] The base substrate 110 can be made of glass or plastic. As the base substrate 110, a plastic with flexible properties, such as polyimide (PI), can be used.

[0171] Reference Figure 9 and 10 A first light-shielding layer 111 is disposed on the base substrate 110. Additionally, a data line DL may be disposed on the base substrate 110.

[0172] The first buffer layer 121 may be disposed on the first light-shielding layer 111. The second light-shielding layer 112 may be disposed on the first buffer layer 121, and the second buffer layer 122 may be disposed on the second light-shielding layer 112.

[0173] Active layers A1, A2, A3 and A4 are disposed on the second buffer layer 122.

[0174] Reference Figure 8 and 9The first active layer A1 of the first thin-film transistor TR1, the second active layer A2 of the second thin-film transistor TR2, and the third active layer A3 of the third thin-film transistor TR3 can be integrally formed on the second buffer layer 122. The first active layer A1, the second active layer A2, and the third active layer A3, which are formed integrally, can constitute a first block.

[0175] A portion of the first active layer A1 can be made conductive to serve as the drain D1 of the first thin-film transistor TR1.

[0176] A portion of the second active layer A2 can be made conductive to serve as the drain D2 of the second thin-film transistor TR2, and another portion of the second active layer A2 can be made conductive to serve as the source S2 of the second thin-film transistor TR2.

[0177] A portion of the third active layer A3 can be made conductive to serve as the drain D3 of the third thin-film transistor TR3.

[0178] Reference Figure 8 and 9 The second active layer A2 of the second thin-film transistor TR2 can be connected to the second light-shielding layer 112 via the second contact hole H2. The second light-shielding layer 112 can be connected to the source S2 of the second thin-film transistor TR2.

[0179] Reference Figure 8 and 10 The fourth active layer A4 of the fourth thin-film transistor TR4 is separately formed on the second buffer layer 122. The fourth active layer A4 may constitute a second block portion that is distinct from the first active layer A1, the second active layer A2 and the third active layer A3.

[0180] A portion of the fourth active layer A4 can be made conductive to serve as the drain D4 of the fourth thin-film transistor TR4, and another portion of the fourth active layer A4 can be made conductive to serve as the source S4 of the fourth thin-film transistor TR4.

[0181] Reference Figure 8 , 9 In the first thin-film transistor TR1, which serves as a light-emitting control transistor, and the second active layer A2 of the second thin-film transistor TR2, which serves as a driving transistor, can be formed as a single unit. The first active layer A1 of the first thin-film transistor TR1, which serves as a light-emitting control transistor, and the second active layer A2 of the second thin-film transistor TR2, which serves as a driving transistor, can be distinguished from the fourth active layer A4 of the fourth thin-film transistor TR4, which serves as a switching transistor.

[0182] Furthermore, the third active layer A3 of the third thin-film transistor TR3, which serves as a sensing transistor, can be integrally formed with the first active layer A1 of the first thin-film transistor TR1, which serves as a light-emitting control transistor, and the second active layer A2 of the second thin-film transistor TR2, which serves as a driving transistor. The third active layer A3 of the third thin-film transistor TR3, which serves as a sensing transistor, can be distinguished from the fourth active layer A4 of the fourth thin-film transistor TR4, which serves as a switching transistor.

[0183] Reference Figure 8 and 10 The fourth active layer A4 of the fourth thin-film transistor TR4 can be connected to the first light-shielding layer 111 via the sixth contact hole H6. Furthermore, the fourth active layer A4 of the fourth thin-film transistor TR4 can be connected to the data line DL via the seventh contact hole H7.

[0184] The first gate insulating layer 141 is disposed on the active layers A1, A2, A3 and A4.

[0185] The light emission control line EL, the sensing control line SCL, and the gate line GL are disposed on the first gate insulating layer 141.

[0186] The portion of the light-emitting control line EL that overlaps with the first active layer A1 becomes the first gate G1 of the first thin-film transistor TR1. Furthermore, another portion of the light-emitting control line EL that overlaps with the second active layer A2 becomes the auxiliary gate 240. In other words, the first gate G1 and the auxiliary gate 240 can be corresponding portions of the light-emitting control line EL.

[0187] According to another embodiment of the present invention, the first gate G1 and the auxiliary gate 240 may be portions of the light emission control line EL. Therefore, the light emission control signal EM can be applied to the first gate G1 and the auxiliary gate 240.

[0188] The portion of the light-emitting control line SCL that overlaps with the third active layer A3 becomes the third gate G3 of the third thin-film transistor TR3.

[0189] Reference Figure 8 and 10 The portion of the gate line GL that overlaps with the fourth active layer A4 becomes the fourth gate G4 of the fourth thin-film transistor TR4.

[0190] The second gate insulating layer 142 is disposed on the light emission control line EL, the sensing control line SCL, and the gate line GL.

[0191] The reference line RL and the second gate G2 of the second thin-film transistor TR2 are disposed on the second gate insulating layer 142. The pad electrode 165 is disposed on the second gate insulating layer 142.

[0192] The reference line RL is connected to the third active layer A3 of the third thin-film transistor TR3 via the third contact hole H3. The reference line RL can be used as the source S3 of the third thin-film transistor TR3.

[0193] Reference Figure 10 The second gate G2 of the second thin-film transistor TR2 can be connected to the first light-shielding layer 111 via the fourth contact hole. As a result, the second gate G2 can be connected to the fourth thin-film transistor TR4 via the first light-shielding layer 111.

[0194] The data voltage Vdata provided via the data line DL can be supplied to the second gate G2 of the second thin film transistor TR2 via the fourth thin film transistor TR4 and the first light-shielding layer 111.

[0195] The first light-shielding layer 111 connected to the second gate G2 can be the first capacitor electrode CE1 of the storage capacitor Cst.

[0196] The second light-shielding layer 112 connected to the source S2 of the second thin-film transistor TR2 can be the second capacitor electrode CE2 of the storage capacitor Cst.

[0197] As a result, the first capacitor electrode CE1 and the second capacitor electrode CE2 can overlap each other to form a storage capacitor Cst.

[0198] Since the first light-shielding layer 111 disposed below the thin-film transistors TR1, TR2, TR3 and TR4 can be the first capacitor electrode CE1 and the second light-shielding layer 112 can be the second capacitor electrode CE2, a large-area storage capacitor Cst can be formed without considering the area of ​​the thin-film transistors TR1, TR2, TR3 and TR4.

[0199] Reference Figure 10 The pad electrode 165 is connected to the second light-shielding layer 112 via the fifth contact hole H5. As a result, the pad electrode 165 can be connected to the source S2 of the second thin-film transistor TR2 and the storage capacitor Cst.

[0200] An interlayer insulating layer 170 is disposed on the reference line RL, the second gate G2, and the pad electrode 165.

[0201] The drive power line PL is located on the interlayer insulation layer 170.

[0202] The driving power line PL can be connected to the first active layer A1 of the first thin-film transistor TR1 via the first contact hole H1. The driving power line PL can be used as the source S1 of the first thin-film transistor TR1.

[0203] The driving voltage Vdd can be transmitted to the first thin-film transistor TR1 via the driving power line PL.

[0204] A planarization layer 175 is disposed on the drive power line PL. The planarization layer 175 planarizes the upper portions of thin-film transistors TR1, TR2, TR3 and TR4, and protects thin-film transistors TR1, TR2, TR3 and TR4.

[0205] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. (Refer to...) Figure 10 The first electrode 711 of the display element 710 is connected to the pad electrode 165 via the eighth contact hole H8. As a result, the first electrode 711 of the display element 710 can be connected to the source S2 of the second thin-film transistor TR2 and the storage capacitor Cst.

[0206] A dam layer 750 is disposed at the edge of the first electrode 711 of the display element 710. The dam layer 750 defines the light-emitting area of ​​the display element 710.

[0207] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 10 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 600 according to one embodiment of the present invention is an organic light-emitting display device.

[0208] According to the present invention, the following beneficial effects can be obtained.

[0209] According to one embodiment of the present invention, thin-film transistors can be integrated at high density because a large number of thin-film transistors and the lines connected to them can be efficiently arranged. In particular, according to one embodiment of the present invention, space utilization is excellent because the thin-film transistors can be effectively implemented even when signal lines overlap with the gates of the thin-film transistors. Furthermore, according to one embodiment of the present invention, capacitor area can be easily ensured.

[0210] In a display device according to one embodiment of the present invention, the driving of the driving transistor can be actively controlled even if the light-emitting control line overlaps with the gate of the driving transistor. Therefore, since it is easy to arrange the elements in the display device and easy to ensure space for the storage capacitor, the driving voltage of the pixel can be stably charged and controlled, thereby enabling the display device to have excellent display performance.

[0211] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from the spirit or scope thereof. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A thin-film transistor substrate, comprising: First thin-film transistor and second thin-film transistor on a base substrate. The first thin-film transistor includes: The first active layer on the base substrate; and The first gate, separated from the first active layer, The second thin-film transistor includes: A second active layer on the base substrate; The second gate separated from the second active layer; and An auxiliary gate between the second active layer and the second gate. The first active layer and the second active layer are formed as a single unit and are connected to each other. The auxiliary gate is integrally formed with the first gate and is separated from the second active layer and the second gate. The second gate overlaps with at least a portion of the auxiliary gate. The second active layer includes: Channel section; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, A portion of the channel overlaps with the auxiliary gate, and another portion of the channel that does not overlap with the auxiliary gate overlaps with the second gate.

2. The thin-film transistor substrate of claim 1, wherein the same voltage as applied to the first gate is applied to the auxiliary gate.

3. The thin-film transistor substrate according to claim 1, wherein the first thin-film transistor is configured to be turned on when the second thin-film transistor is turned on.

4. The thin-film transistor substrate according to claim 1, wherein when the second gate voltage is applied to the second gate, the first gate voltage is applied to the first gate.

5. The thin-film transistor substrate according to claim 1, wherein the portion of the channel facing the first connection portion overlaps with the auxiliary gate but does not overlap with the second gate.

6. The thin-film transistor substrate according to claim 1, wherein the portion of the channel facing the second connection portion overlaps with the auxiliary gate but does not overlap with the second gate.

7. The thin-film transistor substrate according to claim 1, wherein the first active layer and the second active layer comprise at least one of IGZO (InGaZnO)-based oxide semiconductor material, IZO (InZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, FIZO (FeInZnO)-based oxide semiconductor material, ZnO-based oxide semiconductor material, SIZO (SiInZnO)-based oxide semiconductor material, ZnON (Zn oxynitride)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, and GZTO (GaZnSnO)-based oxide semiconductor material.

8. The thin-film transistor substrate of claim 1, wherein each of the first active layer and the second active layer comprises: First oxide semiconductor layer; as well as A second oxide semiconductor layer on top of the first oxide semiconductor layer.

9. The thin-film transistor substrate according to claim 1, further comprising: A first light-shielding layer on the base substrate; as well as A second light-shielding layer on top of the first light-shielding layer. The first light-shielding layer and the second light-shielding layer are separated from each other and overlap each other. One of the first light-shielding layer and the second light-shielding layer is connected to the second active layer. The other of the first light-shielding layer and the second light-shielding layer is connected to the second gate.

10. The thin-film transistor substrate of claim 9, wherein the first light-shielding layer and the second light-shielding layer form a capacitor.

11. A display device comprising a thin-film transistor substrate according to any one of claims 1 to 8.

12. The display device according to claim 11, wherein the first thin-film transistor is a light-emitting control transistor and the second thin-film transistor is a driving transistor.

13. The display device according to claim 11, wherein a light emission control signal is applied to the first gate and the auxiliary gate.

14. The display device according to claim 11, wherein the first gate and the auxiliary gate are corresponding portions of a light-emitting control line.

15. The display device according to claim 11, further comprising: A first light-shielding layer on the base substrate; as well as A second light-shielding layer on top of the first light-shielding layer. The first light-shielding layer and the second light-shielding layer are separated from each other and overlap each other. One of the first light-shielding layer and the second light-shielding layer is connected to the second active layer. One of the first light-shielding layer and the second light-shielding layer is connected to the second gate. The storage capacitor is formed by the overlap between the first light-shielding layer and the second light-shielding layer.

16. The display device according to claim 11, further comprising a driving transistor, a light-emitting control transistor, and a switching transistor. The active layer of the driving transistor and the active layer of the light-emitting control transistor are formed as a single unit. The active layer of the driving transistor and the active layer of the light-emitting control transistor are separated from the active layer of the switching transistor.

17. The display device of claim 16, further comprising a sensing transistor, The active layer of the sensing transistor is formed integrally with the active layer of the driving transistor and the active layer of the light-emitting control transistor. The active layer of the sensing transistor is separated from the active layer of the switching transistor.

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