Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area and a binding area located at least one side of the display area; the display area comprises a plurality of display partitions, and the binding area comprises a plurality of binding terminals; the display substrate further comprises at least two switching units; the binding terminals are connected with the switching units, and the switching units are connected with at least two display partitions; or the binding terminals are connected with at least two switching units, and the switching units are connected with at least one display partition; wherein the switching units are configured to make driving signals enter the display partitions under the control of the binding terminals, and the driving signals are used for driving the display partitions to display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the transformation of automobiles towards intelligence, in-vehicle display technology is also developing rapidly. The light-emitting units in automotive headlights are generally passive matrix organic light-emitting diodes (PMOLEDs).

[0003] The inventors of this application have found that the cost of current vehicle lights is relatively high. Summary of the Invention

[0004] This disclosure provides a display substrate and a display device that can solve the problem of high cost of vehicle lights.

[0005] This disclosure provides a display substrate, including: a display area and a bonding area located on at least one side of the display area; the display area includes a plurality of display partitions, and the bonding area includes a plurality of bonding terminals; the display substrate further includes at least two switching units; the bonding terminals are connected to the switching units, and the switching units are connected to at least two of the display partitions; or, the bonding terminals are connected to at least two of the switching units, and the switching units are connected to at least one of the display partitions; wherein, the switching units are configured to, under the control of the bonding terminals, cause a driving signal to enter the display partition, and the driving signal is used to drive the display partition to display.

[0006] In one exemplary embodiment, the plurality of bonding terminals include a first bonding terminal and at least two second bonding terminals. The first bonding terminal is configured to transmit the drive signal, and the second bonding terminals are configured to transmit a switch signal. The switch signal is used to control the switch unit to be turned on or off. The switch unit is connected to the first bonding terminal and the second bonding terminals and is configured to allow the drive signal from the first bonding terminal to enter the display partition under the control of the second bonding terminal.

[0007] In one exemplary embodiment, a single second bonding terminal is connected to at least two of the switching units.

[0008] In one exemplary embodiment, the switching unit includes a third transistor, the gate of which is connected to the second bonding terminal, the first electrode of which is connected to the first bonding terminal, and the second electrode of which is connected to the display partition.

[0009] In one exemplary embodiment, the display partition includes a driving circuit and a light-emitting element. The driving circuit is connected to a scan signal line and a data signal line and is configured to drive the light-emitting element to emit light. The second electrode of the third transistor is connected to the data signal line of the display partition.

[0010] In one exemplary embodiment, in a first direction, the at least two second binding terminals are located on both sides of the binding area; the first direction is the arrangement direction of the plurality of binding terminals.

[0011] In one exemplary embodiment, the switching signal is a clock signal.

[0012] In one exemplary embodiment, the clock signal includes a first clock signal, a second clock signal, and a third clock signal; the second bonding terminal includes a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, wherein the first clock signal terminal is used to transmit the first clock signal, the second clock signal terminal is used to transmit the second clock signal, and the third clock signal terminal is used to transmit the third clock signal.

[0013] In one exemplary embodiment, in a first direction, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are symmetrically distributed along the center line of the plurality of bonding terminals.

[0014] In one exemplary embodiment, the display substrate includes a substrate and a light-emitting structure layer disposed on the substrate. The substrate includes a driving structure layer, and the switching unit and the driving circuit are disposed on the driving structure layer.

[0015] This invention also provides a display device, including the display substrate described above.

[0016] The display substrate proposed in this embodiment, by setting a switching unit on the display substrate, allows the bonding terminals to indirectly control at least two display zones through the switching unit, which helps reduce the number of bonding terminals and thus the number of driver chips required for the display substrate. Furthermore, a smaller number of bonding terminals allows for a narrower bonding area, eliminating the need to widen the flexible printed circuit board. This solves the problem of high cost in automotive lighting.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0018] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0019] Figure 1 This is a schematic diagram of the display substrate for automotive lights in some technologies;

[0020] Figure 2 This is a schematic diagram of the driving circuitry within a partition in some technologies;

[0021] Figure 3 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0022] Figure 4 This is a schematic diagram of the structure of a display substrate in an exemplary embodiment;

[0023] Figure 5 This is a schematic diagram of the circuit principle for driving three display zones with a single first bonding terminal in an exemplary embodiment.

[0024] Figure 6 This is a schematic cross-sectional view of the display substrate in an exemplary embodiment. Detailed Implementation

[0025] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0026] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0027] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0028] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0029] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0030] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0031] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0032] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0033] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0034] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0035] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0036] In some technologies, the light-emitting element of automotive lights is an OLED, which includes a stacked anode, an organic light-emitting layer, and a cathode. The display substrate of the automotive light is structured by depositing an OLED film layer on a substrate, and driving the OLED to emit light by controlling the potential signals of the anode and cathode. Figure 1 This is a schematic diagram of the display board for vehicle lights. (For example...) Figure 1 As shown, the display substrate of the vehicle headlight includes a display area 100' and a peripheral area surrounding the display area 100'. At least one side of the peripheral area is configured as a bonding area 200'. Multiple bonding terminals 201' are provided in the bonding area 200', and these terminals 201' can be sequentially arranged along the extending direction of the bonding area 200'. The display substrate can receive external signals through the multiple bonding terminals 201'. For example, the multiple bonding terminals 201' can be connected to a flexible printed circuit board, which can be connected to a driver chip. The display area 100' includes multiple display partitions 101', and a single bonding terminal 201' is connected to a single display partition 101'. Under the control of the driver chip, the multiple bonding terminals 201' transmit a drive signal from the first power line VDD to the corresponding display partition to illuminate the corresponding display partition. Figure 1For ease of demonstration, only the connection relationship between some display zones and bonding terminals 201' is shown, omitting the connection relationship between other display zones and bonding terminals 201'. By dividing the display area of ​​a single vehicle headlight into multiple display zones, different display zones can be driven separately using an onboard driver chip, which helps to achieve dynamic display of a single vehicle headlight. However, the inventors of this application have found that in the current technology, a single onboard driver chip can be connected to a maximum of 24 bonding terminals 201'. When the number of display zones 101' divided into the display substrate of the vehicle headlight exceeds 24, multiple driver chips are required to drive the display zones for display, increasing the production cost of the vehicle headlight. In order to realize more possibilities for dynamic display, the market demands that a single vehicle headlight have more display zones, such as 60, 80, or even 100 display zones, which greatly increases the number of driver chips required, thus increasing the cost of the display substrate of the vehicle headlight.

[0037] And, as Figure 1 As shown, the number of bonding terminals 201' is at least equal to the number of display partitions 101'. When the display substrate of the vehicle headlight is divided into a large number of display partitions 101', the bonding area 200' needs to have a large number of bonding terminals 201', which will make the width of the bonding area 200' wider. The flexible printed circuit board connected to the bonding area 200' also needs to be widened, further increasing the cost of a single display substrate. In some technologies, the width of the bonding area 200' is reduced by decreasing the width of the bonding terminals 201' and the distance between adjacent bonding terminals 201', but this approach places higher demands on the manufacturing process and does not reduce the number of driver chips required.

[0038] Figure 2 This is a schematic diagram of the driving circuitry within a partition in some technologies. For example... Figure 2As shown, a 2T1C driving circuit can be used within a single display partition, including a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light-emitting element OLED. The gate of the first transistor T1 is electrically connected to the scan signal line, the first electrode of the first transistor T1 is electrically connected to the data signal line, and the second electrode of the first transistor T1 is electrically connected to one end of the storage capacitor Cst. The first electrode of the second transistor T2 is electrically connected to the first power line VDD, and the second electrode of the second transistor T2 is electrically connected to the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is electrically connected to the second power line VSS. One end of the storage capacitor Cst is electrically connected to the gate of the second transistor T2, and the other end of the storage capacitor Cst is electrically connected to the first electrode of the second transistor T2. During display, the scan signal Gate controls the first transistor T1 to turn on. The data signal Date passes through the first transistor T1 and enters the gate of the second transistor T2 and the storage capacitor Cst. Then, the first transistor T1 turns off. Due to the storage effect of the storage capacitor Cst, the gate voltage of the second transistor T2 can continue to maintain the data signal voltage, keeping the second transistor T2 in the on state. The drive current from the first power line VDD enters the light-emitting element OLED through the second transistor T2, driving the OLED to emit light. The first power line VDD can continuously provide a high-level signal, while the signal on the second power line VSS is a low-level signal. The first transistor T1 is a switching transistor, and the second transistor T2 is a driving transistor.

[0039] In an exemplary embodiment, the first transistor T1 and the second transistor T2 can be either P-type transistors or N-type transistors. Using the same type of transistor in the driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display substrate, and improve product yield. In some possible implementations, the first transistor T1 and the second transistor T2 may include both P-type and N-type transistors.

[0040] This disclosure provides a display substrate, including: a display area and a bonding area located on at least one side of the display area; the display area includes a plurality of display partitions, and the bonding area includes a plurality of bonding terminals; the display substrate further includes at least two switching units; the bonding terminals are connected to the switching units, and the switching units are connected to at least two of the display partitions; or, the bonding terminals are connected to at least two of the switching units, and the switching units are connected to at least one of the display partitions; wherein, the switching units are configured to, under the control of the bonding terminals, cause a driving signal to enter the display partition, and the driving signal is used to drive the display partition to display.

[0041] The display substrate proposed in this embodiment, by setting a switching unit on the display substrate, allows the bonding terminals to indirectly control at least two display zones through the switching unit, which helps reduce the number of bonding terminals and thus the number of driver chips required for the display substrate. Furthermore, a smaller number of bonding terminals allows for a smaller bonding area, eliminating the need to widen the flexible printed circuit board. This solves the problem of increased cost for automotive lights when there are many zones.

[0042] In one exemplary embodiment, the plurality of bonding terminals include a first bonding terminal and at least two second bonding terminals. The first bonding terminal is configured to transmit the drive signal, and the second bonding terminals are configured to transmit a switch signal. The switch signal is used to control the switch unit to be turned on or off. The switch unit is connected to the first bonding terminal and the second bonding terminals and is configured to allow the drive signal from the first bonding terminal to enter the display partition under the control of the second bonding terminal.

[0043] In one exemplary embodiment, a single second bonding terminal is connected to at least two of the switching units.

[0044] In one exemplary embodiment, the switching unit includes a third transistor, the gate of which is connected to the second bonding terminal, the first electrode of which is connected to the first bonding terminal, and the second electrode of which is connected to the display partition.

[0045] In one exemplary embodiment, the display partition includes a driving circuit and a light-emitting element. The driving circuit is connected to a scan signal line and a data signal line and is configured to drive the light-emitting element to emit light. The second electrode of the third transistor is connected to the data signal line of the display partition.

[0046] In one exemplary embodiment, in a first direction, the at least two second binding terminals are located on both sides of the binding area; the first direction is the arrangement direction of the plurality of binding terminals.

[0047] In one exemplary embodiment, the switching signal is a clock signal.

[0048] In one exemplary embodiment, the clock signal includes a first clock signal, a second clock signal, and a third clock signal; the second bonding terminal includes a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, wherein the first clock signal terminal is used to transmit the first clock signal, the second clock signal terminal is used to transmit the second clock signal, and the third clock signal terminal is used to transmit the third clock signal.

[0049] In one exemplary embodiment, in a first direction, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are symmetrically distributed along the center line of the plurality of bonding terminals.

[0050] In one exemplary embodiment, the display substrate includes a substrate and a light-emitting structure layer disposed on the substrate. The substrate includes a driving structure layer, and the switching unit and the driving circuit are disposed on the driving structure layer.

[0051] Figure 3 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. This display substrate can be applied to vehicle lights. The display substrate provided in this embodiment can also be applied to other display devices, and this disclosure does not limit its application. To clearly show the connection relationships, Figure 3 The diagram only illustrates the connection of some display partitions. In practical applications, the positional relationship between display partitions and open cells can be compared with... Figure 3 The differences are illustrated in the text. For example... Figure 3 As shown, the display substrate includes a display area 100 and a bonding area 200. The bonding area 200 may be located on at least one side of the display area 100 and is configured to bond a flexible printed circuit (FPC).

[0052] In an exemplary embodiment, the display area 100 may include a plurality of regularly arranged display partitions 101. Each display partition 101 may include a driving circuit and at least one light-emitting element. The driving circuit and the light-emitting element are connected. The driving circuit may include multiple signal lines. The light-emitting color of the at least one light-emitting element may be the same or different. Figure 3 The display partition 101 is rectangular in shape and is arranged in an array in the display area 100. In other embodiments, the shape of the display partition 101 can be triangular, circular, elliptical, quadrilateral or polygonal, etc. The shape and spacing of different display partitions 101 can be the same or different. The number, shape and arrangement of display partitions in the display area 100 can be set as needed, and this disclosure does not limit this.

[0053] In an exemplary embodiment, the light-emitting elements contained in different display partitions 101 may emit the same or different colors. For example, the light-emitting elements may emit colors such as red, orange, and white. A single display partition 101 may contain any number of light-emitting elements, and the shape, size, and spacing of the light-emitting elements can be set as needed. For example, the shape of the light-emitting elements may be a triangle, quadrilateral, circle, ellipse, other quadrilateral shapes, and polygons, etc., and this disclosure does not limit this. In an exemplary embodiment, the light-emitting elements may be LED light sources, OLED light sources, or other forms of light sources, and this disclosure does not limit this.

[0054] In an exemplary embodiment, the bonding region 200 may be located on one side of the display region 100 along the second direction Y. The bonding region 200 may include at least a plurality of bonding terminals 201, which may be arranged sequentially along the first direction X, where the first direction X intersects the second direction Y. The bonding terminals 201 may be connected to the driving circuitry in the display partition 101 via leads. In an exemplary embodiment, the bonding terminals 201 are configured to be bonded to a flexible printed circuit board, and connected to external circuitry via the flexible printed circuit board. Figure 3 As shown, multiple bonding terminals 201 are arranged in a row along a first direction X. Along the first direction X, the multiple bonding terminals 201 can be symmetrically distributed along a center line Z1. When the number of bonding terminals 201 is odd, the center line Z1 can coincide with the bonding terminal 201 located in the middle; when the number of bonding terminals 201 is even, the center line Z1 may not coincide with any of the bonding terminals 201. In other embodiments, the multiple bonding terminals 201 can be arranged in two or more rows along the first direction X, and this disclosure does not impose any limitations on this.

[0055] In an exemplary embodiment, the display substrate further includes a plurality of switching units 102, each switching unit 102 being connected to at least one display partition 101 and configured to control a drive signal to enter the display partition 101, the drive signal being used to illuminate the display partition 101. In an exemplary embodiment, the drive signal can be a current signal. A single bonding terminal 201 can be connected to a single switching unit 102, and a single switching unit 102 can be connected to at least two display partitions 101; or, a single bonding terminal 201 can be connected to at least two switching units 102, and a single switching unit 102 can be connected to at least one display partition 101, so that a single bonding terminal 201 controls at least two display partitions 101. Figure 3 To clearly show the connection relationship, the diagram illustrates the connection between each switch unit 102 and a single display partition 101.

[0056] In an exemplary embodiment, the display zones 101 connected to different switching units 102 can be different, allowing control of all display zones 101 on the display substrate using fewer switching units 102, thus reducing production costs. Alternatively, the display zones 101 connected to different switching units 102 can overlap, enabling control of more combinations of light emission from the display zones 101, forming more display patterns, and realizing more possibilities for dynamic display on the display substrate. The connection relationship between the switching units 102 and the display zones 101 can be selected as needed, and this disclosure does not limit this.

[0057] In an exemplary embodiment, the bonding terminal 201 includes a first bonding terminal 21 and a second bonding terminal 22. The first bonding terminal 21 is configured to transmit a drive signal, and the second bonding terminal 22 is configured to transmit a switching signal. The switching signal is used to control the switching unit 102 to be turned on or off. Each switching unit 102 is connected to the first bonding terminal 21 and the second bonding terminal 22, respectively. In an exemplary embodiment, the first bonding terminal 21 may be connected to at least one switching unit 102, and the second bonding terminal 22 may be connected to at least two switching units 102.

[0058] By configuring the switching unit 102 to transmit drive signals between the first bonding terminal 21 and the display partition 101, a single first bonding terminal 21 can control two or more display partitions 101, greatly reducing the number of first bonding terminals 21. This not only helps reduce the number of driver chips required for the display substrate but also helps reduce the width of the bonding area 200 along the first direction X, thereby reducing the width of the bonded flexible printed circuit board and lowering the production cost of the display substrate. In an exemplary embodiment, a single switching unit 102 can control multiple display partitions 101, reducing the number of switching units required for the display substrate, further reducing the width of the bonded FPC, and lowering the production cost of the display substrate.

[0059] In an exemplary embodiment, the switching unit 102 may include a third transistor T3. The gate of the third transistor T3 may be connected to the second bonding terminal 22 and is turned on or off under the control of a switching signal. The first terminal of the third transistor T3 may be connected to the first bonding terminal 21, and the second terminal of the third transistor T3 may be connected to a display partition. When the third transistor T3 is turned on, a driving signal can be transmitted to the corresponding display partition for display. In other embodiments, the switching unit 102 may be other forms of switching devices, and this disclosure does not limit this. In an exemplary embodiment, the switching unit 102 may be normally closed and turned on when needed, or the switching unit 102 may be normally open and turned off when needed, and this disclosure does not limit this.

[0060] In an exemplary embodiment, when the switching unit 102 includes a third transistor T3, the switching signal can be a high-potential signal and a low-potential signal to control the turning on and off of the third transistor T3. In an exemplary embodiment, the switching signal transmitted by the second bonding terminal 22 can be a clock signal (CK), and different clock signals can be set as needed to control different display zones.

[0061] In an exemplary implementation, such as Figure 3As shown, in the first direction X, the second bonding terminal 22 can be located on both sides of the first bonding terminal 21. By placing the second bonding terminal 22 on both sides of the first bonding terminal 21, wiring on the display substrate can be facilitated. The switching signals received by the second bonding terminals 22 located on both sides of the first bonding terminal 21 can be the same or different.

[0062] In an exemplary embodiment, the display substrate can receive three different clock signals to control different display zones separately. These three different clock signals are a first clock signal CK1, a second clock signal CK2, and a third clock signal CK3. The second bonding terminal 22 may include a first clock signal terminal 221, a second clock signal terminal 222, and a third clock signal terminal 223. The first clock signal terminal 221 is used to transmit the first clock signal CK1, the second clock signal terminal 222 is used to transmit the second clock signal CK2, and the third clock signal terminal 223 is used to transmit the third clock signal CK3. Figure 3 As shown, along the first direction X, the first clock signal terminal 221, the second clock signal terminal 222, and the third clock signal terminal 223 can be located to the left of the first bonding terminal 21. The three second bonding terminals 22 located to the right of the first bonding terminal 21 can be symmetrically arranged with the three second bonding terminals 22 located to the left of the first bonding terminal 21 along the center line Z1 of the plurality of bonding terminals. Along the first direction X, the three second bonding terminals 22 located to the right of the first bonding terminal 21 can transmit the third clock signal CK3, the second clock signal CK2, and the first clock signal CK1 in sequence from left to right. In this arrangement, the second bonding terminals 22 on the display substrate are symmetrically arranged, which allows the display partition 101 to be connected to the corresponding clock signal terminal nearby, facilitating wiring. Furthermore, only six second bonding terminals 22 are needed to control the display partition 101 on the entire display substrate, reducing the size of the bonding area 200 along the first direction X and helping to save costs. In other embodiments, an appropriate number of clock signals and the number and distribution of the second bonding terminals 22 corresponding to each clock signal can be set as needed, and this disclosure does not limit this.

[0063] In an exemplary implementation, such as Figure 3 As shown, a single first bonding terminal 21 can be connected to three switch units 102, and a single switch unit 102 can be connected to at least one display partition 101. Figure 3To clearly illustrate the connection relationships, each switch unit 102 is shown connected to one display partition 101. In practical applications, the quantity correspondence between the first binding terminal 21 and the switch unit 102, as well as the quantity correspondence between the switch unit 102 and the display partition 101, can be set as needed to adjust the number of display partitions 101 controlled by the first binding terminal 21. This disclosure does not impose any limitations on this.

[0064] Figure 4 This is a schematic diagram of the structure of a display substrate in an exemplary embodiment, still illustrating the connection relationship of some display partitions. Figure 4 and Figure 3 The difference is that, Figure 3 Each switch unit 102 is connected to a single display partition 101, while Figure 4 In this configuration, one portion of the switching unit 102 is connected to a single display partition 101, while another portion of the switching unit 102 is connected to two display partitions 101. Other structural details can be found in the section on... Figure 3 The description will not be repeated here.

[0065] In an exemplary implementation, such as Figure 4 As shown, each switch unit 102 distributed along the first direction X on both sides of the display partition is connected to two different display partitions 101. The number of display partitions 101 connected to switch units 102 at different positions on the display substrate varies, and the connection relationship of the remaining display partitions 101 on the display substrate can be designed as needed. In other embodiments, different switch units 102 can be set to connect to different numbers of display partitions 101; or, different switch units 102 can be set to connect to the same number of display partitions 101, for example, each switch unit 102 can connect to three display partitions 101. When a single switch unit 102 is connected to two or more display partitions 101, the distribution of display partitions 101 connected to the same switch unit 102 on the display area can be adjacent to each other, which can save wiring; or, the distribution of display partitions 101 connected to the same switch unit 102 on the display area can be non-adjacent to each other, which can increase the possibility of dynamic display on the display substrate. Different switch units 102 can be connected to different numbers of display zones 101 distributed in different locations, which allows for more flexible control over the lighting status of different display zones 101. The connection relationship of different display zones 101 within the display area can be selected as needed, enabling the display area to display more patterns and providing more possibilities for vehicle headlight design.

[0066] Figure 5This is a schematic diagram of the circuit principle of a single first bonding terminal driving three display zones in an exemplary embodiment. The explanation will take the control of one display zone by a single switching unit as an example. Figure 5 The first bonding terminal is connected to the first power line VDD, enabling the transmission of drive signals from VDD to the corresponding display partitions. Dashed boxes A, B, and C represent different display partitions. Each display partition contains a 2T1C drive circuit. Display partitions A, B, and C are connected to different switching units, each including a third transistor T3. The gate of the third transistor T3 can be connected to the corresponding clock signal CK, the first electrode of the third transistor T3 can be connected to the first bonding terminal, and the second electrode of the third transistor T3 can be connected to the data line within the corresponding display partition. Under the control of clock signal CK1, the third transistor T3 is turned on, and the drive signal from the first bonding terminal (i.e., the drive current of the first power line VDD) enters display partition A, illuminating the OLED element within it. Similarly, under the control of clock signals CK2 and CK3, display partitions B and C can be illuminated. By using different clock signals, the on and off states of different third transistors T3 can be controlled, thereby controlling the illumination of different display partitions and enabling a single first bonding terminal to drive three display partitions. In other embodiments, a single third transistor T3 may be connected to two or more display partitions, and a single first bonding terminal may drive more display partitions; this disclosure does not limit this.

[0067] Figure 6 This is a cross-sectional view of the display substrate in an exemplary embodiment, illustrating the structure of a display partition. For example... Figure 6 As shown, the display substrate located in the display area includes: a substrate 20 and a light-emitting structure layer disposed on the substrate 20. Figure 6 The following example illustrates the concept of a light-emitting structure layer comprising a single light-emitting element. Figure 6 As shown, the substrate 20 includes a substrate 10 and a driving structure layer 102 disposed on the substrate 10. The driving structure layer 102 includes a plurality of driving circuits and a plurality of switching units. At least one driving circuit includes a plurality of transistors and at least one storage capacitor, and at least one switching unit includes a third transistor. A first insulating layer 11, a second insulating layer 13, a third insulating layer 15, and a fourth insulating layer 16 are disposed between the film layers of the driving circuits. Figure 6The image shows a third transistor and a storage capacitor within a driving circuit. The third transistor may include an active layer 12, a gate electrode 14, a source electrode 17, and a drain electrode 18. A first insulating layer 11 is disposed between the substrate 10 and the active layer 12, a second insulating layer 13 is disposed between the active layer 12 and the gate electrode 14, and a third insulating layer 15 and a fourth insulating layer 16 are sequentially disposed between the gate electrode 14 and the source electrode 17 and drain electrode 18. The gate electrode 14 can be connected to a second bonding terminal, the source electrode 17 can be connected to a first bonding terminal, and the drain electrode 18 can be connected to a data signal line of a display partition. The storage capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first capacitor electrode 41 is disposed on the second insulating layer 13, the second capacitor electrode 42 is disposed on the third insulating layer 15, and the third insulating layer 15 is disposed between the first capacitor electrode 41 and the second capacitor electrode 42. A planarization layer 103 is disposed on the driving structure layer 102, and a light-emitting structure layer is disposed on the planarization layer 103. The light-emitting structure layer includes a pixel definition layer 6 and a light-emitting element 7. The light-emitting element 7 includes an anode 71, an organic light-emitting layer 72, and a cathode 73 disposed sequentially. An opening region of the pixel definition layer 6 exposes the surface of the anode 71. The organic light-emitting layer 72 is formed within the opening region and connected to the anode 71. A portion of the cathode 73 is connected to the organic light-emitting layer 72. The anode 71 can be connected to one terminal of a driving transistor (not shown) in the driving circuit, and the cathode 73 can be connected to a second power line VSS (not shown).

[0068] In an exemplary embodiment, an encapsulation layer 9 may be provided on the side of the cathode 73 away from the substrate 10. An adhesive layer 8 may be provided on the side of the cathode 73 close to the encapsulation layer 9. The orthographic projection of the adhesive layer 8 on the substrate 20 covers the orthographic projection of the cathode 73 on the substrate 20. The adhesive layer 8 can tightly bond the encapsulation layer 9 and the light-emitting element 7, which helps to obtain a better encapsulation effect.

[0069] The structure of the display substrate of this disclosure is illustrated below through an example of the display substrate fabrication process. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0070] The following describes the preparation of such... Figure 6 The following explanation uses the display substrate shown as an example:

[0071] (1) The substrate 10 is prepared on a glass substrate. In this disclosure, the material of the substrate 10 can be selected as needed, for example, the substrate 10 can be a flexible substrate or a rigid substrate.

[0072] (2) A driving structure layer 102 pattern is formed on the substrate 10. In an exemplary embodiment, the driving structure layer 102 may include transistors and storage capacitors constituting a driving circuit, and a third transistor constituting a switching unit. In an exemplary embodiment, the fabrication process of the driving structure layer 102 may include:

[0073] A first insulating film and an active layer film are sequentially deposited on a substrate 10. The active layer film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, and an active layer pattern disposed on the first insulating layer 11. The active layer pattern includes at least an active layer 12.

[0074] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer 13 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 13. The first gate metal layer pattern includes at least a gate electrode 14 and a first capacitor electrode 41.

[0075] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 15 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 15. The second gate metal layer pattern includes at least a second capacitor electrode 42, and the position of the second capacitor electrode 42 corresponds to the position of the first capacitor electrode 41.

[0076] Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned using a patterning process to form a pattern of the fourth insulating layer 16 covering the second gate metal layer. Two first vias are formed on the fourth insulating layer 16, and the positions of the two first vias correspond to the positions of the two ends of the first active layer 12. The fourth insulating layer 16, the third insulating layer 15, and the second insulating layer 13 in the two first vias are etched away, exposing the surface of the active layer 12.

[0077] Subsequently, a third metal thin film is deposited, and the third metal thin film is patterned by a patterning process to form a source / drain metal layer pattern on the fourth insulating layer 16. The source / drain metal layer pattern includes at least a source electrode 17 and a drain electrode 18. The source electrode 17 and the drain electrode 18 are respectively connected to the active layer 12 through a first via.

[0078] At this point, the driving structure layer 102 pattern is fabricated on the substrate 10. The active layer 12, gate electrode 14, source electrode 17, and drain electrode 18 constitute the third transistor, and the first capacitor electrode 41 and the second capacitor electrode 42 constitute the storage capacitor. In an exemplary embodiment, the third transistor may be a thin film transistor (TFT).

[0079] In an exemplary embodiment, the first, second, third, and fourth insulating films can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The first, second, and third metal films can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The active layer thin film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0080] (3) A planarization layer 103 pattern is formed on the substrate 10. A first planarization film is coated on the substrate 10 on which the aforementioned pattern is formed to form a planarization layer 103 covering the entire substrate.

[0081] In one exemplary embodiment, a second via (not shown) can be formed on the planarization layer 103 by a patterning process. The second via can expose the surface of the drain electrode of the driving transistor (not shown) in the driving circuit to facilitate subsequent connection with the anode of the light-emitting element.

[0082] In one exemplary embodiment, the planarization layer may be prepared using organic materials.

[0083] (4) Forming an anode 71 pattern on the substrate 10. A conductive thin film is deposited on the substrate 10 where the aforementioned pattern is formed, and the conductive thin film is patterned using a patterning process to form the anode 71 pattern. The anode 71 is formed on the planarization layer 103 of the display area. In an exemplary embodiment, it can be connected to the drain electrode of the driving transistor in the driving circuit through a second via on the planarization layer 103.

[0084] In one exemplary embodiment, the conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and the anode may be a transparent or opaque structure.

[0085] (5) A pixel definition layer 6 pattern is formed on the substrate 10. A pixel definition film is coated on the substrate 10 on which the aforementioned pattern is formed. The pixel definition layer 6 pattern is formed by masking, exposure and development processes. An opening area is formed on the pixel definition layer 6. The pixel definition film in the opening area is developed away, exposing the surface of the anode 71. The remaining pixel definition film forms a pixel defining unit. The opening area is between adjacent pixel defining units.

[0086] In one exemplary embodiment, the pixel definition layer may be made of materials such as polyimide, acrylic, or polyethylene terephthalate.

[0087] (6) An organic light-emitting layer 72 is formed on the substrate on which the aforementioned pattern is formed. The organic light-emitting layer 72 pattern is formed on the substrate 10 on which the aforementioned pattern is formed by vapor deposition or inkjet printing. The organic light-emitting layer 72 is formed in the opening area between adjacent pixel defining units and is connected to the anode 71. Since the anode 71 is connected to the drain electrode of the driving transistor, the light emission control of the light-emitting layer 72 is realized.

[0088] In an exemplary embodiment, the organic light-emitting layer 72 may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0089] In an exemplary embodiment, the organic light-emitting layer 72 can be prepared in the following manner:

[0090] First, the hole injection layer, hole transport layer, and electron blocking layer are formed sequentially using an open mask (OPM) evaporation process or an inkjet printing process, thus forming a common layer of the hole injection layer, hole transport layer, and electron blocking layer on the display substrate.

[0091] Subsequently, an open-mask evaporation process or an inkjet printing process is used to form different light-emitting layers on different sub-pixels. The light-emitting layers of adjacent sub-pixels may have a small amount of overlap (e.g., the overlapping portion occupies less than 10% of the area of ​​their respective light-emitting layer patterns) or may be isolated.

[0092] Subsequently, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially formed using an open-mask evaporation process or an inkjet printing process, forming a common layer of the hole blocking layer, electron transport layer, and electron injection layer on the display substrate.

[0093] In an exemplary embodiment, the organic light-emitting layer may include a microcavity conditioning layer, such that the thickness of the organic light-emitting layer between the cathode and the anode meets the design of the microcavity length. In some exemplary embodiments, a hole transport layer, an electron blocking layer, or an electron transport layer may be used as the microcavity conditioning layer, and this disclosure is not limited thereto.

[0094] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, with the doping ratio of the guest material ranging from 1% to 20%. Within this doping ratio range, on the one hand, the host material can effectively transfer exciton energy to the guest material to excite it to emit light; on the other hand, the host material "dilutes" the guest material, effectively improving fluorescence quenching caused by intermolecular collisions and energy-based collisions, thereby increasing luminous efficiency and device lifetime. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., mass percentage. In an exemplary embodiment, the host material and the guest material can be deposited together using a multi-source evaporation process, ensuring uniform dispersion of both materials in the light-emitting layer. The doping ratio can be controlled by adjusting the evaporation rate of the guest material or by controlling the ratio of the evaporation rates of the host material and the guest material during the evaporation process. In an exemplary embodiment, the thickness of the light-emitting layer can be approximately 10 nm to 50 nm.

[0095] In an exemplary embodiment, the hole injection layer may be an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may be a dopant of a p-type dopant with a strong electron-withdrawing system and a hole transport material. In an exemplary embodiment, the thickness of the hole injection layer may be approximately 5 nm to 20 nm.

[0096] In an exemplary embodiment, the hole transport layer can be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent groups can be carbazole, methyl fluorene, spirofluorene, dibenzothiophene, or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer can be approximately 40 nm to 150 nm.

[0097] In an exemplary embodiment, the hole-blocking layer and the electron transport layer can be aromatic heterocyclic compounds, such as imidazole derivatives like benzimidazole derivatives, imidazopyridine derivatives, and benzimidazolephenanthridine derivatives; azine derivatives like pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure such as quinoline derivatives, isoquinoline derivatives, and phenanthreneroline derivatives (including compounds with phosphine oxide substituents on the heterocycle). In an exemplary embodiment, the thickness of the hole-blocking layer can be approximately 5 nm to 15 nm, and the thickness of the electron transport layer can be approximately 20 nm to 50 nm.

[0098] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or a metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be approximately 0.5 nm to 2 nm.

[0099] (7) A cathode 73 is formed on the substrate 10 on which the aforementioned pattern is formed. The cathode 73 pattern is formed on the substrate 10 on which the aforementioned pattern is formed by vapor deposition using an open mask. The cathode 73 covers the pixel definition layer 6, and a portion of the cathode 73 is connected to the organic light-emitting layer 72, thereby enabling the organic light-emitting layer 72 to be simultaneously connected to both the anode 71 and the cathode 73.

[0100] In an exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the aforementioned metals.

[0101] (8) An adhesive layer 8 and an encapsulation layer 9 are formed on the substrate 10 on which the aforementioned pattern is formed. Adhesive is coated on the substrate 10 on which the aforementioned pattern is formed to form an adhesive layer 8. The adhesive layer 8 covers the light-emitting element 7.

[0102] Subsequently, an encapsulation layer 9 is formed on the substrate 10 on which the aforementioned pattern is formed. In an exemplary embodiment, the preparation process of the encapsulation layer 9 may be as follows: on the substrate 10 on which the aforementioned pattern is formed, a first encapsulation film is first deposited using an open mask in a deposition manner to form a first layer pattern; then, a second encapsulation material is printed using an inkjet printing process using an open mask to form a second layer pattern; and finally, a third encapsulation film is deposited using an open mask in a deposition manner to form a third layer pattern. Thus, the encapsulation layer pattern is completed. Other structures may also be used for the encapsulation layer 9, which are not limited herein.

[0103] In an exemplary embodiment, the first and third encapsulation films can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. They ensure that external water and oxygen cannot enter the light-emitting element, and the deposition method can be chemical vapor deposition (CVD) or atomic layer deposition (ALD). The second encapsulation film can be made of organic materials, such as resin, and serves to coat the various film layers of the display substrate to improve structural stability and flatness.

[0104] After the above preparation, the structure of the obtained display substrate is as follows: Figure 6 As shown. The display substrate may also include other film layer structures, such as protective layers, which can be fabricated according to actual needs, and will not be elaborated here. During the formation... Figure 6 After the structure shown, the glass substrate can be peeled off.

[0105] Based on the inventive concept of the foregoing embodiments, this invention also provides a display device, which includes a display substrate using the foregoing embodiments. The display device can be any product or component with display function, such as a vehicle headlight, monitor, digital photo frame, or navigator.

[0106] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: A display area and a bonding area located on one side of the display area, the bonding area and the display area being disposed along a second direction, the bonding area including a plurality of bonding terminals arranged along a first direction, the first direction intersecting the second direction; The display area includes multiple display zones arranged in an array; The bonding area includes multiple bonding terminals, which are connected to a flexible printed circuit board. The flexible printed circuit board is connected to a driver chip, and the display substrate receives external signals through the multiple bonding terminals. The display substrate also includes at least two switching units; The plurality of bonding terminals include a first bonding terminal and at least two second bonding terminals. The first bonding terminal is configured to transmit a drive signal from a first power line, the drive signal being a current signal. The second bonding terminals are configured to transmit a clock signal, the clock signal being used to control the switching unit to be turned on or off. In the first direction, the at least two second bonding terminals are located on both sides of the first bonding terminal; The bonding terminal is connected to the switching unit, and the switching unit is connected to at least two of the display zones; or, the bonding terminal is connected to at least two of the switching units, and the switching unit is connected to at least one of the display zones. The switching unit is configured to allow a drive signal to enter the display partition under the control of the bonding terminal, and the drive signal is used to drive the display partition to display. The switching unit includes a third transistor, the gate of which is connected to the second bonding terminal, the first electrode of which is connected to the first bonding terminal, and the second electrode of which is connected to the display partition; The switching unit is connected to the first bonding terminal and the second bonding terminal, and is configured to allow a drive signal from the first bonding terminal to enter the display partition under the control of the second bonding terminal. The first bonding terminal is connected to the multiple display partitions through multiple third transistors to control the multiple display partitions to display.

2. The display substrate according to claim 1, characterized in that, A single second bonding terminal is connected to at least two of the switch units.

3. The display substrate according to claim 1, characterized in that, The display partition includes a driving circuit and a light-emitting element. The driving circuit is connected to the scan signal line and the data signal line and is configured to drive the light-emitting element to emit light. The second electrode of the third transistor is connected to the data signal line of the display partition.

4. The display substrate according to claim 1, characterized in that, In a first direction, the at least two second binding terminals are located on both sides of the binding area; the first direction is the arrangement direction of the plurality of binding terminals.

5. The display substrate according to claim 4, characterized in that, The clock signal includes a first clock signal, a second clock signal, and a third clock signal; the second bonding terminal includes a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, wherein the first clock signal terminal is used to transmit the first clock signal, the second clock signal terminal is used to transmit the second clock signal, and the third clock signal terminal is used to transmit the third clock signal.

6. The display substrate according to claim 5, characterized in that, In a first direction, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal are symmetrically distributed along the center line of the display substrate.

7. The display substrate according to claim 3, characterized in that, The display substrate includes a substrate and a light-emitting structure layer disposed on the substrate. The substrate includes a driving structure layer, and the switching unit and the driving circuit are disposed on the driving structure layer.

8. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 7.

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