A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, which comprises the following steps: sequentially depositing a first blocking layer and a first dielectric layer on a storage area of a metal substrate; etching a first through hole in the first blocking layer and the first dielectric layer of the storage area, depositing a lower electrode in the first through hole, and performing a planarization treatment to make the upper surface of the lower electrode and the upper surface of the first dielectric layer flush; sequentially depositing a resistance change layer and a second blocking layer on the surface of the first dielectric layer and the lower electrode of the storage area; depositing a second dielectric layer on the second blocking layer of the storage area; etching a second through hole and a wire slot which are communicated in the layers above the resistance change layer of the storage area, the bottom of the second through hole being communicated with the resistance change layer, and the top of the second through hole being communicated with the wire slot; sequentially depositing an oxygen grabbing layer and an upper electrode in the second through hole and the wire slot, and then filling a metal wire. The problems of the existing stacked resistance change structure profile easy to deform and metal wire bridging can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Among existing technologies, resistive random access memory (RRAM) is one of the most promising next-generation non-volatile memories. Compared with traditional floating gate flash memory, it has significant advantages in terms of device structure, speed, scalability, and three-dimensional integration potential.

[0003] The basic structure of a Resistive Random Access Array (RRAM) is a metal-insulator-metal (MIM) structure, mainly consisting of a bottom electrode, a resistive switching layer, and a top electrode. The resistive switching layer is made of various oxide thin film materials and can reversibly switch between different resistance states under the influence of applied voltage, current, or other electrical signals. This reversible switching is mostly achieved through the formation and breakage of conductive filaments.

[0004] Currently, the manufacturing method of MIM structures involves sequentially depositing all thin films and then etching them using a photomask to obtain the resistive switching structure (R) (called a stacked resistive switching structure). The size of the resistive switching structure is defined by the photomask. When miniaturizing the resistive switching structure, if the photomask thickness is insufficient or excessive, it can easily cause problems such as the R profile becoming tapered, array edge collapse, or metal wire bridging. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method for manufacturing the same, in order to at least solve the above-mentioned technical problems.

[0006] The first aspect of the present invention provides a method for manufacturing a semiconductor device, comprising: A first barrier layer and a first dielectric layer are sequentially deposited in the storage region of a metal substrate; A first via is etched in the first barrier layer and the first dielectric layer of the storage region, and a lower electrode is deposited in the first via. A planarization process is performed to make the upper surface of the lower electrode flush with the upper surface of the first dielectric layer. A resistive switching layer and a second barrier layer are sequentially deposited on the surfaces of the first dielectric layer and the lower electrode in the storage region; A second dielectric layer is deposited on the second barrier layer of the storage region; A second via and a groove are etched in each layer above the resistive switching layer in the storage area. The bottom of the second via is connected to the resistive switching layer, and the top of the second via is connected to the groove. After depositing an oxygen-binding layer and an upper electrode sequentially in the second through-hole and the groove, a metal wire is filled in.

[0007] The metal substrate further includes logic regions, and correspondingly, While sequentially depositing a first barrier layer and a first dielectric layer in the storage region of the metal substrate, the method further includes: sequentially depositing a first barrier layer and a first dielectric layer in the logic region of the metal substrate.

[0008] The method further includes, while depositing a resistive switching layer and a second barrier layer sequentially on the upper surface of the first dielectric layer and the lower electrode in the storage region, depositing a resistive switching layer and a second barrier layer sequentially on the first dielectric layer in the logic region.

[0009] The method further includes, before depositing the second dielectric layer on the second barrier layer of the storage region, removing the resistive switching layer and the second barrier layer of the logic region. Accordingly, while depositing a second dielectric layer on the second barrier layer of the storage region, the method further includes depositing a second dielectric layer on the first dielectric layer of the logic region.

[0010] The method further includes, before depositing the second dielectric layer on the second barrier layer of the storage region, removing the first dielectric layer, the resistive switching layer and the second barrier layer of the logic region. Accordingly, while depositing a second dielectric layer on the second barrier layer of the storage region, the method also includes depositing a second dielectric layer on the first barrier layer of the logic region.

[0011] The method further includes, while etching interconnected second vias and grooves in each layer above the resistive switching layer of the storage region: Second vias and grooves are etched in each layer above the metal substrate of the logic region.

[0012] The method further includes, while depositing the oxygen-trapping layer and the upper electrode sequentially in the second through-hole and groove of the storage area, the following: An oxygen-binding layer and an upper electrode are sequentially deposited in the second via and the groove in the logic region.

[0013] A second aspect of the present invention provides a semiconductor device, the semiconductor device including a storage region, the storage region comprising: Metal substrate; A first barrier layer located on the metal substrate, and a first dielectric layer located on the first barrier layer; The first via, located in the first barrier layer and the first dielectric layer, is filled with the lower electrode of the first via; A resistive switching layer located above the lower electrode; A second barrier layer located above the resistive switching layer, and a second dielectric layer located above the second barrier layer; The second via and the wire groove are located in the second barrier layer and the second dielectric layer, with the bottom of the second via communicating with the resistive switching layer and the top of the second via communicating with the wire groove. An oxygen-binding layer and an upper electrode are stacked to cover the bottom of the second through hole and the sidewalls of the second through hole and the wire groove; Metal wires filling the second through hole and the groove.

[0014] The second through hole overlaps with the orthographic projection of the first through hole onto the metal substrate.

[0015] The semiconductor device further includes a logic region, which includes: Metal substrate; A first barrier layer located on the metal substrate, a dielectric layer located on the first barrier layer, the dielectric layer comprising the first dielectric layer and the second dielectric layer, or the dielectric layer being the second dielectric layer; The second via and the groove are located in the first barrier layer and the dielectric layer; An oxygen-binding layer and an upper electrode are stacked and cover the bottom of the second through hole and the sidewalls of the second through hole and the wire groove. Metal wires filling the second through hole and the groove.

[0016] In this disclosure, the size of the resistive switching structure is determined by the overlapping area of ​​the orthographic projections of the second via and the first via on the metal substrate. Therefore, the size of the resistive switching structure depends on the dimensions of the second via and the first via. Since the resistive switching structure of this disclosure first deposits a second barrier layer in the storage region, then forms a second dielectric layer, and forms a second via, deposits an oxide-binding layer and an upper electrode in the second barrier layer and the second dielectric layer, the first-formed second dielectric layer and the second barrier layer provide a strong support for the resistive switching structure. Moreover, the second barrier layer and the second dielectric layer are deposited on a plane, which does not produce voids and completely isolates adjacent resistive switching structures. Compared with the manufacturing method of stacked resistive switching structures, this method can avoid problems such as the contour tapering, array edge collapse and metal wire bridging of existing stacked resistive switching structures. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0018] Figure 1 A schematic diagram of the first barrier layer and the first dielectric layer in an example of this disclosure is shown; Figure 2 A schematic diagram of the lower electrode in an example of this disclosure is shown; Figure 3 An example of this disclosure shows a resistive switching layer and a second barrier layer; Figure 4 A schematic diagram of the logical region structure is shown in one example of this disclosure; Figure 5 A schematic diagram of the logical region structure is shown in another example of this disclosure; Figure 6 A schematic diagram of the second dielectric layer is shown in one example of this disclosure; Figure 7 A schematic diagram of the second dielectric layer is shown in another example of this disclosure; Figure 8 A schematic diagram of a second through hole and groove is shown in one example of this disclosure; Figure 9 A schematic diagram of an oxygen-binding layer, an upper electrode, and a metal wire is shown in one example of this disclosure; Figure 10 A schematic diagram of a semiconductor structure provided in this disclosure is shown. Detailed Implementation

[0019] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] This disclosure provides an example of a method for manufacturing a semiconductor device, which utilizes two embedded vias to respectively carry upper and lower electrodes. Thus, the size of the resistive switching structure can be defined by controlling the size of the two vias. Based on this, the resistive switching structure can be miniaturized by reducing the size of the vias.

[0023] In the examples disclosed herein, the fabrication of semiconductor devices is described in terms of a memory region (array) and a logic region (logic), wherein the resistive switching structure is located in the memory region (array).

[0024] The following description, in conjunction with the accompanying drawings, illustrates a method for manufacturing a semiconductor device according to an example of this disclosure. The method includes: Step 101: Sequentially deposit a first barrier layer 20 and a first dielectric layer 30 in the storage region of the metal substrate 10.

[0025] like Figure 1 As shown, the left image represents the storage region, and the right image represents the logic region. While depositing the first barrier layer and the first dielectric layer in the storage region of the metal substrate, the first barrier layer and the first dielectric layer can also be deposited sequentially in the logic region.

[0026] The first barrier layer 20 can be made of nitride-doped carbon (NDC), which prevents the metal from the metal substrate 10 from diffusing into the first dielectric layer 30 and affecting device performance. The first dielectric layer 30 can be made of oxide.

[0027] Step 102: Etch a first via 01 in the first barrier layer 20 and the first dielectric layer 30 of the storage region, deposit a lower electrode 40 in the first via 01, and perform planarization to make the upper surface of the lower electrode 40 flush with the first dielectric layer 30, such as... Figure 2 As shown.

[0028] In this step, the etching of the first via 01 and the deposition of the lower electrode 40 are only for the storage region; therefore, the existing layers in the logic region remain unchanged.

[0029] Step 103: Sequentially deposit a resistive switching layer 50 and a second barrier layer 60 on the surfaces of the first dielectric layer 30 and the lower electrode 40 in the storage region, such as... Figure 3 As shown.

[0030] Simultaneously, a resistive switching layer 50 and a second barrier layer 60 are also sequentially deposited on the first dielectric layer 30 of the logic region, such as... Figure 3 As shown.

[0031] Since only the resistive switching structure needs to be formed in the storage area, in one example of this disclosure, the resistive switching layer 50 and the second barrier layer 60 in the logic area can be removed, such as... Figure 4 As shown.

[0032] In another example, the first dielectric layer 30 of the logic region can also be removed, such as... Figure 5 As shown. Because a dielectric layer needs to be deposited in the subsequent process, the two dielectric layers of the logic region are adjacent. Since the two dielectric layers are not deposited at the same time, differences in materials and processes may cause the dielectric constants of the two dielectric layers to be inconsistent, affecting the device performance. Therefore, when removing the resistive switching layer 50 and the second barrier layer 60 of the logic region, the first dielectric layer 30 can also be removed at the same time.

[0033] And such Figure 4 Retaining the first dielectric layer 30 minimizes the height difference between the logic region and the memory region. Compared to removing the first dielectric layer 30, this prevents the etching process window of the logic region from becoming smaller. Furthermore, the second barrier layer 60 of the memory region can also be used as an etching stop layer, further reducing the height difference between the logic region and the memory region and increasing the etching process window of the logic region.

[0034] The resistive switching layer 50 can be made of filtered metal oxide (TMO) and can be deposited using the ALD growth method.

[0035] The material of the second barrier layer 60 can be any one of NDC, nitride, and aluminum oxide (AlOx).

[0036] Step 104: Deposit a second dielectric layer 70 on the second barrier layer 60 of the storage region.

[0037] At the same time, corresponding to Figure 4 The structure of the logic region shown allows for the deposition of a second dielectric layer 70 on the first dielectric layer 30 of the logic region, such as... Figure 6 As shown; corresponding to Figure 5 The structure of the logic region shown allows for the deposition of a second dielectric layer 70 on the first barrier layer 20 of the logic region, such as... Figure 7 As shown.

[0038] The material of the second dielectric layer 70 can be an ultra-low dielectric constant (ULK) material.

[0039] like Figure 6 and Figure 7As shown, after the second dielectric layer 70 is deposited in the memory region and the logic region, planarization is performed (for example, by using chemical mechanical polishing (CMP)) to make the overall structure of the memory region and the logic region highly consistent, thus ensuring that the etching process windows of the two regions are consistent in the subsequent process.

[0040] Step 105: Etch a connected second via 02 and a groove 03 in each layer above the resistive switching layer 50 in the storage area. The bottom of the second via 02 is connected to the resistive switching layer 50, and the top of the second via 02 is connected to the groove 03.

[0041] like Figure 8 As shown, a second via 02 and a groove 03 are etched in the second barrier layer 60 and the second dielectric layer 70 (i.e., each layer above the resistive switching layer 50) of the storage region.

[0042] Simultaneously, second vias 02 and grooves 03 are etched in each layer above the metal substrate 10 of the logic region. Corresponding to Figure 6 The structure shown involves etching a second via 02 and a groove 03 into the first barrier layer 20, the first dielectric layer 30, and the second dielectric layer 70, as follows: Figure 8 As shown; corresponding to Figure 7 The structure shown is such that a second through-hole 02 and a groove 03 are etched in the first barrier layer 20 and the second dielectric layer 70.

[0043] The second through hole 02 is located directly above the lower electrode 40, meaning that the orthogonal projections of the second through hole 02 and the lower electrode 40 on the metal substrate overlap.

[0044] Step 106: After depositing the oxygen-binding layer 80 and the upper electrode 90 in the second through hole 02 and the groove 03 in the storage area, fill them with metal wire material.

[0045] Simultaneously, after depositing an oxygen-binding layer 80 and an upper electrode 90 in the second via 02 and the groove 03 of the logic region, metal wire material is filled in.

[0046] based on Figure 8 The resulting structure involves first depositing an oxygen-binding layer 80, followed by the deposition of an upper electrode 90. The oxygen-binding layer 80 can be made of Ti or Ta, and is deposited using PVD (Physical Vapor Deposition) technology. Figure 8 An oxygen-binding layer 80 grows on the structure shown, as Figure 9As shown, the oxide-binding layer 80 covers the surface of the second dielectric layer 70, the bottom of the second via 02, and the sidewalls of the second via 02 and the groove 03; the upper electrode material can be TaN, and an upper electrode 90 is grown conformally on the oxide-binding layer 80 using ALD (atomic layer deposition) technology, as shown. Figure 9 As shown. Accordingly, after the upper electrode 90 is deposited, the second through hole 02 and part of the groove 03 form a space, which is used to fill the metal material as a metal wire. The metal material (e.g., copper) can be filled by electroplating.

[0047] Thus, in the storage region, the lower electrode 40, the resistive switching layer 50, the oxygen-binding layer 80 at the bottom of the second through-hole 02, and the upper electrode 90 constitute the resistive switching structure disclosed herein.

[0048] The size of the resistive switching structure is determined by the size of the overlapping area of ​​the upper electrode 90 and lower electrode 40 projected onto the metal substrate at the bottom of the second via 02. The size of the upper electrode 90 at the bottom of the second via 02 is determined by the size of the second via 02 and the slot 03, while the size of the lower electrode 40 is determined by the size of the first via 01. Preferably, as follows... Figure 8 As shown, L2 is the cross-sectional dimension of the slot 03 and the second via 02. L2 can be set using the minimum dimension of the metal wire. The cross-sectional dimension L1 of the first via 01 can be the minimum dimension achievable by the manufacturing process, thus achieving miniaturization of the resistive switching structure. In addition, the distance between each two adjacent first vias 01 and the distance between each two adjacent second vias 02 (slot 03) can also be the minimum dimension achievable by the manufacturing process, thereby improving the integration density of the semiconductor device.

[0049] In the logic region, both the oxygen-binding layer 80 and the upper electrode 90 are barrier layers used to prevent the metal filled in the second via 02 and the slot 03 from diffusing to the surrounding area.

[0050] based on Figure 9 The structure shown, after being filled with metal material, undergoes a planarization process. This involves removing the oxide-binding layer 80, the upper electrode 90, and the metal material outside the second through-hole 02 and the wire groove 03, making the surfaces of the second dielectric layer 70, the oxide-binding layer 80, the upper electrode 90, and the metal wire flush. Figure 10 As shown.

[0051] The following is based on Figure 10 The following provides further explanation of the semiconductor devices provided in this disclosure.

[0052] like Figure 10 As shown, the semiconductor device provided in this disclosure includes a memory region, which includes: Metal substrate 10; A first barrier layer 20 is located on the metal substrate 10, and a first dielectric layer 30 is located on the first barrier layer 20. The first through-hole 01 located in the first barrier layer 20 and the first dielectric layer 30 is filled with the lower electrode 04; wherein there are multiple lower electrodes 40, and each two adjacent lower electrodes 40 are isolated by the first dielectric layer 30. The resistive switching layer 50 is located above the lower electrode 40. The resistive switching layer 50 is a connected region. In addition to covering the lower electrode 40, it also covers the first dielectric layer 30. It can be seen that the resistive switching layer 50 is not etched or cut in this disclosure. This can prevent the resistive switching layer 50 from being damaged, avoid affecting the formation of conductive filaments, and ensure the performance of the resistive switching structure. A second barrier layer 60 is located above the resistive switching layer 50, and a second dielectric layer 70 is located above the second barrier layer 60; The second through hole 02 and the wire groove 03 are located in the second barrier layer 60 and the second dielectric layer 70. The bottom of the second through hole 02 is connected to the resistive switching layer 50, and the top of the second through hole 02 is connected to the wire groove 03. An oxygen-binding layer 80 and an upper electrode 90 are stacked to cover the bottom of the second through hole 02 and the sidewalls of the second through hole 02 and the groove 03. Metal wires filling the second through hole and the wire groove.

[0053] The orthographic projections of the second via 02 and the first via 01 on the metal substrate 10 overlap (i.e., the second via 02 is located directly above the first via 01). Thus, the lower electrode 40, the resistive switching layer 50, the oxide-binding layer 80 at the bottom of the second via 02, and the upper electrode 90 form a resistive switching structure. It can be seen that the resistive switching structures are isolated from each other by the dielectric layers (the first dielectric layer and the second dielectric layer), which can avoid the void formed by first isolating and then filling the dielectric material between existing stacked resistive switching structures, thereby avoiding the problem of metal wire bridging. Moreover, the dielectric layer provides a solid support for the resistive switching structure.

[0054] Furthermore, the size of the resistive switching structure in this disclosure is determined by the area of ​​the overlapping orthographic projections of the second via 02 and the first via 01 on the metal substrate 10. Therefore, the size of the resistive switching structure in this disclosure depends on the dimensions of the second via 02 and the first via 01.

[0055] In the prior art, the stacked resistive switching structure is obtained by etching with a photomask after all the thin films are deposited in sequence, and then a dielectric layer is filled between the resistive switching structures. Therefore, the outline of the stacked resistive switching structure obtained by etching is prone to becoming conical and the array edge is prone to collapse. However, the resistive switching structure disclosed in this invention consists of a lower electrode 40 in the first via 01, a middle resistive switching layer 50, and an oxide-binding layer 80 and an upper electrode 90 in the second via 02. It is a sandwich structure that does not require etching and can avoid the problems of the outline of the stacked resistive switching structure becoming conical and the array edge being prone to collapse.

[0056] like Figure 10 As shown, the semiconductor device provided in this disclosure further includes a logic region, which includes: Metal substrate 10; A first barrier layer 20 is located on the metal substrate 10, and a dielectric layer is located on the first barrier layer 20. The dielectric layer includes a first dielectric layer 30 and a second dielectric layer 70 (corresponding to...). Figure 6 Alternatively, the dielectric layer is a second dielectric layer 70 (corresponding to...). Figure 7 ); The second through-hole 02 and the wire groove 03 are located in the first barrier layer 20 and the dielectric layer; An oxygen-binding layer 80 and an upper electrode 90 are stacked to cover the bottom of the second through hole 02 and the sidewalls of the second through hole 02 and the wire groove 03. Metal wires filling the second through hole and the wire groove.

[0057] Here, in the logic region, the oxide-binding layer 80 and the top electrode 90 function to prevent the metal from the metal wires from diffusing outwards and affecting device performance. In the storage region, the oxide-binding layer 80 and the top electrode 90, in addition to being part of the resistive switching structure, also have the function of preventing the metal from the metal wires from diffusing outwards.

[0058] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0059] The foregoing description is intended to enable any person skilled in the art to implement and use the contents of this disclosure, and is provided in the context of a particular application and its requirements. Furthermore, the foregoing description of embodiments of this disclosure is given for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit this disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Moreover, the foregoing discussion of embodiments is not intended to limit this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown, but will be given the widest scope consistent with the principles and features disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first barrier layer and a first dielectric layer are sequentially deposited in the storage region of a metal substrate; A first via is etched in the first barrier layer and the first dielectric layer of the storage region, and a lower electrode is deposited in the first via. A planarization process is performed to make the upper surface of the lower electrode flush with the upper surface of the first dielectric layer. A resistive switching layer and a second barrier layer are sequentially deposited on the surfaces of the first dielectric layer and the lower electrode in the storage region; A second dielectric layer is deposited on the second barrier layer of the storage region; A second via and a groove are etched in each layer above the resistive switching layer in the storage area. The bottom of the second via is connected to the resistive switching layer, and the top of the second via is connected to the groove. After depositing an oxygen-binding layer and an upper electrode sequentially in the second through-hole and the groove, a metal wire is filled in.

2. The method according to claim 1, characterized in that, The metal substrate also includes logic regions, and correspondingly, While sequentially depositing a first barrier layer and a first dielectric layer in the storage region of the metal substrate, the method further includes: sequentially depositing a first barrier layer and a first dielectric layer in the logic region of the metal substrate.

3. The method according to claim 2, characterized in that, While depositing a resistive switching layer and a second barrier layer sequentially on the upper surface of the first dielectric layer and the lower electrode in the storage region, the method further includes: depositing a resistive switching layer and a second barrier layer sequentially on the first dielectric layer in the logic region.

4. The method according to claim 3, characterized in that, Before depositing the second dielectric layer on the second barrier layer of the storage region, the method further includes: removing the resistive switching layer and the second barrier layer of the logic region; Accordingly, while depositing a second dielectric layer on the second barrier layer of the storage region, the method further includes depositing a second dielectric layer on the first dielectric layer of the logic region.

5. The method according to claim 3, characterized in that, Before depositing the second dielectric layer on the second barrier layer of the storage region, the method further includes: removing the first dielectric layer, the resistive switching layer and the second barrier layer of the logic region; Accordingly, while depositing a second dielectric layer on the second barrier layer of the storage region, the method also includes depositing a second dielectric layer on the first barrier layer of the logic region.

6. The method according to claim 4 or 5, characterized in that, While etching interconnected second vias and grooves in each layer above the resistive switching layer in the storage region, the method also includes: Second vias and grooves are etched in each layer above the metal substrate of the logic region.

7. The method according to claim 6, characterized in that, While sequentially depositing the oxygen-binding layer and the upper electrode in the second through-hole and groove of the storage area, the method also includes: An oxygen-binding layer and an upper electrode are sequentially deposited in the second via and the groove in the logic region.

8. A semiconductor device, characterized in that, The semiconductor device includes a storage region, the storage region comprising: Metal substrate; A first barrier layer located on the metal substrate, and a first dielectric layer located on the first barrier layer; The first via, located in the first barrier layer and the first dielectric layer, is filled with the lower electrode of the first via; A resistive switching layer located above the lower electrode; A second barrier layer located above the resistive switching layer, and a second dielectric layer located above the second barrier layer; The second via and the wire groove are located in the second barrier layer and the second dielectric layer, with the bottom of the second via communicating with the resistive switching layer and the top of the second via communicating with the wire groove. An oxygen-binding layer and an upper electrode are stacked to cover the bottom of the second through hole and the sidewalls of the second through hole and the wire groove; Metal wires filling the second through hole and the groove; The semiconductor device further includes a logic region, the logic region comprising: Metal substrate; A first barrier layer located on the metal substrate, a dielectric layer located on the first barrier layer, the dielectric layer comprising the first dielectric layer and the second dielectric layer, or the dielectric layer being the second dielectric layer; The second via and the groove are located in the first barrier layer and the dielectric layer; An oxygen-binding layer and an upper electrode are stacked and cover the bottom of the second through hole and the sidewalls of the second through hole and the wire groove. Metal wires filling the second through hole and the groove.

9. The semiconductor device according to claim 8, characterized in that, The second through hole overlaps with the orthographic projection of the first through hole onto the metal substrate.

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