Systems and methods for adaptive power reuse

Abstract

A system-on-a-chip (SOC) includes: a first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexer disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to the first memory block and the second memory block; and an enable logic circuit system disposed on the periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to a control terminal of the first power multiplexer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Indian Provisional Patent Application No. 202041032888, filed on July 31, 2020, the entire contents of which are fully set forth below and used for all applicable purposes, and are incorporated herein by reference. Technical Field

[0003] This application relates generally to power reuse, and more specifically, to reducing power usage in power delivery networks that employ power reuse. Background Technology

[0004] Traditional computing devices (such as smartphones, tablets, etc.) may include a System-on-a-Chip (SOC), which has a processor and other operating circuitry. The SOC can receive power from a battery, so traditional designs balance SOC performance and power usage to provide an ideal user experience while requiring as little battery charging as possible.

[0005] Power multiplexing is a technique that can be used to save power in certain situations. One way some systems can use power multiplexing to save power is by drooping the power of certain parts of the processing core (using a first power multiplexer and a first power domain) while providing power to other parts of the processing core (using a second power multiplexer and a second power domain). Another way some traditional systems can use power multiplexing is by switching from a first power supply to a second power supply to power the central processing unit (CPU) memory, and adjusting the second power supply to overdrive the CPU memory. This technique saves power by allowing the SOC to selectively increase the voltage at some components without increasing the voltage at others.

[0006] Some power multiplexing architectures may include power multiplexers and their enabling circuitry placed along the periphery of a System-on-a-Chip (SoC). The power multiplexers are coupled to memory blocks within the SoC. In one example, a power multiplexer on the periphery of the SoC can supply power to multiple memory blocks by traversing a power rail from one memory block to the next in series. The series memory block furthest from the power multiplexer experiences a voltage drop that increases quadratically with the number of intermediate memory blocks. In other words, the voltage drop may become unacceptable after only traversing a few memory blocks. There is a need in the art for more efficient power distribution networks (PDNs) experiencing less voltage drop. Summary of the Invention

[0007] Various implementations provide circuitry and techniques for reducing voltage drops in distribution networks (PDNs). In one example, power multiplexers are placed close to memory blocks. For example, power multiplexers can be placed within memory channels and other locations. As a result, power multiplexers can supply power to their respective memory blocks in a manner that reduces or avoids secondary power drops caused by series-connected intermediate memory blocks.

[0008] According to one embodiment, a system-on-a-chip (SOC) includes: a first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexer disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide operating voltages to both the first memory block and the second memory block; and an enable logic circuit system disposed at the periphery of the SOC remote from the first memory block and the second memory block, the enable logic circuit system being coupled to a control terminal of the first power multiplexer.

[0009] According to one embodiment, a method includes: selecting a first power supply as the operating voltage of a first memory block, wherein the first power supply is selected by a first power multiplexer disposed between the first memory block and a second memory block, wherein the selection is controlled by an enabling logic circuit system disposed at the periphery of the system-on-a-chip (SOC) remote from the first memory block and the second memory block; and selecting a second power supply as the operating voltage of the first memory block under the control of the enabling logic circuit system.

[0010] According to one embodiment, a semiconductor chip includes: a first memory block and a second memory block; a component for selecting between a first power supply and a second power supply, wherein the selection component is disposed between the first memory block and the second memory block and configured to provide an operating voltage to the first memory block; and a component for controlling the selection component, wherein the control component is disposed on the periphery of the chip away from the first memory block and the second memory block, and the control component is coupled to a control terminal of a transistor of the selection component.

[0011] According to another embodiment, a system-on-a-chip (SOC) includes: a first memory block and a second memory block; processing logic, including a set of processing blocks, the processing logic being configured such that the first memory block and the second memory block are located between the processing logic and the periphery of the SOC, the periphery of the SOC corresponding to a lateral portion of the side of the SOC; an enable logic circuit system disposed at the periphery of the SOC; a first plurality of power multiplexers disposed between the first memory block and the second memory block, the first plurality of power multiplexers being configured to receive an enable signal and a switching voltage from the enable logic circuit system; and a second plurality of power multiplexers disposed between the second memory block and the processing logic, the second plurality of power multiplexers being configured to receive an enable signal and a switching voltage from the enable logic circuit system. Attached Figure Description

[0012] Figure 1 This is a simplified diagram of an example SOC that includes an improved power distribution network (PDN) with power multiplexers placed close to the memory blocks.

[0013] Figure 2 This is a diagram of an example multiplexed circuit system according to one implementation method.

[0014] Figures 3A-3C An example implementation is illustrated, wherein a power multiplexer 310 is disposed within a storage channel between memory blocks.

[0015] Figure 4 This is a diagram of an example power multiplexer according to one implementation.

[0016] Figure 5 This is a diagram of an example system that can be implemented in a SOC according to one implementation method.

[0017] Figure 6 This is a diagram of an example system that can be implemented in a SOC according to one implementation method.

[0018] Figure 7 This is a diagram of an example power multiplexer according to one implementation.

[0019] Figure 8 An example enable logic circuit system block comprising three or four switch blocks is shown according to one embodiment.

[0020] Figure 9 It shows that it can be used with Figure 8 Additional routing and metal layers used in the implementation.

[0021] Figure 10 This is a diagram illustrating an example method adapted according to one implementation method. Detailed Implementation

[0022] The various implementations provided herein include systems and methods for providing power multiplexing to memory blocks with a smaller voltage drop than in other designs. The multiplexing circuitry can be placed closer to the memory blocks, such as in a memory channel (the space between two memory blocks), or otherwise close to either side of the memory blocks, thereby reducing the number of series-powered memory blocks. Reducing the number of series-powered memory blocks reduces the voltage drop from the power multiplexing circuitry to the memory blocks powered through the power multiplexing circuitry system.

[0023] Continuing this example, the system may include a system-on-a-chip (SOC) having a first memory block and a second memory block. Examples of memory blocks include a secondary cache within the processor, but in some implementations any acceptable memory block of random access memory (RAM) or read-only memory (ROM) may be used. The SOC may also include processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other standard units or intellectual property (IP) cores.

[0024] The System-on-Chip (SOC) also includes a first power multiplexer disposed between the first memory block and the second memory block. The first power multiplexer is coupled to a first power rail that provides operating voltages to both the first and second memory blocks. The SOC also includes an enable logic circuitry disposed on its periphery, away from the first and second memory blocks. In this example, the periphery of the SOC includes the space surrounding the physical perimeter of the SOC outside the processing circuitry and the memory blocks, and may include lateral portions of one or more sides of the SOC. The enable logic in this example is coupled to control terminals of the first power multiplexer to control the power multiplexer to select either a first power supply or a second power supply. In other words, the operating voltage is selected from the first and second power supplies according to the enable logic circuitry.

[0025] In one example, the SOC also includes a second power multiplexer disposed between the first memory block and the processing unit and also coupled to the first power rail. In this example, the first power multiplexer and the second power multiplexer are coupled to the first memory block to supply power to the first memory block. In some examples, the first power multiplexer may be one of a plurality of power multiplexers disposed in a memory channel between the first memory block and the second memory block.

[0026] Such exemplary embodiments can place the first power multiplexer adjacent to the first and second memory blocks, thereby allowing the first power multiplexer to power one or both of the first and second memory blocks without any other memory block causing a voltage drop due to the other memory block. In other words, some embodiments may include an electrical connection from the first power multiplexer to any one or both of the first and second memory blocks without any other intermediate memory block causing a voltage drop before voltage is delivered to one or both of the first and second memory blocks.

[0027] In one example, reducing the size of the first power multiplexer makes its placement possible. The size of the first power multiplexer can be reduced by including only the multiplexing circuitry within it and placing the enable logic and other supporting circuitry elsewhere (e.g., at the periphery of the SOC). For example, the SOC may also include a voltage generator that provides a switching voltage operable to turn off the transistors within the multiplexer. The voltage generator can be located at the periphery of the SOC or other suitable locations, such as adjacent to the first memory block. However, in this case, the voltage generator is not arranged within the block of the first power multiplexer. Therefore, the block of the first power multiplexer can be small enough to be placed within a memory channel or between a memory block and a processing unit.

[0028] Therefore, various implementations can include more space-saving power multiplexers, which can be placed in a smaller area (e.g., memory channels). The enable logic circuitry and voltage generator can be placed elsewhere outside the multiplexer itself.

[0029] Various implementations may also include methods. One set of example methods includes selecting a first power source by controlling a power multiplexer. The power multiplexer may include, as described in the examples herein, a power multiplexer that may have a reduced size and be placed in a memory channel or between a memory block and a processing unit. This selection is performed by asserting or de-asserting signals from an enable logic circuitry system located remotely from the power multiplexer. For example, the enable logic circuitry system may be located peripherally to the SOC and decoupled from the power multiplexer via memory blocks, multiple memory blocks, processing units, etc. The method may also include controlling the power multiplexer to select a second power source by asserting or de-asserting signals.

[0030] Various implementations can include advantages over other systems. One advantage includes reduced voltage drop across the power rails supplying the memory block. This advantage can be achieved by placing the power multiplexing circuitry near the memory block to avoid an intermediate voltage drop between the power multiplexing circuitry and the memory block. As a result, because there is no need to compensate for the intermediate voltage drop, the minimum power rail voltage can be reduced while still allowing the desired voltage level. Therefore, power consumption can be reduced in some handheld devices, and battery life can be extended.

[0031] Figure 1 This is a simplified diagram illustrating an example SOC 100 including an improved power distribution network (PDN) with power multiplexers placed near a memory block. The example SOC 100 includes a semiconductor chip with a processing block 106. The processing block 106 may include multiple processing devices, such as a graphics processing unit (GPU), a central processing unit (CPU), a modem unit, a camera unit, etc. In some examples, the SOC may be included within a chip package, mounted on a printed circuit board, and disposed within a portable device such as a smartphone or tablet. However, the scope of implementation is not limited to chips implemented in tablets or smartphones, as other applications are possible.

[0032] Processing block 106 may include a CPU with multiple cores, and one or more of those cores may execute computer-readable code that provides the functionality of an operating system kernel. Such CPU cores may read data from and write data to memory blocks 102-105. Furthermore, the example operating system kernel may include power management software that controls power usage within the SOC 100. For example, the power management software may determine to place one or more CPU cores in an accelerated mode and increase the voltage at one or more locations in memory blocks 102-105 to support the CPU accelerated mode. Similarly, the power management software may determine to place one or more CPU cores in a lower operating mode during normal operation, consistent with power saving. In this case, the power management software may decrease the voltage at one or more locations in memory blocks 102-105. Furthermore, in this example, increasing or decreasing the operating voltage at memory blocks 102-105 may include controlling the power multiplexer 110 to select a higher or lower power supply, consistent with the operating mode.

[0033] Power multiplexers 110 are shown as being located away from the periphery 120, 122 of the SOC 100, but rather distributed close to memory blocks 102-105. For example, some power multiplexers 110 are placed in memory channels between memory blocks 102 and 103, while other power multiplexers are placed in memory channels between memory blocks 102 and 104. In fact, memory blocks 103, 104, and 105 each have power multiplexers arranged around three sides.

[0034] Memory block 110 is positioned between memory block 103 and processing block 106. Memory block 110 is also positioned between memory block 104 and processing block 106, and between memory block 105 and processing block 106. Each power multiplexer 110 serves its respective memory block 102-105 by providing its operating voltage to that memory block without any intermediate voltage drop from another memory block. For example, power multiplexer 110a may provide its operating voltage to memory block 103 without any voltage drop attributable to any other memory block 102, 104, 105. The same applies to each other power multiplexer 110 serving its respective memory blocks 102-105. However, the scope of the implementation does not preclude some memory blocks from being served in any suitable manner by other power multiplexers (not shown).

[0035] SOC 100 also includes an enable logic circuitry block, examples of which are shown as items 124 and 126. The enable logic circuitry block is located in the periphery 120, 122 of SOC 100. The enable logic circuitry block is responsible for controlling the power multiplexer 110 via an enable signal and for providing a switching voltage in some example embodiments. The enable signal and the switching voltage are described in more detail below.

[0036] Figure 1 The specific architecture shown is an example, and the scope of implementation is not limited thereto. For example, various implementations may include any appropriate number or location of power multiplexers 110, any number or location of memory blocks, any number or location of enable logic circuitry systems, and any number and location of processing blocks 106.

[0037] Figure 2 This is a conceptual diagram of an example of a multiplexed circuit system according to one implementation. Provided Figure 2 As illustrated, the power multiplexer 110 and the enable logic circuit system block 124 can be physically placed in the same block. In contrast, Figure 1 The implementation physically separates the power multiplexer 110 from the enable logic circuitry system block 124, thereby providing the multiplexer 110 itself with a smaller silicon footprint separate from any silicon footprint attributable to the enable logic circuitry system block 124.

[0038] Enable logic circuitry block 124 includes a forward path that can communicate with power management software, such as an operating system kernel running on the processor core of the SOC 100. The forward path can include signals from the power management software instructing enable logic circuitry block 124 to select one or another power supply Vdd1, Vdd2. A selection signal “SEL” is provided from enable logic circuitry block 124 to multiplexer 110, whereby one of the other power supplies Vdd1, Vdd2 is set or de-set. Although not discussed further herein, enable logic circuitry block 124 may have additional control signal outputs to other components (not shown) and may receive control signal inputs on feedback paths from those or other components (not shown). Furthermore, enable logic circuitry block 124 may also provide control signal feedback to the power management software.

[0039] The output (Vdd_apm) of power multiplexer 110 is provided to the memory block, for example... Figure 1 Any of the memory blocks 102-105. Enable logic system block 124 is shown as an example, and it should be understood that the concepts described with respect to block 124 also apply to block 126 and other enable logic system blocks within the peripheries 120, 122 of SOC 100.

[0040] Figures 3A-3C An example implementation is shown, wherein the power multiplexer 310 is disposed within a storage channel between memory blocks 302-305. For ease of illustration, Figure 3A The memory blocks 302-305, the power multiplexer 310, and the enable logic circuit system block 324 are shown. Figure 3B Vertical track 333 and horizontal track 334 are shown, which provide operating voltage Vdd_apm from power multiplexer 310 to memory blocks 302-305. Figure 3C Vertical rail 335 and horizontal rail 332, respectively communicating with the first power source MX, and vertical rail 336 and horizontal rail 331, respectively communicating with the second power source CX, are shown. In summary, Figures 3A-3C An embodiment including all tracks 331-336 built into the semiconductor device is shown.

[0041] Figures 3A-3C A top-down view, not scaled, is provided. Additionally, Figures 3A-3C Implementation within the SOC is not shown. Figures 3A-3CThe architecture is intended to utilize different metal layers. However, it should be understood that although tracks 331-336 are shown as intersecting, they are appropriately located on different layers so that different voltages do not short-circuit. Furthermore, the various tracks 331-336 can be appropriately electrically coupled via vias to any of the memory blocks 302-305, multiplexer 310, or enable logic circuitry system block 324. Figures 3A-3C The use of the tracks and vias shown can be applied to other embodiments described herein to provide appropriate electrical coupling for power multiplexers such as 110 and 310.

[0042] In this example, the enable logic circuit system block 324 is similar to the one described above. Figure 1 and Figure 2 The enable logic circuitry system block 124 is discussed in more detail. Each power multiplexer 310 is similar to the referenced above. Figure 1 and Figure 2 The power multiplexer 110 is discussed. Power multiplexer 310 communicates with two different power supplies MX and CX via tracks 331, 332, 335, and 336. Although no track is shown for distributing selection signals from enable logic circuitry block 324 to power multiplexer 310, it should be understood that tracks similar to any of tracks 331-336 may be additionally and appropriately included. Each multiplexer 310 selects one of power supplies MX and CX as its operating voltage to supply one or more memory blocks 302-305 via tracks 333 and 334.

[0043] Figure 4 This is a diagram illustrating an example power multiplexer 600 according to one embodiment. For example, power multiplexers 110 and 310 may employ... Figure 4 The architecture shown is correct. However, any suitable power multiplexer architecture can be used in various implementations.

[0044] The power multiplexer 600 selects between two power supplies, Vdd_MX and Vdd_apc. In one example, Vdd_MX represents the power supply used as the default for the memory block, while Vdd_apc represents the variable power supply used by the processor. Continuing with this example, during accelerated operation mode, Vdd_apc can be increased and supplied to the memory block via the power multiplexer 600. During non-accelerated operation mode, the power multiplexer 600 can select the Vdd_MX power supply for the memory block.

[0045] Figure 4The implementation includes two enable signals En_1 and En_2, and two P-type metal-oxide-semiconductor (PMOS) transistors 601 and 602. PMOS transistors 601 and 602 are turned off when the gate-source voltage is greater than or equal to zero, and turned on when the gate-source voltage is negative. Therefore, when En_1 is high and En_2 is low, transistor 601 is turned on and power multiplexer 600 selects Vdd_MX as the Vdd_apm output. On the other hand, when En_1 is low and En_2 is high, transistor 602 is turned on and power multiplexer 600 selects Vdd_apc.

[0046] Furthermore, enable signals En_1 and En_2 are used to ensure that only one is on at a given time, thus preventing short circuits in Vdd_MX and Vdd_apc. Nevertheless, both En_1 and En_2 can be low, thus not selecting any power supply.

[0047] When transistor 601 is turned on and transistor 602 is turned off, a voltage VDD_aon is applied to the gate of transistor 602. Vdd_aon is a switching voltage and is chosen to be the higher of Vdd_MX and Vdd_apc, thus ensuring that the gate-source voltage is greater than or equal to zero even if the voltage level of Vdd_apc changes. Similarly, when transistor 601 is turned off, Vdd_aon is applied to its gate, thereby ensuring that the gate-source voltage is greater than or equal to zero during its off-state.

[0048] Vdd_aon can be provided by one or more voltage generators, which can be separate from or included within the enable logic circuitry system block (e.g., 124, 126, 324). Furthermore, the enable signal indicates... Figure 2 Specific implementations of the selection signal (SEL) are provided, and they can be provided by an enable logic circuitry system block. The techniques for providing Vdd_aon and the enable signal will be referenced below. Figures 5-6 To provide a more detailed explanation.

[0049] Figure 4 An advantage of this implementation is that the power multiplexer 600 can be constructed to a relatively small size, as it comprises two transistors 601 and 602 and four inverters 611-614. Therefore, in some applications, the multiplexer 600 can be small enough to be physically disposed within the space (or memory channel) between two memory blocks. Such a arrangement is as follows: Figure 1 As shown in Figure 3, some or all of the power multiplexers 110 and 310 are located within the memory channel. The circuitry responsible for providing the enable signal and switching voltage can be placed elsewhere, thus avoiding the use of the silicon region within the memory channel. For example, Figure 1The embodiment shown in Figure 3 places this circuit system in the enable logic circuit system blocks 124, 126, and 324 on the periphery of the SOC.

[0050] Figure 5 This is a diagram of an example system 700 according to one implementation method, which can be implemented in a SOC. Figure 5 Provided to illustrate what can be used in including Figure 1 Techniques for distributing the switching voltage Vdd_aon in some applications, including those shown in Figure 3.

[0051] exist Figure 5 In the example, enable logic system blocks 721-724 are placed on the periphery of the SOC, and memory blocks 701-705 extend from right to left towards the center of the SOC. Enable logic system blocks 721-724 can be structurally and operationally similar to those described above. Figure 1 The enable logic circuitry blocks 721-724, specifically those similar to those discussed in Figure 3, are analogous to those in Figure 3. In this example, enable logic circuitry blocks 721-724 can provide enable signals to the power multiplexer 710 under the control of, for example, a power management program within the operating system kernel. Enable logic circuitry blocks 721-724 in… Figure 5 The tiles are referred to as "APM tiles" to indicate their role in adaptive power multiplexing (APM) operation. The power multiplexer 710... Figure 5 These are referred to as “micro-APMs” to indicate that their physical size is limited by omitting the enable logic circuitry and the switching voltage generated from the power multiplexer 710 itself.

[0052] For ease of explanation, only one power multiplexer 710 is labeled, but it should be understood that... Figure 7 The other power multiplexers in the implementation are essentially the same as those shown in item 710. Power multiplexers 710 are disposed within the region between each memory block 701-705, also referred to as a memory channel. Power multiplexers 710 output Vdd_apm to power rails 731-734, labeled VDD_AR. Power rails 731-734 are electrically coupled to memory blocks 701-705 and the corresponding enable logic circuitry system blocks 721-724. Within a given memory channel, the number of power rails 731-734 is less than the number of power multiplexers 710; therefore, more than one power multiplexer 710 can share the corresponding power rails 731-734.

[0053] The power multiplexer specifically designated as item 710 can provide power to one or both of memory blocks 701 and 702, both of which are adjacent to the power multiplexer specifically designated as item 710. Therefore, the power multiplexer specifically designated as item 710 provides power to adjacent memory blocks 701, 702 and avoids intermediate voltage drops that might be caused by other memory blocks in different applications. The same applies to other power multiplexers 710 between blocks 701, 702 and between other blocks 703-705; that is, each of the power multiplexers 710 provides power to adjacent memory blocks through at least one of power rails 731-734. Figure 7 The advantage of this implementation is that it reduces or eliminates the voltage drop from the multiplexer to the memory block by omitting the intermediate voltage drop that might otherwise be caused by the intermediate memory block.

[0054] The power multiplexer 710 receives the switching voltage Vdd_aon from the voltage generators 741-744 via rail 730. Figure 7 In this implementation, voltage generators 741-744 do not occupy silicon regions within the memory channels between each memory block 701-705. Instead, voltage generators 741-744 are placed together with enable logic circuitry system blocks 721-724 or adjacent memory blocks 705.

[0055] In some implementations, voltage generators 743 and 744 may be omitted. However, implementations that include more voltage generators distributed throughout the SOC may benefit from a more uniform Vdd_aon level across the entire SOC, but at the cost of increased circuitry overhead due to the additional voltage generators. In any case, the scope of the implementation is not limited to any number or arrangement of voltage generators, as any suitable number and arrangement of voltage generators can be used.

[0056] Figure 6 This is a diagram of an example system 800 according to one implementation method, which can be implemented in a SOC. Figure 6 Provided to illustrate what can be used in including Figure 1 The techniques for assigning enable signals and switching voltages Vdd_aon in some applications, as shown in Figure 3.

[0057] Figure 6 Implementation methods and Figure 5The implementation operates similarly. Specifically, each power multiplexer 710 provides operating voltage to one or two adjacent memory blocks 701-705 via power rails 731-734. In some implementations, enable logic circuitry system blocks 724-725 may include the multiplexers themselves (in addition to power multiplexers 710), and those multiplexers within enable logic circuitry system blocks 724-725 may utilize the switching voltage Vdd_aon via rail 730. However, the switching voltage Vdd_aon is not allocated to the power multiplexers 710 in the memory channel. Instead, each power multiplexer 710 in the memory channel may be constructed according to an architecture that ensures transistors are turned off in different ways. Figure 7 An example is shown.

[0058] Figure 7 This is a diagram illustrating an example power multiplexer 900 according to one embodiment. The example power multiplexer 900 can be used in any of the above embodiments. The power multiplexer 900 is described in U.S. Patent 10,103,626, the entire contents of which are incorporated herein by reference.

[0059] Power multiplexer 900 includes four PMOS transistors 911-914 and level shifters 901, 902. Power multiplexer 900 does not receive En_1 and En_2, but instead receives the inverted signals (also called bars) of those enable signals. When a high signal is received, each of level shifters 901, 902 selects the higher of the two power supplies Vdd_MX and Vdd_apc. When En_1 is high, its inverted form is low (digital zero), which is applied to the gates of transistors 911 and 912, thus turning on those transistors and selecting Vdd_MX. When En_1 is high, it is expected that En_2 will be low, so the reciprocal of En_2 will be high (digital one). Digital one turns off transistors 913 and 914. In the case of transistor 914, it receives the higher of Vdd_MX and Vdd_apc from level shifter 902. The higher voltage at transistor 914 ensures that transistor 914 is turned off, thus preventing any current from Vdd_apc.

[0060] Conversely, when transistors 911 and 912 are off, transistors 913 and 914 are on. In this case, transistor 912 receives the higher of Vdd_MX and Vdd_apc, thus ensuring that transistor 912 is off, thereby preventing any current from Vdd_MX.

[0061] Figure 7The advantage of this implementation is that the SOC architecture can omit the allocation of Vdd_aon to the power multiplexer 710 in the memory channel. However, the two additional transistors of the power multiplexer 910 may cause additional voltage drops from each power supply Vdd_MX and Vdd_apc during use. Furthermore, Figure 7 The power multiplexer 900 is greater than Figure 6 The power multiplexer 600, and in some applications where space within the memory channel is very precious, may not be feasible to implement within the memory channel.

[0062] Return to Figure 6 It also illustrates examples of routing enable signals En_1 and En_2. Specifically, enable logic circuitry block 725 distributes enable signals to power multiplexers 710 within the channels between memory blocks 701-705. Although Figure 6 Enable wiring from enable logic circuitry block 725 is shown only, but this is for illustrative purposes. It should be understood that other enable logic circuitry blocks 721-725 may or may not use enable wiring (not shown) to distribute enable signals to some of the power multiplexers 710. Figure 6 The routing enable signal technique shown above can be applied to the above. Figure 1 -Figure 3 and Figure 5 Other implementations described herein.

[0063] Furthermore, the enable logic circuit system blocks 721-725 can be used for any suitable purpose. For example, in Figure 6 In this implementation, blocks 721-725 host voltage generators 741 and 742. Furthermore, each of the enable logic circuitry blocks 721-725 may include a power multiplexer in addition to the power multiplexer 710 within the memory channel. This additional power multiplexer is not included in... Figure 6 As shown, however, they can be used to supplement or replace power multiplexer 710 to provide operating voltage to any of the memory blocks 701-705. In fact, each of the enable logic circuitry system blocks 721-725 may include one or more power multiplexers, wherein more power multiplexers within a given enable logic circuitry system block are expected to reduce voltage drop because they can route to multiple memory blocks in parallel at once. However, such a technique can use more… Figure 6 The diagram shows more routing and metal layers. Figure 8 An example enable logic circuitry system block 850 according to one embodiment is shown, which includes four switch blocks 851-854; however, the scope of the embodiment may include any number of switch blocks. Block 850 also includes an enable logic circuitry system and a switch voltage generation circuitry system 855.

[0064] and Figure 2 In contrast, block 850 may include an enable logic circuitry system block and a switching voltage generation, and each switching block 851-854 may correspond to a power multiplexer 110. Therefore, the scope of the implementation does not preclude at least some multiplexing functions from being implemented within the enable logic circuitry system block. The enable logic circuitry system and switching voltage generation of block 855 may communicate with one or more smaller power multiplexers, such as those shown as 110 or 310 in the examples above. In other words, in some implementations, block 850 may be implemented as one or more of blocks 124, 126, 324, and / or 721-725.

[0065] Figure 9 It shows that it can be used with Figure 8 An additional routing layer and metal layer are used in the same implementation. The metal layers are shown (from top to bottom) D8-M1, with the transistor shown below M1. The different metal layers are connected by vias, which are indicated by "V". Figure 8 The switch blocks 851-854 can be used Figure 9 The metal layers and vias are implemented in any suitable manner. In one embodiment, the design maximizes the number of vias allowed by applicable constraints, thereby increasing the number of wiring paths within a given volume of the device, wherein the increased number of wiring paths serves an increased number of switch blocks 851-854.

[0066] The above is about Figures 1-9 The described implementation offers advantages over other designs that place power multiplexers only at the periphery of the SOC. For example, when power multiplexers are limited to the periphery of the SOC, they can provide operating voltages to multiple memory blocks connected in series via voltage rails. However, each of those memory blocks can cause the voltage drop to increase quadratically with increasing intermediate memory blocks, so that the memory block furthest from the power multiplexer may experience a significant voltage drop. Some systems can then raise the minimum voltage of the power rails so that the furthest memory block receives an acceptable operating voltage level. However, raising the minimum voltage level on the power rails may be wasteful of power. Alternatively, such systems may not raise the minimum voltage level on the rails, but in this case, the memory blocks can be limited to operating speeds corresponding to the lowest voltage level at the furthest memory block.

[0067] In contrast, the various embodiments described herein can place power multiplexers near their memory blocks, such that a given power multiplexer is adjacent to one or two memory blocks it serves. Thus, at least some power multiplexers and their respective memory blocks can be spatially arranged such that a given multiplexer supplies a given memory block without any intermediate memory blocks causing a voltage drop. Therefore, this design can omit on-rail voltage compensation, which would otherwise be used in the case of intermediate voltage drops. Furthermore, each memory block can operate at a speed that is not reduced due to lower voltages at other memory blocks.

[0068] Figure 10 The diagram shows a flowchart of an example method 1000 for multiplexing among multiple power supplies. In one example, method 1000 consists of... Figures 1-7 The circuits shown are executed. These circuits can operate under the control of a power management unit, which may include hardware and / or software functions at the processor (e.g., CPU) of the computing device, the computing device including... Figure 1 In the SOC 100, in processing block 106. In some examples, the power management unit includes a processing circuitry that executes computer-readable instructions to select one power supply or another power supply as the operating voltage for one or more memory blocks.

[0069] At action 1010, the system selects a first power supply as the operating voltage for the first memory block. For example, the first power supply may be at a higher voltage level to support accelerated processing mode. In another example, the first power supply may be at a lower voltage level compared to a higher voltage level to be used during non-accelerated operation to conserve battery life.

[0070] In this example, the first power supply is selected by a first power multiplexer located between the first memory block and the second memory block. Figure 1 An example is shown in which a power multiplexer 110 is disposed between memory blocks 102 and 103. Figures 3A-3C , Figure 5 , Figure 6 Other examples are illustrated in the figure. Examples of the gate and transistor levels of the power multiplexer used in this implementation are as follows: Figure 2 , 4 As shown in Figure 7.

[0071] Furthermore, selection can be performed under the control of an enable logic circuit system located on the periphery of the chip, such as a chip. Examples of enable logic circuit systems include... Figures 1-2 Enable logic circuit system 124 Figures 3A-3C Enable logic circuit system 324 and Figures 5-6The enabling logic circuitry systems 721-725 are described above. Furthermore, in this example, the enabling logic circuitry systems may also provide a switching voltage configured to turn the transistors of the multiplexer on or off. An example is Vdd_aon in the above embodiments.

[0072] Continuing this example, selection can be performed by setting or de-setting the enable signal of a transistor in the first power multiplexer. In one example, the multiplexer includes a PMOS transistor that is turned off by a high (digital one) signal and turned on by a low (digital zero) signal. Therefore, in a PMOS implementation, a low signal can be used to turn on the transistor, creating a current path between the first power supply and the power rail supplying the first memory block, while a high signal turns off another transistor that would otherwise create a current path between the second power supply and the power rail. In an example using an N-type metal-oxide-semiconductor (NMOS) transistor, a high signal is used to turn on the transistor, and a low signal is used to turn it off. The enable signal can be provided by an enable logic circuit system.

[0073] At action 1020, the system selects a second power supply as the operating voltage for the first memory block under the control of the enable logic circuitry. For example, the system can switch from an accelerated mode to a non-accelerated mode (or vice versa) when switching from the first power supply to the second power supply. As with selecting the first power supply, selecting the second power supply may include setting or de-setting an enable signal to turn on or off the appropriate transistor in the first power multiplexer.

[0074] The scope of the implementation method is not limited to Figure 10 The actions shown are not the same as those in the embodiments, but other implementations may add, omit, rearrange, or modify one or more actions. For example, some implementations may include repeating actions 1010-1020 multiple times during normal operation of the processor on the chip as it transitions from one power mode to another.

[0075] As those skilled in the art will now understand and, depending on the specific application at hand, many modifications, substitutions, and variations can be made to the method of use, materials, apparatus, and configuration of the device without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein, as they are only by way of a few examples, but should be fully commensurate with the scope of the appended claims hereinafter and their functional equivalents.

Claims

1. A system-on-a-chip (SoC), comprising: First memory block and second memory block; The processing unit is coupled to the first memory block and the second memory block; A first power multiplexer is disposed between the first memory block and the second memory block and coupled to a first power rail, the first power rail being configured to provide an operating voltage to both the first memory block and the second memory block; An enabling logic circuit system is disposed on the periphery of the SOC, away from the first memory block and the second memory block. The enabling logic circuit system is configured to control the first power multiplexer to select between a first power supply voltage and a second power supply voltage to provide the operating voltage to the first power rail. as well as A voltage generator is configured to provide a switching voltage to the first power multiplexer via a second power rail, wherein the first power multiplexer is configured to use the switching voltage to turn off a transistor within the first power multiplexer.

2. The SOC according to claim 1 further includes a second power multiplexer disposed between the first memory block and the processing unit, and coupled to the first power rail.

3. The SOC according to claim 1, wherein the first power multiplexer is one of a plurality of power multiplexers disposed in a memory channel between the first memory block and the second memory block, the plurality of power multiplexers being coupled to the enable logic circuit system.

4. The SOC according to claim 1, wherein the voltage generator is disposed on the periphery of the SOC.

5. The SOC of claim 1, wherein the voltage generator is disposed away from the periphery of the SOC and adjacent to the first memory block.

6. The SOC of claim 1, wherein the voltage generator comprises one of a plurality of voltage generators coupled to the second power rail.

7. A method comprising: A first power supply is selected as the operating voltage for the first memory block, wherein the first power supply is selected by a first plurality of power multiplexers and a second plurality of power multiplexers disposed between the first memory block and the second memory block, wherein the selection is under the control of an enabling logic circuit system disposed at the periphery of the system-on-a-chip (SoC) remote from the first memory block and the second memory block. Under the control of the enabling logic circuit system, a second power supply is selected as the operating voltage for the first memory block; and A switching voltage is received at the control terminal of a transistor in each of the first plurality of power multiplexers and the second plurality of power multiplexers, the switching voltage turning off the transistor, wherein the switching voltage is selected as the higher of the following: the first power supply and the second power supply.

8. The method of claim 7, wherein selecting the first power source comprises: For each of the first plurality of power multiplexers and the second plurality of power multiplexers, an enable signal is received from the enable logic circuitry system.

9. The method according to claim 7, further comprising: The enable logic circuit system is controlled by a power control program running on the processing unit of the SOC.

10. A semiconductor chip, comprising: First memory block and second memory block; A first power multiplexer is disposed between the first memory block and the second memory block and coupled to a first power rail, the first power rail being configured to provide an operating voltage to both the first memory block and the second memory block; A component for controlling the first power multiplexer to select between a first power supply voltage and a second power supply voltage to provide the operating voltage to the first memory block and the second memory block, wherein the component for control is disposed on the periphery of the chip away from the first memory block and the second memory block, and the component for control is coupled to the control terminal of the transistor of the first power multiplexer. and A voltage generator is configured to provide a switching voltage to the first power multiplexer via a second power rail, wherein the first power multiplexer is configured to use the switching voltage to turn off the transistors within the first power multiplexer.

11. The semiconductor chip of claim 10, wherein the first power multiplexer is configured to provide the operating voltage to the first memory block, and there is no voltage drop attributable to an intermediate memory block.

12. The semiconductor chip of claim 10, wherein the first power multiplexer comprises a plurality of power multiplexers disposed in a memory channel between the first memory block and the second memory block.

13. The semiconductor chip of claim 10, wherein the first power multiplexer comprises: A first plurality of power multiplexers and a second plurality of power multiplexers are disposed in a memory channel between the first memory block and the second memory block, and the second plurality of power multiplexers are disposed between the second memory block and the processing unit.

14. A system-on-a-chip (SoC), comprising: First memory block and second memory block; The processing logic includes a set of processing blocks, the processing logic being configured such that the first memory block and the second memory block are located between the processing logic and the periphery of the SOC, the periphery of the SOC corresponding to the lateral portion of the side of the SOC; An enabling logic circuit system is located within the periphery of the SOC; A first plurality of power multiplexers are disposed between the first memory block and the second memory block, and the first plurality of power multiplexers are configured to receive an enable signal and a switching voltage from the enable logic circuit system; and A second plurality of power multiplexers are disposed between the second memory block and the processing logic, and the second plurality of power multiplexers are configured to receive the enable signal and the switching voltage from the enable logic circuitry.

15. The SOC according to claim 14, further comprising: A voltage generator is configured to provide the switching voltage to the first plurality of power multiplexers via a first power rail.

16. The SOC of claim 15, wherein the voltage generator is disposed on the periphery of the SOC.

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