Voltage glitch detection and protection circuit for secure memory devices

Abstract

A voltage glitch detection and protection circuit and method is provided. Generally, the circuit includes a voltage glitch detection block (GDB) and a system reset block coupled to the GDB to generate a reset signal to reset a device in a chip including the circuit in the event of a voltage glitch in a supply voltage (VDD). The GDB includes a voltage glitch detector coupled to a latch. The voltage glitch detector detects a voltage glitch and generates a PULSE to the system reset block and the latch to ensure that the reset signal is generated regardless of the width of the PULSE. In one embodiment, the latch includes a filter and a sample-and-hold circuit to power the latch in the event that the voltage to the GDB or the latch drops below a minimum voltage due to the voltage glitch and to ensure that the PULSE_LATCHED signal is coupled to the system reset block.

Description

[0001] Cross-reference to related applications

[0002] This application is an international application of U.S. Nonprovisional Application No. 17 / 241,447, filed April 27, 2021, which claims priority to U.S. Provisional Patent Application No. 63 / 048,975, filed July 7, 2020, pursuant to 35U.SC119(e), all of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to secure memory devices, and more specifically, to voltage spike detectors and methods for operating the voltage spike detector to detect and prevent side-channel voltage spike attacks in secure memory devices. Background Technology

[0004] Figure 1 This is a schematic block diagram illustrating a side-channel voltage glitch attack (SCA) on the security chip 100. (Refer to...) Figure 1 In SCA, a hacker uses external hardware 102 to induce voltage spikes 104 on the chip's power supply voltage 106, causing the analog and / or digital circuits and components on the chip to operate under unstable or abnormal conditions. This can allow the attacker to access confidential data stored in the secure chip's memory 108, such as encryption keys. A voltage spike refers to a very rapid and brief drop in the power supply voltage from the standard complementary metal-silicon (CMOS) voltage level to 0V or a negative voltage, followed by a similarly rapid return to the power supply voltage. For example... Figure 1 As shown, voltage glitches 104 can cause the output voltage from the power supply voltage 106 to, for example, change from the standard CMOS voltage (V). STD ) drops to the minimum CMOS voltage (VDD) MIN The time frame can be as short as approximately 20 ns. For many security systems, and especially for systems including security chips 100 with secure non-volatile or flash memory, SCA has become a significant problem.

[0005] Existing security chips or systems with memory typically include a conventional reset circuit 200, which comprises one or more blocks or circuits to detect various events or changes in electrical voltage or power. For example, Figure 2The reset circuit 200 shown includes a slow clock voltage detector (slow CLK detector 202), a CMOS level detector 206, and an undervoltage detector (BOD 208). The slow CLK detector 202 is designed to detect a drop in the first power supply voltage (VPWR) and signal the power-on / power-off (PU / PD) controller 204 to reduce the clock speed of the CMOS device for compensation. The CMOS level detector 206 detects a significant drop in the second (main) power supply voltage (VDD) occurring at the first rate or slope and signals the PU / PD controller 204 to perform a full system reset of all analog and digital devices on the security chip or in the security system using the reset circuit 200. The primary purpose of the CMOS level detector 206 is to signal the PU / PD controller 204 that the power supply voltage is higher than the CMOS level. The CMOS level detector is implemented in such a way that it can initiate a full system reset when the power supply voltage drops below the CMOS level for approximately 15 μsec. The primary purpose of the CMOS level detector 206 is to send a signal to the PU / PD controller 204 that the supply voltage is higher than the CMOS level. However, this does not indicate that the voltage is high enough to meet all functions or performance requirements; therefore, a more accurate BOD is used for this purpose. BOD 208 is designed to detect a smaller voltage drop at VDD occurring at a shorter duration and a higher voltage slope than that of the CMOS level detector 206, and to signal the PU / PD controller 204 to perform a partial system reset of the on-chip analog and digital devices (including at least some devices in the secure data domain, such as at least some on-chip memory). Both the CMOS level detector 206 and BOD 208 require a power-off time (tpD) longer than 300 ns at or below the transition point of either the CMOS level detector or the BOD before initiating the reset. Therefore, both the CMOS level detector 206 and BOD 208 typically have a relatively slow response time, which is too long to detect the 20 ns glitches of fast SCA.

[0006] Furthermore, both CMOS level detectors 206 and BOD 208 are typically integrated into the same circuitry as other devices on the security chip and experience the same supply voltage drops. Therefore, they may become ineffective or at least unreliable under extreme and / or rapid voltage changes (e.g., pulses of SCA or extreme, rapid negative voltage glitches). Because CMOS level detectors 206 and BOD 208 cannot operate reliably under the voltage conditions of voltage glitches, they cannot detect SCA. This is particularly problematic for CMOS level detectors 206 and BOD 208, which are manufactured using CMOS devices and cannot operate under sub-CMOS and / or negative voltage conditions.

[0007] Figure 3 The diagram illustrates the timing of typical voltages and signals in a conventional power reset scheme using a CMOS level detector and a BOD. Specifically, line 300 in the top diagram represents a drop in the supply voltage that will be detected by a conventional CMOS level detector, triggering a reset pulse 304. Line 302 in the middle diagram represents a separate event, a drop in the supply voltage that is both faster and smaller than a drop in supply voltage that can be detected by a conventional CMOS level detector, but which will be detected by a conventional undervoltage detector (BOD), triggering a reset pulse 304, thus causing a safe reset of all circuitry and components on the chip.

[0008] Refer again Figure 3 The top figure in the diagram should indicate that conventional CMOS level detectors are capable of a falling slope (Tf) of approximately 40 μsec / 1V. V ) detects reset supply voltages as low as approximately 1.1V to approximately 0.7V. rst The power supply voltage drops, and a reset pulse will be triggered after a tpD period much longer than 0.05 μs (50 ns). It should also be noted that the reset pulse 304 does not become de-asserted until the power supply voltage recovers to the power-on reset voltage (Vpor) of approximately 1.52 V.

[0009] Similarly, such as Figure 3 As shown in the middle figure, conventional BOD can achieve steeper or higher descent slopes (Tf). BOD ) detects undervoltage supply voltage transition levels as low as approximately 1.45V (V bod The power-off time (tpD) required by the BOD is typically set by the local response time of the comparator in the BOD (typically 50ns to 100ns) plus the charging time of the additional RC circuitry in the BOD (e.g., approximately 300ns in total).

[0010] Therefore, there is a need for voltage spike detection and protection systems or circuits, as well as methods for detecting and preventing side-channel voltage spike attacks in secure memory devices. It is also desirable that such circuits and methods do not interfere with existing CMOS level detectors or BODs, or otherwise adversely affect the operation of security chips or memory devices that include or use them. Summary of the Invention

[0011] A voltage glitch detection and protection circuit and a method for preventing voltage glitch are provided. Typically, the circuit includes a voltage glitch detection block and a system reset block, the system reset block being coupled to the voltage glitch detection block to generate a system reset signal upon detection of a voltage glitch in the supply voltage (VDD), thereby resetting multiple on-chip circuits or sub-circuits and devices including the voltage glitch detection and protection circuit. The voltage glitch detection block includes a voltage glitch detector coupled to a latch. The voltage glitch detector detects a voltage glitch and generates a voltage glitch detection pulse (PULSE) and couples it to the system reset block and the latch. The latch receives the PULSE and generates a voltage glitch detection pulse latch (PULSE_LATCHED) signal and couples it to the system reset block to ensure that a system reset signal is generated regardless of the width of the PULSE. In one embodiment, the latch is a voltage glitch isolation latch and includes a voltage glitch isolation filter to provide a filtered VDD voltage (VDD) to the latch when VDD of the latch and / or the voltage glitch detection block drops below a minimum voltage due to a voltage glitch. RC ), and VDD RC Sample and hold power supply (VDD) RC-S&H It further supplies power to the latch and ensures that the PULSE_LATCHED signal is coupled to the system reset block.

[0012] On the other hand, a method is provided for operating voltage glitch detection and protection circuitry to prevent voltage glitch in a safety chip. Typically, this method begins based on a predetermined setpoint voltage (V) coupled to a second input terminal of a comparator. GLITCH The power supply voltage (VDD) coupled to the first input of the comparator in the voltage glitch detection block and the reference voltage (V) are used to... REF Compare this to the reference voltage (VDD). <V REF If a voltage glitch detection pulse (PULSE) is generated and coupled to the latch and system reset block in the voltage glitch detection block, then a voltage glitch detection pulse latch (PULSE_LATCHED) signal is generated and coupled to the system reset block. The system reset block receives the PULSE and / or PULSE_LATCHED signals and generates a safe system reset signal, ensuring that the sub-circuits and devices in the chip are fully and safely reset. Because the latch generates a separate PULSE_LATCHED signal and couples it to the system reset block, a system reset signal is generated regardless of the width of the PULSE. In one embodiment, the method further includes filtering, sampling, and holding the voltage of the latch to ensure that the PULSE_LATCHED signal is coupled to the system reset block when the voltage of the latch and / or the voltage glitch detection block drops below a minimum voltage due to a voltage glitch.

[0013] Voltage spike detection and protection circuits and methods are particularly suitable for protecting security chips, including embedded non-volatile memory (eNVM) or flash memory, from side-channel voltage spike attacks (SCA).

[0014] Other features and advantages of embodiments of the present invention, as well as the structure and operation of various embodiments of the present invention, will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Attached Figure Description

[0015] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which corresponding reference numerals indicate corresponding parts. Furthermore, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the invention and, together with the description, further serve to explain the principles of the invention and enable those skilled in the art to implement and use the invention.

[0016] Figure 1 This is a block diagram illustrating a side-channel voltage glitch attack (SCA) on a security chip;

[0017] Figure 2 This is a block diagram of a conventional circuit used to detect changes in power supply voltage.

[0018] Figure 3 This is a timing diagram showing typical voltages and signals in a conventional power reset scheme;

[0019] Figure 4 This is a block diagram illustrating an embodiment of a voltage glitch detection and protection circuit including a voltage glitch detection block;

[0020] Figure 5 This is a schematic diagram illustrating an embodiment of a current comparator for a voltage glitch detector;

[0021] Figure 6 This is a schematic diagram illustrating an implementation of a voltage glitch detector based on a current comparator;

[0022] Figure 7 This is a schematic diagram illustrating an embodiment of a voltage glitch isolation latch that includes a power supply voltage glitch isolation filter and a sample and hold (S&H) circuit.

[0023] Figure 8 This is a schematic diagram illustrating an implementation of a four-transistor voltage adder that utilizes voltage mirroring technology to provide a voltage glitch detector with an accurate reference voltage that is twice as high as the maximum available reference voltage on the chip.

[0024] Figure 9A and Figure 9B This is a schematic diagram illustrating an implementation of a current mirror circuit for voltage glitches detection and protection, and it operates at a voltage much lower than the minimum user supply voltage (VDD). MIN Provides a reliable voltage glitch detection reference current mirror for reference current originating from a high saturation voltage and current source at VDD level or even below BOD level;

[0025] Figure 10A These are waveform and timing diagrams illustrating an implementation scheme for voltage spike detection and protection power reset for short voltage spikes.

[0026] Figure 10B These are waveform diagrams and timing diagrams illustrating an implementation scheme for voltage spike detection and protection power reset for long voltage spikes.

[0027] Figure 11 It is a waveform diagram of a side-channel voltage glitch attack (SCA) on a security chip including voltage glitch detection and protection circuitry, and the signal in response thereto, illustrating the circuit's ability to prevent SCA.

[0028] Figure 12 This is a schematic diagram illustrating another embodiment of a voltage glitch detector and a voltage glitch detector latch capable of operating in a negative voltage domain caused by voltage glitch.

[0029] Figure 13A and Figure 13B This is a schematic diagram illustrating an implementation of a system reset block, which includes a holding circuit to invoke detected voltage glitches when the system reset block is powered back on;

[0030] Figure 14 This is a flowchart illustrating a method for detecting and preventing side-channel voltage glitch attacks (SCA) using an operating voltage glitch detection and protection circuit; and

[0031] Figure 15 This is a block diagram of an embedded non-volatile memory (eNVM) system including a system reset subsystem analog (SRSSA) block with voltage glitch detection and protection circuitry, which includes a voltage glitch detector for preventing SCA (Super Squeeze Attack). Detailed Implementation

[0032] Voltage spike detection and protection circuitry and methods for detecting and preventing side-channel voltage spike attacks or side-channel attacks (SCA) are disclosed.

[0033] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail or illustrated in block diagram form in order to avoid unnecessarily obscuring the understanding of this specification.

[0034] The reference to "one embodiment" or "implementation" in this specification means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing in different places in the specification does not necessarily refer to the same embodiment. The term "coupled" as used herein can include both direct electrical connection of two or more components or elements and indirect connection of two or more components or elements through one or more intermediate components.

[0035] Now refer to Figures 4 to 7 This describes an implementation of a power reset or voltage glitch detection and protection circuit or system, which includes a voltage glitch detection block (e.g., used in an SCA) for detecting glitches. A glitch refers to a very brief and rapid drop in the mains supply voltage (VDD) from a standard voltage level to 0V or even a negative voltage, followed by a similarly rapid return to the supply voltage or a much slower return. Voltage glitches used in SCAs can last from as short as approximately 20 ns to last for more than several microseconds.

[0036] In particular, Figure 4 This is a block diagram illustrating an embodiment of a voltage glitch detection and protection circuit 400 including a voltage glitch detection block. (Refer to...) Figure 4 In one embodiment, the voltage glitch detection and protection circuit 400 includes a power-on / power-off (PU / PD) controller 402 or block, multiple reset detectors, and a programmable power-on driver 406, which includes power-on control logic, a voltage driver, and a one-time programmable (OTP) trimmer. Optionally, the glitch detection and protection circuit 400 also includes design-for-test (DFT / logic 408). The multiple reset detectors may include one or more CMOS level detectors 414a, 414b coupled to a first voltage supply (VPWR) slow clock voltage detector (slow CLK detector 410), an undervoltage detector (BOD 412), and a system reset block 416, and according to this disclosure, the voltage glitch detection block 418 includes a voltage glitch detector 420 and multiple latches or voltage glitch protection latches (e.g., voltage glitch protection set / reset (S / R) latches 422a, 422b).

[0037] The PU / PD controller 402 receives system reset signals from multiple reset detectors and generates one or more global reset signals for analog and digital or logic devices and other circuitry on the security chip (not shown) to power on the devices and circuitry according to a predefined power-on reset (POR) sequence. Preferably, the POR sequence of the chip is the same regardless of the event causing the reset, to ensure that the security chip or device in which voltage glitch detection and protection circuitry 400 is implemented or includes is secure, thereby ensuring the security of confidential data such as encryption keys.

[0038] The programmable power-on driver 406 includes a plurality of one-time programmable (OTP) memory elements, logic elements, and voltage drivers powered by one or more main voltage supplies, including a first voltage supply (VPWR) and a second or main voltage supply (VDD). The programmable power-on driver 406 is configured to receive one or more global reset signals from the PU / PD controller 402 and, upon power-on, send a plurality of enable signals, voltage trimming signals, and reference signals to the reset detector.

[0039] A slow Clk voltage detector 410 is coupled to the VPWR to monitor the VPWR voltage. The slow Clk voltage detector 410 receives an enable signal and an OTP voltage trimming signal from a programmable power-on driver 406 and is configured to detect a drop in the VPWR from a first CMOS voltage (e.g., 1.8V) to a second CMOS voltage (e.g., 1.6V) and signal to the PU / PD controller 402 to reduce the clock speed of devices and circuits on a safety chip in which voltage glitches detection and protection circuitry 400 is implemented, to compensate for drops below a predetermined minimum user voltage (VDD). MIN CMOS speed degradation at voltages of )

[0040] An undervoltage detector, or BOD 412, is coupled to a second main voltage supply (VDD) for both power supply and monitoring of the VDD voltage. BOD 412 receives an enable signal and an OTP voltage trimming signal from a programmable power-on driver 406, and typically uses a comparator sensor, which may detect the jump point voltage (VDD) of the BOD before startup reset. BOD The downtime required at or below this level is several hundred nanoseconds. The BOD 412 is designed or configured to detect a smaller voltage drop at VDD than the CMOS level detectors 414a, 414b, at a shorter duration and a higher voltage slope, and to signal the PU / PD controller 402 to perform a partial system reset of the on-chip analog and digital devices (including at least some devices in the secure data domain, such as at least some on-chip memory).

[0041] In the illustrated embodiment, a first CMOS level detector 414a is coupled between the voltage glitch detection block 418 and the PU / PD controller 402, and a second CMOS level detector 414b is coupled to the PU / PD controller. The CMOS level detectors 414a and 414b are also coupled to VDD for both power supply and monitoring of the VDD voltage, and include a sensor configured to detect / sensor a VDD drop at a slope or rate much lower than that configured to be detected / sensed by BOD 412.

[0042] In the illustrated embodiment, the system reset block 416 further includes a first logic gate 424, through which the two complements of the secure system reset signal (SYS_RESET_B Sec.) from the first CMOS level detector 414a and the non-secure system reset signal (SYS_RESET_B non-Sec.) from the second CMOS level detector 414b are coupled to the PU / PD controller 402, so that the PU / PD controller performs a complete reset of the security chip.

[0043] Regarding slow VDD power supply change detection, the first CMOS level detector 414a and the second CMOS level detector 414b are similar in configuration and function, but they differ in their behavior during voltage glitches. Specifically, as... Figure 4 As shown, the first CMOS level detector 414a is configured to receive both a voltage glitch detection pulse (PULSE) and a voltage glitch pulse latch (PULSE_LATCHED) signal from the voltage glitch detection block 418, and in response generate a SYS_RESET_BSec. signal, which is then coupled to the PU / PD controller 402 via a first logic gate 424. Furthermore, as described in more detail below, in some embodiments, the first CMOS level detector 414a is used as a hold or memory circuit to store and recall voltage glitch detection events upon power restoration after the system reset block 416 has lost power.

[0044] In addition to the glitch detector 420, the voltage glitch detection block 418 also includes at least a first voltage glitch protection S / R latch 422a. The first voltage glitch protection S / R latch 422a has an output coupled to the voltage glitch detector 420 to receive a PULSE set (S) input therefrom, an output connected to a first CMOS level detector 414a to couple the PULSE_LATCHED signal thereto, and an output coupled to the first logic gate 424 to reset the first voltage glitch protection S / R latch's reset_b function when the SYS_RESET_B signal is coupled to the PU / PD controller 402. enter.

[0045] As included in the illustrated embodiment, the glitch detection block 418 further includes a second voltage glitch protection S / R latch 422b, which has an output coupled to the voltage glitch detector 420 to receive a PULSE set (S) input, an output coupled to the (DFT) / logic 408, and an output coupled to the second CMOS level detector 414b to reset the second voltage glitch protection S / R latch only when a full VDD power-off reset is performed. Input. This second instance of the voltage glitch-protected S / R latch 422b is used for DFT purposes because the second glitch-protected latch is the only volatile memory element on the safety chip that can withstand both a voltage glitch event (which is not detected as a complete power-off by the second CMOS level detector 414b) and the subsequent chip reset. By directly coupling the DFT PULSE_Latched signal to the DFT / logic 408, the chip can "remember" whether a voltage glitch existed before the last chip reset event. Therefore, the DFT / logic 408 enables the chip to know that a voltage glitch event or SCA has been detected, thereby enabling the testing and calibration of the circuitry in the voltage glitch detection block 418.

[0046] The voltage spike detector 420 may include any suitable voltage- or current-based comparator capable of detecting voltage spikes or SCAs with similar characteristics. The characteristics of a voltage spike detected by the voltage spike detector 420 may include a rapid drop or decrease in the main supply voltage (VDD) below a predetermined target spike or setpoint voltage (V). GLTICH ), and V GLTICH The following narrow pulse widths or power-off times (tpD) are as low as approximately 20 ns. Under these conditions, the comparator of a suitable voltage glitch detector 420 can deliver a sufficiently wide voltage glitch detection pulse (PULSE) to directly trigger the first CMOS level detector 414a or to set the first voltage glitch protection S / R latch 422a.

[0047] Typically, the voltage spike detector 420 receives a threshold detection level (V) that is substantially equal to the target spike voltage from the reference voltage generator 425 in the voltage spike detection block 418. GLITCH The fine-tuning reference voltage (V) GLITCH-TRIMMED The reference voltage generator 425 receives the bandgap reference (BGREF) voltage and digital voltage trimmer (V) directly from the programmable power-on driver 406. Trim () signal to generate V from 0.9V to 2.3V. GLITCH-TRIMMED The voltage can be adjusted in 50mV increments or steps. GLITCH-TRIMMED The voltage is supplied by a voltage adder circuit (e.g., Figure 8 (As shown) The voltage is generated within a reference voltage generator 425, which can generate voltages up to 2.3V using two voltage inputs less than or equal to 1.2V. The two inputs of the voltage adder are taken from a 50mV resolution 0V to 1.2V voltage ladder within the reference voltage generator 425. Although shown separately from the voltage glitch detector 420 in this embodiment, it should be understood that the reference voltage generator 425 may alternatively be included within the voltage glitch detector.

[0048] Furthermore, in the illustrated embodiment, the voltage glitch detection block 418 also includes a second logic gate 426, through which the voltage glitch detector 420 is coupled to the programmable power-on driver 406. The second logic gate 426 receives an enable signal and a bandgap reference OKAY (BGREF_OK) signal from the programmable power-on driver 406, and outputs a voltage glitch detection enable (EN) signal to the voltage glitch detector 420.

[0049] As described above, the voltage glitch detector 420 may include any suitable voltage- or current-based comparator circuitry. In some embodiments, the voltage glitch detector 420 is a current comparator or includes a current comparator. Current comparator-based voltage glitch detectors offer many advantages over voltage comparator-based voltage glitch detectors, including easier isolation from extreme voltage glitch that could otherwise negatively impact the operation of the voltage glitch detector 420 and the functionality of the voltage glitch detection and protection circuitry 400.

[0050] Now refer to Figure 5 Description applicable Figure 4 Implementation of the current comparator for a voltage glitch detector. See [reference]. Figure 5 The comparator circuit 500 typically includes a current source 502, which is connected in series with an n-channel metal-oxide-semiconductor field-effect transistor (nMOS 504) at the comparator's isolation power supply voltage (VDD). COMP_RC The so-called comparator isolation power supply voltage refers to the comparator's power supply voltage (VDD) between the comparator and ground. COMP_RC The power supply voltage (often referred to here as VDD or VDD) is monitored by means of, for example, a low-pass filter or a resistor-capacitor (RC) filter and chip glitches. CHIP High-frequency / high-slope event isolation on VDD. This isolation significantly reduces the impact of VDD or VDD during the time period required for the comparator to safely generate a voltage glitch detection indication. CHIP The fast voltage spikes on the circuit cause voltage fluctuations in comparator circuit 500. The nMOS 504 has a source and body junction commonly coupled to ground, and a spike monitoring supply voltage (VDD or VDD).CHIP The gate of the voltage glitch isolation current source 502 receives the reference voltage (V). REF (not shown in the figure), and provides a reference current (I) VOLTAGE-GLITCH The reference current is essentially equal to the current flowing through it in V. VOLTAGE-GLITCH Gate-source voltage (V) GS-NMOS The current of the operating nMOS 504, where V VOLTAGE-GLITCH It is the jump point of the comparator and is considered to be VDD (or VDD). CHIP ) level, from this VDD (or VDD) CHIP Voltage levels below a specified level are considered voltage glitches. In some implementations, a reference voltage (V) is also provided to the current source 502 via an RC filter. REF This makes the current source a voltage glitch isolated current source. During operation, when VDD or VDD is coupled to the gate of the nMOS504... CHIP Descending to V VOLTAGE-GLITCH The following is the current (I) flowing through the nMOS due to VDD. VDD Reduce to less than the reference current (I) VOLTAGE-GLITCH ), and therefore, the voltage (V) at the output of comparator circuit 500 OUT The value becomes logical high or "1". Conversely, if VDD is higher than or greater than VDD, it becomes logical high or "1". VOLTAGE-GLITCH Then the current (I) through the nMOS 504 VDD ) greater than the reference current (I) VOLTAGE-GLITCH ), and the output of comparator circuit 500 (V OUT It can be changed to or remain logically low or "0".

[0051] Figure 6 This is a simplified schematic diagram illustrating an embodiment of a voltage glitch detector 600 based on a current comparator, which includes a p-channel metal-oxide-semiconductor field-effect transistor (pMOS) as the current source in a glitch-isolated current comparator 602. (Refer to...) Figure 6 In addition to the current comparator 602, the voltage glitch detector 600 also includes a voltage sensor that detects voltage spikes via V. REF The voltage glitches isolation filter 606 is coupled to the voltage reference (V) of the current comparator. REF Circuit 604 is connected in series to the output (V) of the current comparator. OUT The chip uses a first inverter 608a and a second inverter 608b to generate voltage glitch detection pulses (PULSE) and voltage glitch detection pulse complements (PULSE_b), as well as a power supply voltage glitch isolation filter 610. The chip's power supply voltage (VDD) is provided to the current comparator 602 through the power supply voltage glitch isolation filter 610. REFCircuit 604 and inverters 608a and 608b. V REF The voltage glitch isolation filter 606 includes a resistor-capacitor (RC) filter (comprising resistor R1 and capacitor C1) to significantly reduce the filtered reference voltage (VDD) caused by fast voltage glitches on VDD. REF-RC (relative to V) REF The power supply voltage glitch isolation filter 610 also includes a resistor-capacitor (RC) filter (including resistor R2 and capacitor C2), which significantly reduces functional interference variations in the power supply voltage (VDD) caused by fast voltage glitch. The voltage glitch isolation filter 610 is designed to even, or particularly, reduce VDD when it rapidly slopes down to subCMOS or negative voltage levels. RC The voltage level is maintained at which the voltage glitch detector 600 and current comparator 602 are fully operational. The power supply voltage glitch isolation filter 610 also includes a diode (D) coupled in parallel with a resistor (R2) to prevent VDD from dropping below V... VOLTAGE-GLITCH Achieving VDD during rapid ramp-up (e.g., in the case of repetitive voltage glitches or SCA). RC The rapid recovery, which attempts to achieve by means of VDD, etc. RC The filtered power supply is degraded to below the operating level on average, thus damaging the filtered power supply. This is especially true when VDD is expected to be low. RC In situations where a rapid return to full CMOS operating levels is required, such as when VDD quickly returns to the level before the voltage spike, the diode (D) also supports rapid power-up.

[0052] V REF Circuit 604 includes circuits series coupled to VDD RC The first pair of pMOS 612 and nMOS 614 are connected to ground. The gate of nMOS 614 receives a fine-tuned voltage glitch signal (V) from the reference voltage generator 425 or the voltage glitch detector 420 in the voltage glitch detection block 418. GLITCH-Trimmed ). As the V of nMOS 614 GS-NMOS The reference voltage induces an I in the nMOS 614. VOLTAGE-GLITCH Drain-source current (I DS This, in turn, applies the same current to pMOS 612. Transistor pMOS 612 is connected to pMOS 616 as a current mirror in a current mirror configuration, and therefore pMOS 616 acts as a current mirror with a current bias equal to I... VOLTAGE-GLITCH The current source of the current. Due to the gate (V) of the pMOS 612 REF ) is connected to its drain, so it is relative to VDD RC The gate voltage (equal to the gate-source voltage of the pMOS 612) GS-PMOSDirectly depends on I VOLTAGE-GLITCH And therefore depends on V VOLTAGE-GLITCH-TRIMMED Transistors pMOS 612 and pMOS 616 are connected via V REF The resistors (R1) of the voltage glitch isolation filter 606 share and / or are coupled to their gate voltages (their gate voltages are V respectively). REF and V REF-RC And when a voltage spike is introduced on the supply voltage (VDD), through V REF The current in circuit 604 will immediately change to be the same as I. VOLTAGE-GLITCH They are fundamentally different, and therefore, VDD RC -V REF This will also fundamentally change the target current of the current source pMOS 616 in the current comparator 602 (the target current depends on VDD). RC -V RTF-RC It will remain stable for a sufficient period of time to maintain the target current of the current source pMOS 616 and enable the current comparator to detect whether a destructive voltage spike has occurred.

[0053] In addition to the pMOS 616, the current comparator 602 also includes a series-coupled component on VDD. RC The nMOS transistor (nMOS 618) is connected to ground. The gate of the nMOS 618 receives a non-isolated supply voltage (VDD), making the gate-source voltage across the nMOS essentially equal to the supply voltage (VDD). If the supply voltage (VDD) is affected by voltage glitches, causing VDD to drop below VDD... VOLTAGE-GLITCH Then the gate-source voltage (V GS-NMOS The current will also decrease, thus reducing the current through the nMOS 618 and lowering the output (V) of the current comparator 602. OUT Move to logic high or "1". Conversely, if VDD is higher than or greater than VDD, move to logic high or "1". VOLTAGE-GLITCH The output of comparator circuit 602 (V) OUT It can be changed to or remain logically low or "0".

[0054] Figure 7 This demonstrates suitability for use with any of the aforementioned voltage glitch detectors and is applicable to Figure 4 A schematic diagram illustrating an embodiment of the voltage glitch protection or isolation latch 700 of the voltage glitch detection block 418 shown. (Refer to...) Figure 7 The voltage glitch isolation latch 700 typically includes a set / reset (S / R) latch 702 coupled to the chip power supply voltage (VDD) via a power supply voltage glitch isolation filter (GIF) 716 and a sample-and-hold (S&H) circuit 718, and an inverter 706 coupled to a single output of the S / R latch.

[0055] In the illustrated embodiment, the S / R latch circuit 702 is a bistable latch similar to an SRAM (Static Random Access Memory) cell. However, it should be understood that the S / R latch circuit 702 can alternatively be implemented using any known logic structure that provides a latch with set / reset functionality. The latch also includes a pair of back-to-back inverters 708a and 708b, a pair of transistors (including a first nMOS 710 and a second nMOS 712 series coupled between ground and the first side of the inverters), and a third nMOS transistor 714 coupled between ground and the second side of the inverters. The third nMOS transistor 714 serves as the output of the S / R latch 702 to output a voltage glitch pulse-latched signal.

[0056] The gate of the first nMOS 710 is used as the reset input of the S / R latch 702, and an inverter 719 is used to... Figure 4 The first logic gate 424 in the system reset block 416 receives the SYS_RESET_B signal. The gate of the second nMOS 712 is used as the first input and coupled to the output of the voltage glitch detector 600 to receive the voltage glitch detection pulse complement (PULSE_b), ensuring that the voltage glitch protection S / R latch 702 will not be reset due to chip reset as long as the voltage glitch detector output displays VOLTAGE-GLITCH_PULSE, and the PULSE_Latched signal will be displayed as long as VOLTAGE-GLITCH_PULSE is active. The gate of the third nMOS 714 is used as the second input and coupled to the output of the voltage glitch detector 600 to receive the voltage glitch detection pulse (PULSE).

[0057] Circuit 704 includes a power supply voltage glitch isolation filter 716 and an S&H circuit 718. The power supply voltage glitch isolation filter 716 includes a resistor R coupled in parallel with the chip power supply voltage (VDD) and coupled to ground through a first capacitor C1, and a first diode D1. (As mentioned above...) Figure 6 The description of V REF Voltage glitch isolation filter 606 and power supply voltage glitch isolation filter 610, power supply voltage glitch isolation filter 716 are designed to isolate VDD. RC-S&H Isolation from high-frequency variations in the supply voltage (VDD) caused by voltage glitches. The S&H circuit 718 includes components series-coupled to the chip supply voltage (VDD) and VDD. RC-S&H The second diode D2 is coupled to VDD. RC-S&HA second capacitor C2 is connected to ground, and a pair of pMOS transistors 720a and 720b are coupled between the first capacitor C1 and the second capacitor C2. These pMOS transistors 720a and 720b act as PMOS switches in the S&H switch. The gates of the pMOS transistors 720a and 720b are connected in parallel to the output of the inverter 706 to receive the PULSE_Latched signal. Once a voltage spike is detected by the voltage spike detector 600 and a PULSE_Latched signal is generated, the PULSE_Latched signal turns off the pMOS transistors 720a and 720b, reducing the voltage (VDD) supplied to the S / R latch 702 and the inverter 706. RC S&H It is isolated from VDD and allows the glitch isolation latch 700 to provide its own power supply voltage, thereby isolating the voltage glitch isolation latch from extreme voltage glitch conditions and increasing the reliability of the voltage glitch detection and protection circuit.

[0058] Now refer to Figure 8 Describes the generation of a reference voltage (V) for a voltage glitch detector based on voltage or current. REF Alternative implementations of the circuit. Specifically, Figure 8 This is a schematic diagram illustrating an implementation of a four-transistor voltage adder that utilizes voltage mirroring technology to provide a reference voltage to a voltage glitch detector that is twice as high as the maximum available on-chip reference voltage (typically about 1.2V). (Refer to...) Figure 8 The voltage mirror 800 typically includes a first pair of substantially identical nMOS transistors 802 and 804 connected in series between the voltage supply VDD and ground, and a second pair of substantially identical pMOS transistors 806 and 808 connected in parallel with the first pair of transistors. The gate of the first nMOS transistor 802 is coupled to a first input voltage (VDD). IN-N The gate of the second nMOS transistor 804 is coupled to its drain to function as a diode with characteristics similar to those of the nMOS transistor 802. The gate of the first pMOS transistor 806 is coupled to the second input voltage (VI). N-P The gate of the second pMOS transistor 808 is coupled between the source of the second nMOS transistor 804 and the drain of the first nMOS transistor 802. The bulk or body junctions of all devices 802 to 804 are connected to their respective source nodes.

[0059] During operation, the gate-source voltage (V) of the second nMOS transistor 804 GS ) equals V as nMOS 802 GS-N_802 V IN-NAnd is voltage mirrored to the gate of the second pMOS transistor 808, causing V GS-P_808 =V GS-N_804 This also causes the gate-source voltage (V) of the first pMOS transistor 806 to increase. GS ) equals the gate-source voltage (V) of the first nMOS transistor 802 GS ). Compared with a conventional current mirror (where the drain-source current (I) DS The current matching (mirror image from one side of the mirror to the other) is different. In voltage mirror 800, the current (I) through the first nMOS transistor 802 and the second nMOS transistor 804 is different. N-BIAS The magnitude of ) is different (higher or lower) than the current (I) passing through the second pMOS transistors 806 and 808. P-BIAS ), and the matching from one side to the other is V. GS Instead of I DS Therefore, in V IN-N Greater than the nMOS threshold voltage (V TN ) and pMOS threshold voltage V TP The maximum value and V IN-P When the absolute value of Vtp is greater than a negative value (-|VTP|), the output of the voltage mirror 800 (V OUT ) will be V IN-N and V IN-P The sum. This means that for the range of the absolute value of Vtp (|Vtp|), the input to the pMOS 806 V IN-P It can be negative, and the circuit will still act as a voltage adder.

[0060] Figure 8 The voltage mirror 800 can provide a reference voltage between 900mV and approximately 2.3V. REF It can be adjusted in 50mV steps or increments, where V IN-N Within the range of approximately 900mV to 1.15V, and V IN-P Within the range of 0V to 1.15V. For example, when VDD is 2.4V entering voltage mirror 800, V... IN-N It is 900mV, and V IN-P With a voltage of 0V, the output is 900mV. When VDD enters the voltage mirror 800, it is 2.4V. IN-N It is 1.15V, and V IN-P With a voltage of 1.1V, the output is 2.25V.

[0061] In addition to having an output voltage that can be adjusted in 50mV steps or increments, the Voltage Mirror 800 also features a high-impedance input, requires no feedback or current input, can be manufactured using a variety of different manufacturing techniques, and has a small area without resistors.

[0062] Figure 9A and Figure 9B This is a schematic diagram illustrating an embodiment of a current mirror circuit 900 suitable for generating a reference current and for use in voltage glitch detection and protection circuits.

[0063] Figure 9A A schematic diagram of an embodiment of the current mirror circuit 900 is shown. (Refer to...) Figure 9A The current mirror circuit 900 includes a two-stage folded current mirror 904 having at least two stages. The two-stage folded current mirror 904 includes a first branch or auxiliary branch 906, a second branch or first fold (fold-1908), and a third branch or second fold (fold-2910). The auxiliary branch 906 includes components coupled to the power supply voltage (VDD) and the auxiliary current source N. CURR-AUX The first pMOS transistor between 914 (P AUX-1 912). The second branch or first fold (fold-1 908) includes a second pMOS transistor (P) series coupled between VDD and ground. Fold-1 916) and the first nMOS transistor (N Fold-1 918), where the current source N CURR-SRC 920 is coupled between ground and the first node 922 between the transistor. The third branch or second fold (fold-2 910) includes a second nMOS transistor (N) between VDD and ground. Fold-2 926) The third pMOS transistor (P) is connected in series. Fold-2 924). The current mirror 904 also includes coupling to P. Fold-2 924 transistors and N Fold-2 The second node 930 between transistors 926 and the first nMOS mirror transistor (N) to ground MIRROR-1 928), and a second mirror transistor (N) coupled between the client / load 934 and ground. MIRROR-2 932). N Fold-1 918 and N MIRROR-1 The gate of 928 is coupled to the first node 922, and N Fold-2 926 transistors and N MIRROR-2 The gate of transistor 932 is coupled to node 930. All pMOS transistors—P AUX-1 Transistor 912, P Fold-1 Transistor 916 and P Fold-2The gate of transistor 924 is coupled in parallel to the auxiliary current source N. CURR-AUX 914.

[0064] In operation, each stage or fold of 908, 910 allows the saturation voltage of the previous stage to be reduced to N in that stage. Fold-1 918 transistors and N Fold-2 Threshold voltage (V) of 926 transistor TH-N This enables the use of a high saturation voltage input current source N. CURR_SRC 920, while simultaneously providing a low-saturation voltage output current source to the client / load 934. It should be noted that I... AUX-1 >I IN Therefore I AUX-1 -I IN High enough to make N FOLD-1 918 and N MIRROR-1 The 928 can be used as an accurate current mirror.

[0065] Figure 9B A voltage glitch detector 902 is shown, incorporating a current mirror circuit 900 into a voltage glitch detection and protection circuit. (Refer to...) Figure 9B The voltage glitch detector 902 includes a current comparator 936, which transmits voltage through a voltage sensor. REF The voltage glitches isolation filter 940 is coupled to the voltage reference (V) of the current comparator. REF Circuit 938, series coupled to the output (V) of the current comparator OUT The chip includes a first inverter 942a and a second inverter 942b, as well as a power supply voltage glitch isolation filter 944. The chip's power supply voltage (VDD) is supplied to the circuitry and sub-circuit of the voltage glitch detector through the power supply voltage glitch isolation filter 944. A current comparator 936 includes components series-coupled to VDD. RC The pMOS 946 and nMOS transistor 948 are connected to ground. The gate of the pMOS 946 is connected to V... REF Voltage glitch isolation filter 940 is coupled to V REF Circuit 938, and the gate of nMOS 948 is coupled to VDD. V REF The voltage glitch isolation filter 940 includes a resistor-capacitor (RC) filter to significantly reduce the reference voltage (V) caused by fast voltage glitch on VDD. REF (relative to VDD) RC The power supply voltage glitch isolation filter 944 also includes a resistor-capacitor (RC) filter, which significantly reduces functional interference variations in the power supply voltage (VDD) caused by fast voltage glitch.

[0066] V REFCircuit 938 includes a series connection to VDD RC The pMOS 950 and nMOS 952 are connected to ground, among which... Figure 9A The current mirror circuit 900 is coupled between pMOS 950 and nMOS 952. In the voltage glitch detector embodiment described above, the gate of nMOS 952 receives the fine-tuned voltage glitch signal (V). GLITCH Trimmed), which induces an energy equal to I in nMOS 952. VOLTAGE-GLITCH Drain-source current (I DS This current is then connected to the pMOS 950 through the current mirror circuit 900, enabling the pMOS 950 to act as a current mirror with a current equal to I. VOLTAGE-GLITCH The current source of the current and generates V REF The current mirror circuit 900 enables the voltage glitch detector 902 to detect voltage spikes very close to V. GLITCH-Trimmed The voltage glitches that start with the VDD voltage, while still maintaining accurate V... GLITCH-Trimmed Voltage detection point. At VDD only compared to V... GLITCH-Trimmed At a high voltage of 100mV, due to VDD RC There is not enough voltage range between VDSAT and ground to sustain VDSAT. N_952 +VTH P_950 +VDSAT P_950 Therefore, it cannot meet the high saturation voltage VDSAT of the current source nMOS 952. N_952 This drives the current source nMOS 952 into the linear region, which reduces its IL. VOLTAGE-GLITCH Current and cause the detection voltage to drop to V GLITCH-Trimmed the following.

[0067] Figure 10A and Figure 10B It is shown that it consists of, for example, Figure 6 and Figure 7 The diagram shows the timing of the signals generated when a voltage glitch detection and protection circuit detects a voltage glitch event. Specifically, Figure 10A The signal generated by detecting a short voltage glitch event of 20 ns is shown, while Figure 10B The signal generated by detecting a long voltage glitch event of 200 ns is shown.

[0068] Reference Figure 10A At the initial time (t0), in the top diagram, the chip's main power supply voltage (VDD 1002) begins to drop rapidly from the initial voltage level (VDD) due to a short-circuit voltage glitch event. Simultaneously, at (t0), the isolation power supply voltage (VDD) of the comparator in the voltage glitch detector...RC 1004) and isolation reference voltage (V REF-RC (1006) also begins to decrease, but due to the voltage glitches and isolation filter, the decrease is much slower. Typically, V... REF-RC 1006 decreases at a rate or slope of less than approximately 20 mV / in over 40 ns, and it should be noted that as long as VDD... RC 1004 maintains a minimum detector operating voltage of approximately 1.4V (VDD). DET-OP-OK The voltage glitch detector will continue to operate and can respond to voltage glitch events.

[0069] Specifically or alternatively, the current comparator includes a pMOS (e.g., Figure 6 In the embodiment shown, the pMOS616 transistor input is... Figure 10A The top diagram shows V REF-RC The waveform of 1006 is actually VDD. RC -V REF-RC The result is because V REF-RC It is the gate of the pMOS in the current mirror configuration (which is coupled to VDD via a large capacitor (C)). RC The input will be followed by VDD for high-frequency changes. RC Change. Therefore, VDD RC -V REF-RC relative to VDD-V REF The change is small and will decrease at a rate or slope of less than approximately 20 mV / in over 40 ns, and only as long as VDD... RC 1004 remains in VDD DET-OP-OK The above applies, and the glitch detector will continue to operate and can respond to glitch events.

[0070] Next, at time (t1) approximately 20 ns after the voltage glitch width, the voltage glitch detector generates a voltage glitch detection pulse (PULSE1008) with a pulse width of at least approximately 10 ns, which is coupled to the voltage glitch protection latch, as shown by dashed arrow 1010. Shortly thereafter, starting at time (t2), the voltage glitch protection latch generates a voltage glitch PULSE_Latched signal (PULSE_LATCHED 1012), which, along with PULSE, is coupled to the PU / PD controller, as shown by dashed arrow 1014. Finally, at time (t4), the PU / PD controller generates a global reset signal 1016 to safely power on the devices and circuitry on the security chip according to a predefined power-on reset (POR) sequence and reset the voltage glitch protection latch, as shown by dashed arrow 1018. It should be mentioned that... Figure 10AAs shown in the diagram, PULSE 1008 can appear earlier than 20ns, so PULSE_LATCHED 1012 can appear after PULSE 1008 with a delay of less than 10ns.

[0071] Figure 10B The following timing diagram illustrates the signal generated by detecting a long voltage glitch event of >200ns, and shows the ability of a voltage glitch protection latch, including sample-and-hold (S&H) circuitry, to ensure a safe system reset after a long voltage glitch event when signals from blocks and other circuits in the voltage glitch detection and protection circuitry become invalid during the voltage glitch event.

[0072] Reference Figure 10B At time (t0), the chip's main power supply voltage (VDD 1002) begins to drop rapidly due to a sharp and prolonged voltage glitch event. The two isolated power supply voltages (VDD 1002 and VDD 1002) of the voltage glitch detector and the voltage glitch protection latch are respectively... RC 1004, VDD RC-S&H 1020) and the isolation reference voltage (V) of the comparator in the voltage glitch detector. REF-RC 1006) also begins to decrease, but due to the voltage glitches and isolation filter, the decrease is much slower. As mentioned above, as long as VDD RC 1004 maintains the minimum detector operating voltage (VDD) DET-OP-OK Above this point, the voltage spike detector will continue to operate. At time (t1), VDD 1002 drops to V VOLTAGE-GLITCH Below, and at time (t2), approximately 20 ns later, the voltage glitch detector generates a rising edge of PULSE 1008, which is coupled to the voltage glitch protection latch, as indicated by the dashed arrow 1010 at time (t3). At approximately the same time (t3), the voltage glitch protection latch generates a rising edge of PULSE_LATCHED 1012. The increased power required by the voltage glitch protection latch due to the generation of PULSE_LATCHED 1012 will affect the isolation voltage from the power supply to the voltage glitch protection latch (e.g., ...). Figure 7 VDD in RC S&H Reduce the voltage to a slightly lower level while safely maintaining it at the predetermined minimum effective voltage (VDD). VALID The above. Due to the rising edge of PULSE_LATCHED 1012, the voltage glitch protection latch isolation power supply is disconnected from the main chip power supply, thereby enabling the sample-and-hold circuit (e.g., Figure 7 The S&H circuit 718 in the middle can keep the internal power supply at VDD. VALIDThis hold time is sufficiently long to ensure that the PULSE_LATCHED 1012 signal is received in the PU / PD controller once the voltage glitch event has ended. Sufficient hold time can include, for example, >14 μsec. Figure 10B The purpose of the example shown should be noted that VDD VALID It can be lower than VDD DET-OP-OK Furthermore, the voltage can be several hundred millivolts higher than VTN or VTP, which is sufficient to trigger a reset. It should also be noted that 14 μsec is sufficient because for voltage glitches lasting longer than 14 μsec, other reset detectors (e.g., the second CMOS level detector 414b) will generate SYS_RESET_B after VDD recovers. Note that, unlike short voltage glitches, the voltage glitch detector will continue to output PULSE1008 until VDD recovers. RC 1004 dropped to VDD DET-OP-OK the following.

[0073] At time (t3), the voltage glitch protection latch generates the PULSE_LATCHED 1012 signal, which is coupled to or attempts to be coupled to the PU / PD controller, as indicated by dashed arrow 1014. However, when VDD 1002, which supplies power to both the PU / PD controller and the CMOS level detector (through which the PULSE_LATCHED 1012 signal is coupled), drops to VDD... VALID The global reset signal 1016 is not generated until time (t7). As described above, at the rising edge of the PULSE_LATCHED 1012 signal, the voltage glitch protection latch power supply VDD is latched using the S&H circuit 718. RC-S&H 1020 is disconnected from power supply VDD 1002, allowing S / R latch 702 to store logic data for a sufficiently long time after the voltage glitch ends, and powering the CMOS level detectors, and the PU / PD controller to regain a valid CMOS level. Since PULSE_LATCHED 1012 retains its valid logic value until after the voltage glitch, once the voltage glitch event ends, a valid SYS_RESET_B is received in the PU / PD controller, and a valid global reset signal 1016 is generated. It should also be noted that 14 μsec is sufficient, because for voltage glitch durations longer than 14 μsec, other reset detectors (e.g., the second CMOS level detector 414b) will generate SYS_RESET_B after VDD recovers.

[0074] At time (t4), VDD RC 1004 dropped to VDDDET-OP-OK Furthermore, at time (t5), the output of the voltage glitch detector becomes unreliable due to the invalid CMOS level between time (t5) and time (t6).

[0075] Finally, at time (t6), VDD 1002 starts from the minimum voltage - glitch voltage (VDD). VOLTAGE-GLITCH-MIN Rise above VDD DET-OP-OK The level, and at time (t7) it is higher than VDD. VALID The power supply to the PU / PD controller and the CMOS level detector (through which the PULSE_LATCHED 1012 signal is coupled) is able to resume operation, and a global reset signal 1016 is generated, as shown by arrow 1022.

[0076] Figure 11 This is a waveform diagram of a side-channel voltage glitch (SCA) attack on a security chip, including the voltage glitch detection and protection circuitry and the signals responding to it, illustrating the circuitry's ability to prevent SCA. (Refer to...) Figure 11 At the initial time (t0), the attack caused the chip's supply voltage (VDD 1102) to begin dropping rapidly at a slope of approximately 1V / ns. The supply voltage quickly fell outside the range of the effective CMOS voltage levels indicated by the shaded box 1104, and at time (t1), VDD had dropped to the predefined voltage glitch voltage (V...). VOLTAGE-GLITCH Or below the jump point. As the supply voltage continues to drop into the range of invalid CMOS voltage levels indicated by the shaded box 1106, the analog and digital devices (including memory devices) in the security chip and the devices in the voltage glitch detection and protection circuit (e.g., undervoltage detector) become inoperable or are damaged by invalid CMOS levels or data, as indicated by area 1108 in the operating state indication in the lower figure. As indicated by the inflection point 1112 on line 1110, when the voltage glitch detector 420 and the first glitch protection S / R latch 422a begin to supply the PULSE-OR-PULSE_Lattched signal 1114 to the CMOS level detector, the sample-and-hold (S&H) circuit sets the supply voltage (VDD) of the voltage glitch protection latch indicated by line 1110. DET-LatchThe voltage remains stable, and the supply voltage begins to drop at the same time (t0) as the chip's supply voltage (VDD 1102), although the rate of drop is slower due to the voltage glitch isolation filter. At essentially the same time (t2), the voltage glitch detection block 418 (and more specifically, the voltage glitch protection latch 420a) continues to operate at a valid CMOS level, thereby providing the PULSE-OR-PULSE_Lattched signal 1114 for the remainder of the voltage glitch event, as shown in the middle figure.

[0077] Next, at time (t3), after a voltage glitch width or power-off time ranging from approximately 20 μs to up to approximately 25 μs, the voltage glitch event ends, and the chip's power supply voltage (VDD 1102) begins to rise sharply. Between time (t3) and time (t4), as the chip's power supply voltage (VDD 1102) rises towards the valid CMOS level, the latched voltage glitch detection signal 1114, coupled to the PU / PD controller via the CMOS level detector 414a, causes the PU / PD controller in the voltage glitch detection and protection circuit to execute a full system reset sequence starting at time (t4). As shown in the figure below, as indicated by region 1116, during SCA, data in the security domain is safely erased and / or protected from damage.

[0078] Figure 12 This is a schematic diagram illustrating an alternative embodiment of the voltage glitch detector 1202 and voltage glitch detector latch 1204 capable of operating in the negative domain. It should be understood that the voltage glitch detector 1202 and voltage glitch detector latch 1204 can be used, for example, in the voltage glitch detection and protection circuit described above, or in place of the voltage glitch detector and voltage glitch detector latch, or added to and coupled in parallel with the previously described voltage glitch detector and voltage glitch detector latch. It should be clear that both the voltage glitch detector 1202 and voltage glitch detector latch 1204 include power supply isolation filters 1213 and 1230, which are respectively connected to power supply isolation filters VDD-VDD. NEG-TRIGGER The behavior is similar to VDD RC -GND and VDD-V NEG-LATCH The behavior is similar to VDD RC S&H-GND performs similar operation to power isolation filters 610 and 716. In this case, the power isolation filter still filters for mains power (VDD) variations, but achieves this by effectively lowering the circuit's local ground to a negative voltage, thereby maintaining the circuit at its operating voltage relative to the VDD supply during voltage spikes. Instead of using resistors, the isolation filter relies on the RDS resistors of nMOS devices 1212 and 1232. In this alternative implementation of the voltage spike detector and latch (1202, 1204, respectively), both power isolation filters (1213, 1230, respectively) use sample-and-hold switches (nMOS 1212, 1232, respectively) to adjust their relative voltage to VDD (VDD-VDD, respectively) at the falling edge of the spike detection PULSE_LATCHED_NEG_B. NEG-TRIGGER and VDD-V NEG-LATCH The internal negative power supply domain is sampled. It should also be mentioned that the bulk of nMOS devices 1212 and 1232 is connected to their drains, and this connection forms a diode that functions similarly to the diodes in the power supply voltage glitch isolation filter 610 and circuit 704, to enable fast recovery of the internal negative power supply domain when the VDD power supply recovers from a glitch or performs a fast power-up. Finally, it should be noted that nMOS switches 1212 and 1232 function as resistors in the RC filter using their RDS, as sample-and-hold switches, and as fast recovery diodes, all within a single device, making this alternative implementation more area-efficient.

[0079] Reference Figure 12 The voltage glitch detector 1202 typically includes: having a V REF-RC The input current comparator 1206, which is connected to V REF The glitch isolation filter 1210 is coupled to the reference (V) REF The V generated by circuit 1208 REF Voltage; has a negative domain (V) Neg-Trigger The power isolation filter 1213 includes an nMOS transistor 1212 and a capacitor (C). Neg-Trigger ).Notice, Figure 12 The current comparator 1206 shown is similar in design and function to Figure 5 The current comparator shown has an output that is active in the opposite polarity. (See reference...) Figure 12The current comparator 1206 includes a pMOS transistor 1214 and an nMOS transistor 1216. The pMOS transistor 1214 includes a gate coupled to ground, a source coupled to VDD and an N-well or body contact, and a drain coupled to the drain of the nMOS transistor 1216. The nMOS transistor 1216 is coupled between the pMOS transistor 1214 and the negative domain power supply 1213 (VDD). Neg-Trigger Between ) . The gate of nMOS transistor 1216 is connected to V REF Voltage glitches isolation filter 1210 is coupled to V REF Circuit 1208, to receive V REF-RC The reference voltage allows the nMOS transistor 1216 to act as a reference voltage, which provides a voltage spike current (I0) from it. VOLTAGE-GLITCH The pMOS transistor 1214 provides the current source for VDD (IDD). VDD-CHIP V REF The voltage glitches isolation filter 1210 is a resistor-capacitor (RC) filter, including coupling at V REF The resistor (R) between the output of circuit 1208 and the gate of nMOS transistor 1216 REF ) and coupled to the negative domain power supply 1213 (V Neg-Trigger ) and reference resistor (R) REF The capacitor (C) between the junction of the gate of the nMOS transistor 1216 and the current comparator 1206. REF V REF Circuit 1208 includes a first nMOS transistor 1218 and a second nMOS transistor 1220 connected in series between VDD and ground, and a pMOS transistor 1222 connected between VDD and a third nMOS transistor 1224. The pMOS transistor 1222 is also coupled to the negative domain power supply 1213 (V Neg-Trigger) The third nMOS transistor 1224 is used as V. REF The circuit output, and has a voltage across V. REF Voltage glitches isolation filter 1210 is coupled to the gate (V) of nMOS transistor 1216 in current comparator 1206. REF-RC The source and gate of ), and coupled to the negative domain power supply (V Neg-Trigger The drain of the third nMOS transistor 1224. The third nMOS transistor 1224 acts as a current mirror for the nMOS transistor 1216 and provides a current bias reference that allows the nMOS transistor 1216 to have voltage glitch current (I) within the current comparator 1206. VOLTAGE-GLITCHThe current source of the current comparator 1206 is the pMOS transistor 1216. It should be mentioned that the VREF circuit 1208 utilizes a voltage mirroring technique between the nMOS 1220 and pMOS 1222 to align the current source of the current comparator 1206 (nMOS transistor 1216) to have an IL relative to the current generated by the pMOS 1214. VDD I VOLTAGE-GLITCH Electric current.

[0080] Reference Figure 12 The voltage glitch detector latch 1204 typically includes a pMOS transistor 1226, which serves as the set_b input of the latch and is connected between the chip power supply voltage (VDD) and the output PULSE_LATCHED_NEG of the first inverter 1228a in a pair of back-to-back inverters 1228a and 1228b. The pMOS transistor 1226 includes the gate of the shared drain PULSE_B of the nMOS transistor 1216 and pMOS transistor 1214 coupled to the current comparator in the glitch detector 1202 to receive the glitch detection pulse complement (PULSE_B). The inverters 1228a and 1228b are coupled between VDD and ground and are also coupled to ground via a sample-and-hold (S&H) circuit 1230. The S&H circuit 1230 typically includes an nMOS transistor 1232 acting as a switch, coupled between the first inverter 1228a, the second inverter 1228b, and ground, and an NMOS transistor 1232 with its drain V connected to it. Neg-Latch The sample-and-hold capacitor (C) between VDD and VDD Neg-Latch The voltage glitch detector latch 1204 also includes a third inverter or output inverter 1234 coupled between VDD and ground, and a second pMOS 1236 coupled between VDD and the gates of the transistors in the first inverter 1228a and the third inverter 1234, the gates of which are also the PULSE_LATCHED_NEG_B output of inverter 1228b. The gate of the second pMOS 1236 receives the RESET_B signal from a complementary system reset signal (e.g., SYS_RESET_B in 400) and serves as the reset_b input of the voltage glitch detector latch 1204.

[0081] pMOS transistor 1226 has a gate that shares a drain (PULSE_B) with nMOS transistor 1216 and pMOS transistor 1214 coupled to the current comparator, and serves as the set_b input of voltage glitch protection latch 1204, which is similar to setting PULSE_LATCHED_NEG to "1" (or VDD) during glitch detection. Figure 7The medium voltage glitch protection latch 700 uses the non-inverting Glitch-Det-Pulse input of the nMOS transistor 714. During a voltage glitch, the negative domain power supply 1213 (V) of the voltage glitch detector 1202 is used. Neg-Trigger The negative domain power supply (V) of the voltage glitch isolation latch 1204. Neg-Latch These are respectively used as the isolation ground or negative domain power supply for voltage glitch detectors and voltage glitch isolation latches. The isolated ground power supply (V... NEG-Trigger and V NEG-Latch This will cause the ground of voltage glitch detector 1202 and voltage glitch isolation latch 1204 to slope down to a negative voltage at a rate similar to or slightly lower than the sloping rate of voltage glitch on the VDD power supply. Therefore, the isolated ground power supply (VDD) NEG-Trigger and V NEG-Latch This will ensure that the voltage glitch detector 1202 and the voltage glitch isolation latch 1204 function for at least the first 20 ns of a voltage glitch. The drain-to-source resistor (R) of nMOS transistors 1212 and 1232 is used. DS This achieves ground isolation, where both the source and the N-well or body contact are coupled to V. NEG(Trigger / Latch) power supply.

[0082] During the voltage glitch, both nMOS transistors 1212 and 1232 initially act as transistors with sufficiently large resistance (R) during the first 20 ns of the voltage glitch. DS The resistor element is used to completely isolate the internal V. NEG(Trigger / Latch) Node. nMOS transistors 1212 and 1232 connect two V on the negative edge of the internal node of SR latch 1204 in PULSE_LATCHED_NEG_B. NEG(Trigger / Latch) The power supply is disconnected from ground to act as a sample-and-hold switch.

[0083] V of voltage glitch detector 1202 REF Circuit 1208 utilizes the previously combined Figure 8 The voltage mirroring technique described is used to make V REF The circuit generates I in 1208 VOLTAGE-GLITCH Specifically, the VREF trimmer glitch voltage (V) of the nMOS transistor 1218 GLITCH This causes the drain to source (I) of the nMOS transistor 1218 to be connected. DS This forces the I of the nMOS transistor 1220 to... DS I is the nMOS transistor 1218 DS This reduces the gate-to-source voltage (V) of the nMOS transistor 1220. GS It is basically equal to the V of the nMOS transistor 1218. GS-1218 It is essentially equal to the glitch voltage (V)GLITCH Then, this voltage is mirrored to pMOS transistor 1222, causing V to... GS-1222 Basically equal to the glitch voltage (V) GLITCH This causes the pMOS transistor 1222 to be essentially equal to I. VOLTAGE-GLITCH Drain-to-source current (I DS Then, the drain-to-source current (I) of the pMOS transistor 1222 DS The voltage is applied to the nMOS transistor 1224, which generates the nBIAS voltage, which is the VREF input of the current comparator 1206 of the voltage glitch detector 1202.

[0084] The reference voltage (VREF) of the nMOS transistor 1224 is determined by V. REF The voltage glitch isolation filter 1210 isolates and is coupled to the V of the nMOS transistor 1216. REF-RC gate, when I GLTICH >I VDD At that time, its resistance to I from pMOS transistor 1214 VDD Pull-up current and pull-down I GLTICH Similar to Figure 6 The current comparator 602 in the middle. Figure 6 In the current comparator 602, the current comparator generates a voltage glitch detection pulse with a rising edge pulse. Figure 12 In a circuit capable of operating in the negative domain, current comparator 1206 generates a voltage glitch detection pulse with a falling edge. This pulse is latched by voltage glitch isolation latch 1204 and delivered as a positive edge PULSE_LATCHED to the RESET output of the voltage glitch isolation latch. Similar to... Figure 7 The voltage glitch isolation latch shown uses the negative edge of the internal signal PULSE_LATCHED_NEG_B to generate a voltage glitch detection pulse for latching. This affects the latch's isolation power supply (V). Neg-Latch The circuit samples and holds the signal. However, the voltage level of the isolation ground in this circuit is negative and will be held relative to the VDD supply voltage for a sufficient time to enable the "0" voltage level of the internal signal PULSE_LATCHED_NEG_B. This subsequently enables the "1" at the PULSE_LATCHED output of latch 1204 for a sufficient time to force a system reset at the end of the voltage spike. The latch output PULSE_LATCHED is coupled to... Figure 13B The alternative first CMOS level detector shown has a negative reset input capable of resetting the PU / PD controller 402. Figure 4In section 414a), the PULSE_LATCHED_NEG output of latch 1204 and the VNEG output of glitch detector 1202 are respectively coupled to... Figure 13B The matched input in the alternative CMOS level detector. A VNEG output is required because PULSE_LATCHED_NEG is generated from the VNEG field and is relative to VNEG, not ground.

[0085] In another embodiment, such as Figure 13A and Figure 13B As shown, at least the first CMOS level detector in the system reset block includes a reservation circuit to recall the detected voltage glitches when the system reset block is powered back on, thereby ensuring a complete and safe system or chip reset even if the voltage glitch detection and protection circuit loses power. (Refer to...) Figure 13A The CMOS level detector 1300 includes an inverter consisting of a strong pMOS transistor 1302 and a weak nMOS transistor 1304 connected in series between the main voltage supply (VDD) and ground, and a switching node 1306 formed between the gates of the pMOS transistor and the nMOS transistor. During normal operation, it has a voltage level higher than VDD. MIN During operation at a stable power supply voltage, the switching node 1306 is biased by an RC divider, which is formed by multiple weak pMOS transistors (collectively referred to as 1308) connected in series between VDD and ground, and a resistor 1310. The resistance of resistor 1310 is chosen to be relatively large (on the order of approximately 5 MΩ) to avoid excessive current and power consumption of the CMOS level detector 1300 during normal operation, i.e., before a power-down event (voltage glitches or a slow drop in VDD).

[0086] During normal operation, the switching node 1306 is at a high voltage or logic 1, and the logic complement (Trip_B) is coupled through delay circuit 1312 and inverter 1314 to provide a logic high or 1 to the SYS_RESET_B output of the CMOS level detector 1300. During a CMOS level reset event, i.e., a reset caused by a slow and relatively long drop in the supply voltage, the switching node 1306 slowly discharges to ground (logic Trip_B logic 0) through resistor 1310. When the switching node 1306 is fully discharged, the strong pMOS transistor 1302 turns on and the weak nMOS transistor 1304 turns off, toggling the logic complement (Trip_B) to logic 1, and after a delay of delay circuit 1312, the CMOS level detector 1300 outputs the SYS_RESET_B signal (logic 0), which causes the PU / PD controller (not shown in the figure) to initiate a reset sequence when the supply voltage recovers to a level higher than the predefined reset voltage.

[0087] During a voltage glitch event, a voltage glitch detection pulse (PULSE) is received in the CMOS level detector 1300. This pulse causes the switching node 1306 to rapidly discharge to the switching setpoint (logic 0), flipping the logic complement (Trip_B) to logic 1. After a delay in the delay circuit 1312, the CMOS level detector 1300 outputs the logic 0SYS_RESET_B signal, causing the PU / PD controller to initiate a complete system reset. In some embodiments, the voltage glitch detection and protection circuitry also includes a voltage glitch protection latch, and the CMOS level detector 1300 also receives a voltage glitch pulse latch (PULSE_LATCHED) signal.

[0088] The CMOS level detector 1300 also includes a hold circuit 1316 to store and recall voltage glitches when power is restored after the CMOS level detector has lost power. Figure 13AIn the illustrated embodiment, the holding circuit 1316 includes a pair of pull-down circuits, each of which includes a plurality of nMOS transistors coupled in parallel between the source / drain (S / D) junction of the weak pMOS transistor 1308 and ground. This causes the PULSE signal coupled to the gate of the nMOS transistor in the first pull-down circuit 1318 and / or the PULSE_LATCHED signal coupled to the gate of the nMOS transistor in the second pull-down circuit 1320 to turn on the weak pMOS transistor 1308, causing the switching node 1306 to discharge rapidly and causing the CMOS level detector 1300 to output the SYS_RESET_B signal, thereby causing the PU / PD controller to initiate a complete system reset. It should be noted that since the switching node 1306 will typically be in a discharged state if given sufficient time at a sufficiently low supply voltage, and the transistors in the pull-down circuits 1318 and 1320 are nMOS, causing the switching node 1306 to discharge to "0" quickly, once the PULSE or PULSE_LATCED signal is activated, the switching node 1306 will remain discharged when the CMOS level detector 1300 is restored to power. This allows it to remember or recall the detected voltage glitches and signal the PU / PD controller to perform a full system reset, thereby ensuring the security chip or device is protected from side-channel voltage glitches or side-channel attacks (SCA). Furthermore, PULSE_LATCHED is maintained at a sufficiently high CMOS level "1" to force the switching node 1306 to be "0" for a sufficiently long time, so that even if PULSE_LATCHED drops below "1", the CMOS level can naturally remain at "0". Finally, the holding circuit 1316 can be reset by SYS_RESET_B, which ultimately forces both the PULSE and PULSE_LATCHED inputs of the nMOS transistor's gate to "0", enabling the weak pMOS transistor 1308 to restore the CMOS level detector 1300 to the same nominal switching point.

[0089] Figure 13B Another embodiment of a CMOS level detector is shown, which includes a holding circuit and is configured to, for example, relate to the above-mentioned... Figure 12 Used together with the negative domain spur detector shown and described. (Refer to...) Figure 13B Note that the CMOS level detector 1301 is basically the same as... Figure 13A The circuit is the same, but the CMOS level detector 1301 is from... Figure 12 The negative domain glitch detector receives PULSE_LATCHED-NEG, V NEG And PULSE-LATCHED, and the transistor of pull-down circuit 1318 is coupled to V. NEG Instead of being coupled to ground.

[0090] Now we will refer to the process. Figure 14 A method is described for operating a voltage spike detection and protection circuit, the voltage spike detection and protection circuit including a voltage spike protection system with a voltage spike detection block, the voltage spike detection block including a voltage spike detector and a voltage spike protection latch, to detect and prevent side-channel voltage spike attacks (SCA) in a security chip or system. (Refer to...) Figure 14 The method begins by providing a main supply voltage (VDD) to the first input of a current comparator in the glitch detector, and a predetermined setpoint voltage (V) based on a second input coupled to the comparator. GLITCH The reference voltage (V) REF (Step 1402). Next, a current (I) is generated from VDD coupled to the first input terminal. VDD ), from V REF Generates glitch current (I VOLTAGE-GLITCH ), and I VDD with I VOLTAGE-GLITCH Compare (step 1404). Determine I VDD Is it less than I? VOLTAGE-GLITCH (Step 1406).

[0091] If I VDD Not less than I VOLTAGE-GLITCH Then steps 1402 and 1404 are repeated because the circuit continues to monitor for voltage glitches in the power supply voltage (VDD). It is worth noting that the circuit also continues to monitor other events in the chip voltage supply (VDD) simultaneously or concurrently, such as the generation of a slow clock signal, undervoltage detector (BOD) reset, and / or CMOS level reset events, without being affected by the voltage glitch detection block or other adverse effects.

[0092] If I VDD Less than I VOLTAGE-GLITCH Then, a glitch detection pulse (PULSE) is generated and coupled to a latch in the glitch detection block and to the system reset block (step 1408). Next, a glitch detection pulse latch (PULSE_LATCHED) signal is generated and coupled to the system reset block (step 1410). As described above, the PULSE_LATCHED signal ensures the generation of a system reset signal (SYS_RESET_B) and its transmission to the PU / PD controller, causing the controller to perform a complete reset of the safety chip, even if the comparator power is subsequently lost. More preferably, the method includes, when generating the PULSE_LATCHED signal, adjusting the isolation power supply voltage (VDD) of the voltage glitch protection latch. RC S&H Sampling and preservation are performed.

[0093] Next, in response to one or both of the PULSE and PULSE_LATCHED signals, a system reset signal (SYS_RESET_B) is generated in the system reset block and coupled to the power-on / power-off (PU / PD) controller to fully and safely reset the sub-circuits and devices in the chip (step 1412).

[0094] Finally, determine whether VDD has been restored to the predetermined minimum supply voltage (VDD). MIN If VDD has recovered, the voltage glitch detection and protection circuit is reset, and the monitoring process continues (step 1414).

[0095] Figure 15 This is a block diagram of a security system or chip 1500, which includes embedded non-volatile memory (eNVM) or flash memory 1502 and a system reset subsystem analog (SRSSA) block 1504 including a voltage glitch protection system 1506 for preventing side-channel voltage glitch attacks (SCA). See reference... Figure 15 The flash memory 1502 includes multiple memory arrays, such as a first memory array 1508 and a second memory array 1510. Each memory array includes an array of non-volatile memory cells, and each memory array is controlled by processing circuitry 1512 integrally formed on the security chip 1500. Typically, the flash memory 1502 also includes a first controller 1514 and a second controller 1516, as well as a voltage / current power supply block 1518. The first controller 1514 and the second controller 1516 are each configured to provide support for read operations and programming and erase operations for the first memory array 1508 and the second memory array 1510, respectively. The voltage / current power supply block 1518 is a versatile mixed-signal block configured to provide the flash memory 1502 with a series of voltage, current, and digital signals / indicators for the different operating modes listed above.

[0096] SRSSA block 1504 includes an implementation of voltage glitch protection system 1506, such as one of the implementations described above, and is coupled to each block or circuit of processing circuitry 1512 and flash memory 1502. It is configured to provide a global reset signal to each block or circuit to perform substantially the same POR reset scheme, regardless of the event causing the reset. Voltage glitch protection system 1506 ensures that a safe reset is performed under all conditions of power ramp and level, protecting security chip 1500 from any and all side-channel voltage glitch attacks without affecting the performance of security chip or flash memory 1502.

[0097] It will also be recognized that the components of the SRSSA block 1504, including the voltage glitch protection system 1506, can be implemented on the same security chip 1500 having flash memory 1502 and processing circuitry 1512, or on a separate chip coupled to the security chip and configured to monitor the main power supply voltage (VDD) of the flash memory and processing circuitry, and configured to provide a global reset signal to the flash memory and processing circuitry.

[0098] Therefore, a voltage spike protection system and a method for operating the voltage spike protection system are disclosed, which is capable of detecting and preventing fast and short-duration side-channel voltage spike attacks on a power supply voltage (VDD) as low as 0V or negative voltage, with durations ranging from 25 μs to less than about 20 ns. Embodiments of the invention have been described above with the aid of functional block diagrams and schematic block diagrams illustrating the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0099] The foregoing description of specific embodiments so fully reveals the general characteristics of the invention that others can readily modify such specific embodiments and / or adapt them to various applications without excessive experimentation by applying knowledge of the art, without departing from the overall concept of the invention. Therefore, it is intended that such adaptations and modifications be made within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on these teachings and guidance.

[0100] It should be understood that the claims are intended to be interpreted using the Detailed Description section rather than the Summary and Abstract section. The Summary and Abstract section may set forth one or more exemplary embodiments of the invention as conceived by the inventors, but not all exemplary embodiments, and therefore is not intended to limit the invention and the appended claims in any way.

[0101] The breadth and scope of this invention should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A circuit for voltage spike detection and protection, comprising: Voltage glitch detection block, comprising: A voltage glitch detector, operable to detect voltage glitch in the power supply voltage and generate a voltage glitch detection pulse; and A first latch, the first latch having a set input coupled to the voltage glitch detector, the first latch being operable to receive the voltage glitch detection pulse and generate a first voltage glitch detection pulse latch signal; and A system reset block, coupled to the voltage glitch detector and the first latch, receives the voltage glitch detection pulse and the first voltage glitch detection pulse latch signal, and generates a safety system reset signal that resets several on-chip circuits, including the aforementioned circuitry. The voltage glitch detector includes: A comparator having a first input coupled to the power supply voltage and a second input coupled to a reference voltage based on a predetermined setpoint voltage, the comparator being operable to compare the power supply voltage with the reference voltage, and wherein the voltage glitch detector is operable to generate a voltage glitch detection pulse when the power supply voltage is less than the reference voltage; and A first voltage glitch isolation filter and a second voltage glitch isolation filter are provided. The comparator is coupled to the power supply voltage via the first voltage glitch isolation filter to provide the comparator with a filtered voltage, thereby isolating the comparator from rapid drops in the power supply voltage caused by the voltage glitch. The second input terminal is coupled to the reference voltage via the second voltage glitch isolation filter to isolate the comparator from rapid changes in the reference voltage caused by the voltage glitch.

2. The circuit according to claim 1, wherein, The comparator is a current comparator, the current comparator including a current source operable to generate a voltage glitch current based on the reference voltage, and wherein the current comparator is operable to compare the voltage glitch current with a current from the power supply voltage applied to the first input terminal to the reference voltage and to generate the voltage glitch detection pulse if the current is less than the voltage glitch current.

3. The circuit according to claim 2, wherein, The first latch is a voltage glitch protection latch including a third voltage glitch isolation filter and a sample-and-hold circuit, wherein the voltage glitch protection latch is coupled to the power supply voltage through the sample-and-hold circuit to provide a voltage supplying the voltage glitch protection latch when the power supply voltage drops below the predetermined set point voltage, and the first voltage glitch detection pulse latch signal is coupled to the system reset block.

4. The circuit according to claim 1, wherein, The voltage glitch detection block also includes a reference voltage generator, which includes a voltage adder for generating the reference voltage using voltage mirroring technology.

5. The circuit according to claim 1, wherein, The voltage glitch detection block also includes a reference voltage generator, which includes a folded current mirror with at least two stages for generating the reference voltage.

6. The circuit according to claim 1, wherein, The system reset block includes a first level detector, which is coupled to receive the voltage glitch detection pulse and the first voltage glitch detection pulse latch signal, and the first level detector is operable to generate the safety system reset signal.

7. The circuit according to claim 1, wherein, The voltage glitch detector and the first latch are operable to operate in the negative voltage domain during the voltage glitch.

8. A circuit for voltage spike detection and protection, comprising: Voltage glitch detection block, including: A voltage glitch detector, operable to detect voltage glitch in a power supply voltage and generate a voltage glitch detection pulse; and A first latch, the first latch having a set input coupled to the voltage glitch detector, the first latch being operable to receive the voltage glitch detection pulse and generate a first voltage glitch detection pulse latch signal; and A system reset block, coupled to the voltage glitch detector and the first latch, receives the voltage glitch detection pulse and the first voltage glitch detection pulse latch signal, and generates a safety system reset signal that resets several on-chip circuits, including the aforementioned circuitry. The system reset block includes a first level detector, which is coupled to receive the voltage glitch detection pulse and the first voltage glitch detection pulse latch signal. The first level detector is operable to generate the safety system reset signal. The system reset block further includes a second level detector, which is coupled to the power supply voltage and coupled to the controller through a logic gate, wherein: The second level detector is operable to detect when the power supply voltage drops below a predetermined minimum power supply voltage and generate a non-safety system reset signal; The logic gate is operable to receive a non-safe system reset signal from the second level detector and a safe system reset signal from the first level detector, thereby generating a system reset signal for the controller; and The controller is operable to generate one or more global reset signals to reset the plurality of on-chip circuits in the chip.

9. The circuit according to claim 8, wherein, The first latch also includes a reset_b input coupled to the output of the logic gate.

10. The circuit according to claim 8, wherein, The voltage glitch detection block further includes a second latch having a set input coupled to the voltage glitch detector. The second latch is operable to receive the voltage glitch detection pulse from the voltage glitch detector, generate a second voltage glitch detection pulse latch signal, and couple the second voltage glitch detection pulse latch signal to the testability design logic in the circuit.

11. The circuit according to claim 10, wherein, The second latch includes a reset-b input, which is coupled to receive the non-safety system reset signal from the second level detector.

12. The circuit according to claim 8, wherein, The voltage glitch detector and the first latch are operable to operate in the negative voltage domain during the voltage glitch.

13. A security system, comprising: Embedded non-volatile memory; The circuit includes: Voltage glitch detection block, comprising: A voltage glitch detector, operable to detect voltage glitch in a power supply voltage and generate a voltage glitch detection pulse; and A latch having a set input coupled to the voltage glitch detector, the latch being operable to receive the voltage glitch detection pulse and generate a voltage glitch detection pulse latch signal; and A system reset block, coupled to the voltage glitch detector and the latch, receives the voltage glitch detection pulse and the voltage glitch detection pulse latch signal, and generates a safety system reset signal to reset the embedded non-volatile memory. The system reset block includes: A first-level detector, coupled to receive the voltage glitch detection pulse and the voltage glitch detection pulse latch signal, is operable to generate the safety system reset signal. A second level detector, coupled to the power supply voltage and coupled to the controller via logic gates, is operable to detect when the power supply voltage drops below a predetermined minimum power supply voltage and generate a non-safety system reset signal. The voltage glitch detector includes a comparator having a first input coupled to the power supply voltage and a second input coupled to a reference voltage based on a predetermined setpoint voltage. The comparator is operable to compare the power supply voltage with the reference voltage. Furthermore, the voltage glitch detector is operable to generate a voltage glitch detection pulse when the power supply voltage is less than the reference voltage. The latch is a voltage glitch protection latch including a first voltage glitch isolation filter and a sample-and-hold circuit. The voltage glitch protection latch is coupled to the power supply voltage through the sample-and-hold circuit to provide a voltage to supply power to the voltage glitch protection latch when the power supply voltage drops below the predetermined set point voltage.

14. The security system according to claim 13, wherein, The comparator is a current comparator, the current comparator including a current source operable to generate a voltage glitch current based on the reference voltage, and wherein the current comparator is operable to compare the voltage glitch current with a current generated from the power supply voltage and generate the voltage glitch detection pulse if the current is less than the voltage glitch current.

15. The security system according to claim 14, wherein, The voltage spike detection block further includes a second voltage spike isolation filter and a third voltage spike isolation filter, wherein the comparator is coupled to the power supply voltage through the second voltage spike isolation filter to provide the comparator with a filtered voltage, thereby isolating the comparator from the rapid drop in the power supply voltage caused by the voltage spike, and the second input terminal is coupled to the reference voltage through the third voltage spike isolation filter to isolate the comparator from the rapid change in the reference voltage caused by the voltage spike.

16. The security system according to claim 13, wherein, The system reset block also includes: The logic gate is operable to receive the non-safe system reset signal from the second level detector and the safe system reset signal from the first level detector, thereby generating a system reset signal for the controller; and The controller is operable to generate the security system reset signal to reset the embedded non-volatile memory.

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