Ion current drop compensation

Abstract

In some embodiments, a high-voltage power supply is disclosed that provides a plurality of high-voltage pulses without any voltage drop between two subsequent pulses. In some embodiments, a high-voltage power supply is disclosed that provides a waveform of voltage changing over time with a plurality of high-voltage pulses having a voltage greater than 1 kV and having substantially flattened portions between the pulses. In some embodiments, a high-voltage power supply is disclosed that includes a buffer resistor having a resistance value of approximately 7.5 mΩ–1.25 Ω and a buffer capacitor having a capacitance value of approximately 2 μF–35 μF.

Description

Background Technology

[0001] Some plasma systems include at least two power sources. One generates a high-frequency waveform, which can be used to generate plasma within the plasma chamber. The other generates a high-voltage pulse, which accelerates the charged plasma particles towards the wafer within the plasma chamber. Summary of the Invention

[0002] Some embodiments include a power supply that provides multiple high-voltage pulses that do not have any substantial voltage drop between two subsequent pulses.

[0003] Some embodiments include a power supply that provides a waveform of voltage varying over time with a plurality of high-voltage pulses having a voltage greater than 1 kV and having substantially flat portions between the pulses.

[0004] Some embodiments include a power supply comprising an RF driver that generates an RF signal having an RF frequency; a nanosecond pulser that generates a high-voltage pulse having a pulse repetition frequency less than the RF frequency, a pulse width, and a peak voltage greater than 2 kV; the nanosecond pulser including a buffer circuit and a filter circuit disposed between the RF driver and the plasma chamber. The buffer circuit may include a buffer resistor having a resistance value of approximately 7.5 mΩ–1.25 Ω; and a buffer capacitor having a capacitance value of approximately 2 μF–35 μF.

[0005] In some embodiments, the filter circuit includes a filter inductor having an inductance value of approximately 0–2.5 μH.

[0006] In some embodiments, the power supply has a stray inductance of less than approximately 800 nH.

[0007] In some embodiments, the pulse width has a duration of approximately 100-250 ns.

[0008] In some embodiments, the RF signal has a voltage greater than 100V.

[0009] In some embodiments, the nanosecond pulser includes a DC power supply with a voltage greater than 500V.

[0010] In some embodiments, the voltage change between two consecutive pulses is less than 1V / ns.

[0011] In some embodiments, the voltage change between two consecutive pulses without an RF signal is less than 1V / ns.

[0012] In some embodiments, the average voltage change between two consecutive pulses is less than 1 V / ns.

[0013] In some embodiments, the power supply output has an RF signal waveform between each of the plurality of high-voltage pulses.

[0014] Some embodiments include a semiconductor processing system comprising: a plasma chamber; and a power supply according to the present disclosure coupled to the plasma chamber to introduce the RF signal and the drive pulse into the plasma chamber.

[0015] In some embodiments, the plasma chamber has an inductance of less than approximately 20 nH.

[0016] In some embodiments, the chamber includes a chuck having a capacitance value of less than approximately 10 nF.

[0017] Some embodiments include a pulse generator comprising: a power supply providing a voltage greater than 2kV; a transformer including: a transformer core; a primary coil wound around at least a portion of the transformer core, the primary coil having a first conductor and a second conductor; and a secondary coil wound around at least a portion of the transformer core. The pulse generator may also include a droop compensation circuit electrically coupled to the first conductor of the primary coil; a first switch electrically connected to the droop compensation circuit and the power supply; a second switch electrically connected to the second conductor of the primary coil and the power supply, wherein the first switch and the second switch are turned on and off at different time intervals; and a pulse output electrically coupled to the secondary coil of the transformer, which outputs a square wave pulse. For example, the first switch and the second switch may be turned on and off at different time intervals; and

[0018] In some embodiments, the pulse output outputs a pulse having a voltage greater than approximately 2 kV and a pulse frequency greater than 1 kHz.

[0019] In some embodiments, the dropout compensation circuit includes a biased dropout diode to allow current to flow from the first switch to the transformer.

[0020] In some embodiments, the droop compensation circuit includes a first inductor and a first resistor, the first inductor and the first resistor being connected in series and electrically coupled across the droop diode. For example, the first inductor has an inductance value of less than approximately 50 μH. For example, the first resistor has a resistance value of less than approximately 1 Ω. For example, the droop circuit may also include a second inductor electrically coupled to the first wire of the droop diode and the primary coil. For example, the second inductor has an inductance value of less than approximately 50 nH.

[0021] The pulse generator may also include a third inductor and a third resistor connected in series between the second switch and the second wire of the primary coil. For example, the third inductor has an inductance value of less than approximately 35 nH. For example, the third resistor has a resistance value of less than approximately 1 Ω.

[0022] Some embodiments include a pulse generator comprising: a DC power supply providing a voltage greater than 2kV and a transformer, the transformer comprising: a transformer core; a primary coil surrounding at least a portion of the transformer core, the primary coil having a first conductor and a second conductor; and a secondary coil surrounding at least a portion of the transformer core. The pulse generator may include a plurality of switches arranged in a full-bridge configuration, first portions of the plurality of switches being electrically connected to the droop compensation circuit and the power supply; and second portions of the plurality of switches being electrically connected to the second conductor of the primary coil and the power supply. For example, the first portions and the second portions of the plurality of switches may be turned on and off at different time intervals. The pulse generator may include a damping circuit electrically disposed between the first portions of the plurality of switches and / or the second portions of the plurality of switches and the transformer. The damping circuit may include: a diode biased from the first portions of the plurality of switches toward the first conductor; a first resistor disposed between the diode and the first conductor; a first inductor; and a second resistor connected in series with the first inductor and electrically coupled across the diode. The pulse generator may include a pulse output electrically coupled to the secondary coil of the transformer, the output having a voltage greater than approximately 2 kV and a pulse frequency greater than 1 kHz.

[0023] In some embodiments, the first inductor has an inductance value of less than approximately 35 nH. In some embodiments, the first resistor has a resistance value of less than approximately 1 Ω. In some embodiments, the second resistor has a resistance value of less than approximately 1 Ω.

[0024] In some embodiments, the pulse generator may further include a second inductor and a third resistor, the second inductor and the third resistor being connected in series between the second portion of the plurality of switches and the second wire.

[0025] The different embodiments described in the Summary of the Invention and in this document are not intended to limit or restrict the scope of this disclosure or the claims. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of the power system driving the load stage according to some embodiments;

[0027] Figure 2 This is a circuit diagram of a power supply system having a resistive output stage driving a load stage according to some embodiments.

[0028] Figure 3 These are examples of two waveforms generated by a power supply system that does not have RF power, according to some embodiments;

[0029] Figure 4 These are examples of two waveforms generated by a power supply system with RF power according to some embodiments;

[0030] Figure 5 These are examples of two waveforms generated by a power supply system that does not have RF power, according to some embodiments;

[0031] Figure 6 These are examples of two waveforms generated by a power supply system with RF power according to some embodiments;

[0032] Figure 7 These are examples of two waveforms generated by a power supply system that does not have RF power, according to some embodiments;

[0033] Figure 8 These are examples of two waveforms generated by a power supply system with RF power, according to some embodiments.

[0034] Figure 9 Examples of side-by-side waveforms with and without descent compensation generated by a nanosecond pulser without a system, according to some embodiments.

[0035] Figure 10A and Figure 10B This is a bar chart showing wafer potentials with and without downside correction according to some embodiments.

[0036] Figure 11 This is a circuit diagram of a power supply system driven by a droop compensation circuit according to some embodiments.

[0037] Figure 12 This is a circuit diagram of a power supply system driven by a droop compensation circuit according to some embodiments.

[0038] Figure 13 This is a circuit diagram of a pulser and plasma system according to some embodiments.

[0039] Figure 14 This is a circuit diagram of a pulser and a plasma system that combines a pulser with an energy recovery circuit according to some embodiments. Detailed Implementation

[0040] Some embodiments include a power supply system that includes a nanosecond pulser that generates pulses (e.g., square wave pulses) to drive the plasma within a plasma chamber. The power supply system may include a buffer circuit comprising circuit elements that cancel out ion currents that occur within the plasma after the pulse completes.

[0041] Figure 1 This is a circuit diagram illustrating how a pulser and plasma system 100, according to some embodiments, drives pulses into a plasma chamber 106. For example, these pulses may include square wave pulses. The pulser stage 101 may include multiple pulses that can be introduced into the plasma chamber 106. For example, an RF generator 108 may generate an RF signal such as a sine wave signal. A filter circuit 103 may prevent the RF signal and pulses from interfering with each other. The values ​​of components in the buffer circuit, such as a buffer resistor R3, a buffer inductor L3, and / or a buffer capacitor C5, may be selected to reduce the dropout of the pulses introduced into the plasma chamber 106.

[0042] For example, the buffer resistor R3 can have a resistance value of less than approximately 100 mΩ, such as 75, 50, 25, 10, 5, 1, 0.5 mΩ, etc. Optionally or additionally, the buffer resistor R3 can have a resistance value of approximately 7.5 mΩ–1.25 Ω. For example, the buffer capacitor can have a capacitance value of less than approximately 50 μF, such as approximately 2 μF–35 μF.

[0043] In some embodiments, plasma chamber 106 may represent an ideal or effective circuit for a semiconductor processing chamber such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc. For example, capacitor 12 may represent the capacitance value of an electrostatic chuck on which a semiconductor process wafer may be located. For example, the chuck may include a dielectric material (e.g., alumina, or other ceramic material and conductors encapsulated within the dielectric material). For example, capacitor 11 may have a small capacitance value (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0044] For example, capacitor 13 could represent the sheath capacitance between the plasma and the wafer. For example, resistor 56 could represent the sheath resistance between the plasma and the wafer. For example, current source 12 could represent the sheath inductance between the plasma and the wafer. For example, capacitor 23 or capacitor 13 could have small capacitance values ​​(e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

[0045] For example, capacitor 18 can represent the plasma shell capacitance to the chamber wall. For example, resistor 57 can represent the shell resistance between the plasma and the chamber wall. For example, current source 11 can represent the ion current in the plasma. For example, capacitor 23 or capacitor 18 can have small capacitance values ​​(e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0046] In some embodiments, the plasma voltage may be the voltage measured from ground to circuit point 123; the wafer voltage may be the voltage measured from ground to circuit point 122 and may represent the voltage on the wafer surface; the card voltage may be the voltage measured from ground to circuit point 121; the electrode voltage may be the voltage measured from ground to circuit point 124 (e.g., on the electrode); and the input voltage may be the voltage measured from ground to circuit point 125.

[0047] In some embodiments, the pulser and plasma system 100 may include, for example, Figure 11 The DC bias circuit shown.

[0048] In some embodiments, bias capacitor 20 can isolate (or isolate) the DC bias voltage from other circuit elements. For example, bias capacitor 20 can allow a potential to move from one part of the circuit to another. In some embodiments, this potential movement can ensure that the electrostatic force holding the wafer on the chuck remains below a voltage threshold. Resistor R2 can isolate the DC bias power supply from the high-voltage pulse output from pulser stage 101.

[0049] For example, the bias capacitor 20 may have a capacitance value less than approximately 100pF, 10pF, 1pF, 100μF, 10μF, 1μF, etc. For example, the resistor R2 may have a high resistance value, such as approximately 1kΩ, 10kΩ, 100kΩ, 1MΩ, 10MΩ, 100MΩ, etc.

[0050] Circuit 105 can represent a transmission line from the circuit to the plasma chamber 106. For example, resistor 63 can represent the resistance value of a wire or transmission line that connects the output of a high-voltage power supply system to an electrode (e.g., plasma chamber 106). For example, capacitor 11 can represent stray capacitance in a wire or transmission line.

[0051] In some embodiments, the pulser stage 101 may generate a pulse having a high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., a rise time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), a fast fall time (e.g., a fall time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), and / or a short pulse width (e.g., a pulse width less than approximately 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0052] For example, pulser stage 101 may include all or any part of the device described in U.S. Patent Application No. 14 / 542,486 entitled “High Voltage Nanosecond Pulse Generator”, which is incorporated herein by reference for all purposes; or all or any part of the device described in U.S. Patent Application No. 14 / 635,991 entitled “Electrically Isolated Variable Output Pulse Generator Disclosure”, which is incorporated herein by reference for all purposes; or all or any part of the device described in U.S. Patent Application No. 14 / 798,154 entitled “High Voltage Nanosecond Pulse Generator with Variable Pulse Width and Pulse Repetition Frequency”, which is incorporated herein by reference for all purposes.

[0053] In some embodiments, the nanosecond pulser stage 101 may include one or more nanosecond pulsers coupled together in a variety of ways.

[0054] In some embodiments, the nanosecond pulser stage 101 may include a DC power supply providing a constant DC voltage, which is switched by switch S6 and provides switching power to transformer T1. The DC power supply may include a voltage power supply V5 and an energy storage capacitor C7. If transformer T1 has a turns ratio of 1:10, then the transformer can generate 10kV on the load.

[0055] In some embodiments, if the load capacitance value (e.g., capacitance values ​​13 and 18) is smaller than the capacitance value of the energy storage capacitor C7, voltage doubling may (or may not) occur at the input of the transformer. For example, if the energy storage capacitor C7 provides 500V, then 1kV can be measured at the input of the transformer T1.

[0056] For example, switch S6 may include one or more solid-state switches, such as, for example, IGBTs, MOSFETs, silicon carbide MOSFETs, silicon carbide transistors, FETs, silicon carbide switches, gallium nitride switches, optoelectronic switches, etc. Switch S6 can be switched based on signals from the controller identified as Sig+ and Sig-.

[0057] In some embodiments, switch S6 can switch so quickly that the voltage of the switch may never be at full voltage (e.g., the voltage of energy storage capacitor C7 and / or voltage supply V5). In some embodiments, the gate resistor coupled to switch S6 can be set using a short-time turn-on pulse.

[0058] In some embodiments, the nanosecond pulser stage 101 may include a freewheeling diode D2. In some embodiments, the freewheeling diode D2 may be used in conjunction with an inductive load to ensure that energy stored in the inductive load can be allowed to dissipate after the switch S6 is turned on in a manner that allows current to continue flowing through the inductor in the same direction and energy to dissipate in the resistive elements of the circuit. If the freewheeling diode D2 is not included, this can, for example, result in a reverse voltage across the switch S6.

[0059] In some embodiments, the pulser stage 101 may include a stray inductance L1 and / or a stray resistance R1. For example, the stray inductance L1 may be less than approximately 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc. For example, the stray resistance R1 may be less than approximately 1 Ω, 100 mΩ, 10 mΩ, etc.

[0060] In some embodiments, the energy recovery circuit 110 may be electrically coupled to the secondary side of the transformer and / or the energy storage capacitor C7. For example, the energy recovery circuit 110 may include a crowbar diode 130 traversing the secondary side of the transformer T1. For example, the energy recovery circuit 110 may include an energy recovery diode 120 and an energy recovery inductor 115 (connected in series), which may allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7. The energy recovery diode 120 and the energy recovery inductor 115 may be electrically connected to the secondary side of the transformer T1 and the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 may include a diode 130 and / or an inductor 140 electrically coupled to the secondary side of the transformer T1. The inductor 140 may represent a stray inductance and / or may include the stray inductance of the transformer T1.

[0061] In some embodiments, the energy recovery inductor 115 may include any type of inductor, such as, for example, a ferrite core inductor or an air core inductor. In some embodiments, the energy recovery inductor 115 may have any type of geometry, such as, for example, a solenoid winding, a toroidal winding, etc. In some embodiments, the energy recovery inductor 115 may have an inductance value greater than approximately 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 115 may have an inductance value from approximately 1 μH to approximately 100 mH.

[0062] In some embodiments, the order of the energy recovery inductor 115 and the energy recovery diode 120 can be interchanged. For example, the energy recovery diode 120 can follow the energy recovery inductor 115 or the energy recovery inductor 115 can follow the energy recovery diode 120.

[0063] In some embodiments, when the nanosecond pulser is on, current can charge the plasma chamber 106 (e.g., charge capacitors 13, 12, or 18). For example, when the voltage on the secondary side of transformer T1 rises above the charge voltage on energy storage capacitor C7, some current can flow through energy recovery inductor 115. When the nanosecond pulser is off, current can flow from a capacitor (e.g., capacitor 11) through energy recovery inductor 115 to charge energy storage capacitor C7 until the voltage across energy recovery inductor 115 is zero. Claw diode 130 prevents the capacitors within plasma chamber 106 from ringing along with the inductors within plasma chamber 106 or DC bias circuit 104.

[0064] For example, the energy recovery diode 120 can prevent charge from flowing from the energy storage capacitor C7 to the capacitor inside the plasma chamber 106.

[0065] The value of the energy recovery inductor 115 can be selected to control the current drop time. In some embodiments, the energy recovery inductor 115 may have an inductance value between 1 μH and 600 μH. In some embodiments, the energy recovery inductor 115 may have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 115 may have an inductance value less than approximately 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

[0066] For example, if the energy storage capacitor C7 provides 500V, then 1kV is measured at the input of transformer T1 (e.g., due to voltage multiplication, as described above). When switch S6 is open, the 1kV at transformer T1 can be divided among the components of energy recovery circuit 110. If the values ​​are correctly selected (e.g., the buffer inductor L3 has a smaller inductance value than the energy recovery inductor 115), the voltage across energy recovery diode 120 and energy recovery inductor 115 can be greater than 500V. Current can then flow through energy recovery diode 120 and / or charge energy storage capacitor C7. Current can also flow through diode D3 and inductor L8. Once energy storage capacitor C7 is charged, current can no longer flow through diode D3 and energy recovery inductor 115.

[0067] In some embodiments, the energy recovery circuit 110 can transfer energy (or charge) from the plasma chamber 106 on, for example, fast timescales (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The stray resistance value of the energy recovery circuit can be low to ensure that the pulses across the plasma chamber 106 have a fast fall time tf. For example, the stray resistance of the energy recovery circuit 110 can have a resistance less than approximately 1 Ohm, 100 mOhm, 10 mOhm, etc. In some embodiments, the energy transfer efficiency from the plasma chamber 106 can be high, for example, greater than approximately 60%, 70%, 80%, or 90%, etc.

[0068] It may or may not be necessary. Figure 1 Any number of components shown, such as, for example, diode 135 or crowbar diode 130 or inductor 140.

[0069] In some embodiments, the diode may be placed between the voltage source V1 and a connection point where the energy recovery circuit 110 is connected to the voltage source V1 and / or the energy storage capacitor C7. For example, this diode may be configured to allow current to flow from the voltage source V1 to the energy storage capacitor C7, but may not allow current to flow from the energy recovery circuit to the energy storage capacitor C7.

[0070] In some embodiments, the energy recovery circuit 110 may be removed. In some embodiments, a resistive output stage or a bias compensation circuit may be included. Many other circuits or circuit elements may be included.

[0071] In some embodiments, the pulser and plasma system 100 may include a filter circuit 103. In this example, the filter circuit includes a filter capacitor 185 and / or a filter inductor 180. For example, the filter capacitor 185 filters low-frequency signals from the pulser stage 101. For example, these low-frequency signals may have frequencies of approximately 100 kHz and 10 MHz (e.g., most of the spectral content), such as approximately 10 MHz. For example, the filter capacitor 185 may have a value of approximately 1 pF to 1 nF, such as less than approximately 100 pF.

[0072] In some embodiments, the filter inductor 180 can, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may have frequencies ranging from approximately 1 MHz to 200 MHz, for example, greater than approximately 1 MHz or 10 MHz. For example, the filter inductor 180 may have a value ranging from approximately 10 nH to 10 μH, for example, greater than approximately 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance value across its terminals. In some embodiments, the coupling capacitance value may be less than 1 nF.

[0073] In some embodiments, one or both of the filter capacitor 185 and the filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulse generator stage 101 (or vice versa). For example, the filter capacitor 185 can isolate pulses generated by the pulse generator stage 101 from pulses generated by the RF generator 108. The filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulse generator stage 101.

[0074] Figure 2 This is a circuit diagram of a power supply system 200 having a resistive output stage 220 driving a load stage according to some embodiments. In this example, the energy recovery circuit 110 is removed from the pulser and plasma system 100 and replaced by the resistive output stage 220.

[0075] The resistive output stage 220 may include any resistive output stage in the prior art. For example, the resistive output stage 220 may include any resistive output stage described in U.S. Patent Application No. US16 / 178,538, entitled “High Voltage Resistive Output Stage Circuit,” which is incorporated herein for all purposes.

[0076] For example, resistive output stage 220 may include an inductor L11, a resistor R10, and a capacitor C11. In some embodiments, inductor L11 may include an inductance value of approximately 5 μH to approximately 25 μH. In some embodiments, resistor R11 may include a resistance value of approximately 50 Ω to approximately 250 Ω. In some embodiments, resistor R10 may include stray resistance in resistive output stage 220.

[0077] In some embodiments, resistor R11 may include a plurality of resistors connected in series or parallel. Capacitor C11 may represent the stray capacitance value of resistor R11, including the capacitance value set by the series and / or parallel resistors. For example, the stray capacitance value of C11 may be less than 500pF, 250pF, 100pF, 50pF, 10pF, 1pF, etc. For example, the stray capacitance value of C11 may be less than the load capacitance value, such as, for example, less than 12, 13, and / or 18.

[0078] In some embodiments, resistor R11 can discharge a load (e.g., a plasma shell capacitor). In some embodiments, resistive output stage 220 can be configured to discharge at an average power of approximately 1 kW per pulse cycle and / or at an energy of approximately 1 kW or less in joules per pulse cycle. In some embodiments, the resistance value of resistor R11 within resistive output stage 220 can be less than 200 Ω. In some embodiments, resistor R11 can comprise a plurality of series or parallel resistors having a total capacitance value of less than approximately 200 pF (e.g., 111).

[0079] In some embodiments, the resistive output stage 220 may include circuit elements that can be used to control the shape of the voltage waveform across the load. In some embodiments, the resistive output stage 220 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistive output stage 220 may include active circuit elements (e.g., switches) and passive circuit elements. In some embodiments, for example, the resistive output stage 220 may be used to control the voltage rise time and / or the voltage fall time of the waveform.

[0080] In some embodiments, the resistive output stage 220 can discharge capacitive loads (e.g., wafers and / or plasma). For example, these capacitive loads may have small capacitance values ​​(e.g., 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

[0081] In some embodiments, the resistive output stage 220 can be used in a circuit with pulses having high pulse voltages (e.g., 1kV, 10kV, 20kV, 50kV, 100kV, etc.) and / or high frequencies (e.g., 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.) and / or frequencies of approximately 400kHz, 0.5MHz, 2.0MHz, 4.0MHz, 13.56MHz, 27.12MHz, 40.68MHz, 50MHz, etc.

[0082] In some embodiments, the resistive output stage 220 can be selected to handle high average power, high peak power, fast rise time and / or fast fall time. For example, the average power level may be greater than about 0.5kW, 1.0kW, 10kW, 25kW, etc., and / or the peak power level may be greater than about 1kW, 10kW, 100kW, 1MW, etc.

[0083] In some embodiments, the resistive output stage 220 may include a series or parallel network of passive components. For example, the resistive output stage 220 may include a series connection of a resistor, a capacitor, and an inductor. As another example, the resistive output stage 220 may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor. For example, L11 may be chosen large enough that no significant energy is injected into the resistive output stage 220 when there is voltage coming out of the rectifier. The values ​​of R10 and R11 may be chosen so that the L / R time can deplete the appropriate capacitor in the load faster than the RF frequency.

[0084] In some embodiments, the pulser stage 101 of the pulser and plasma system 100 or the power system 200 may include a buffer circuit. In some embodiments, the buffer circuit may include a buffer capacitor C5. In some embodiments, the buffer circuit may include a buffer capacitor C5 and a buffer resistor R3. In some embodiments, the buffer circuit may include a buffer capacitor C5, a buffer inductor L3, and a buffer resistor R3.

[0085] In some embodiments, the buffer circuit may include a buffer resistor R3 and / or a buffer inductor L3 configured in parallel with a buffer diode D4. The buffer inductor L3, buffer resistor R3, and buffer diode D4 are configured in series with a buffer capacitor C5. In some embodiments, the buffer resistor R3 and / or buffer diode D4 may be disposed between the collector of switch S6 and the primary winding of transformer T1. The buffer diode D4 can be used to suppress any overvoltage in the switch. A large or fast-acting buffer capacitor C5 may be coupled to the emitter or collector of switch S6. A freewheeling diode D2 may also be coupled to the emitter side of switch S1. Many other components not shown in the figures may be included. One or more switches and / or circuits may be connected in parallel or in series.

[0086] In some embodiments, to counteract the ion current within the chamber, a positive current can be generated flowing out of pulser phase 101 after the pulse completes. This can be achieved, for example, by adjusting the inductance of the buffer inductor L3 (which may be removed, for example), the resistance of the buffer resistor R3, and / or the capacitance of the buffer capacitor C5, so that the buffer capacitor C5 can discharge during the pulse and / or may not be fully charged before the next pulse. This can, for example, allow the decaying current to flow out of the energy storage capacitor C7 and / or the voltage source V1 in the same direction as the current flow during the pulse. This can produce a waveform shape on the wafer that does not include a dropout.

[0087] As the voltage rises between pulses generated by the pulser stage 101, a drop can occur. The drop can consist of a voltage rise of 0.2V / ns (e.g., for a chuck with an ion current of approximately 5nF and 1Amp) or 1V / ns (e.g., for a chuck with an ion current of approximately 5nF and 5Amp).

[0088] RF generators 1-8 can be electrically coupled to plasma chamber 106. RF generator 108 can, for example, introduce a high-frequency RF signal into the plasma chamber, which can generate plasma from the components within the chamber.

[0089] RF generator 108 may include any device that generates RF power for the cathode. RF generator 108 may include, for example, a nanosecond pulser, a resonant system driven by a half-bridge or full-bridge circuit, an RF amplifier, a nonlinear transmission line, an RF plasma generator, etc. In some embodiments, RF generator 108 may include an impedance matching network.

[0090] In some embodiments, the RF generator 108 may include one or more RF drivers capable of generating RF power signals having multiple different RF frequencies, such as 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz. For example, conventional RF frequencies may include frequencies between 200 kHz and 800 MHz. In some embodiments, the RF generator 108 may generate and sustain plasma within a plasma chamber. For example, the RF generator 108 may provide an RF signal to a cathode (and / or antenna) to excite different gases and / or ions within the chamber to generate plasma.

[0091] In some embodiments, the RF generator 108 may be coupled to an impedance matching circuit or may include an impedance matching circuit that can match the non-standard output impedance of the RF generator 108 to the industry standard characteristic impedance of a 50Ω coaxial cable or any cable.

[0092] In some embodiments, the RF generator 108 may generate bursts with an RF frequency greater than the pulse repetition frequency of the pulses generated by the pulser stage 101.

[0093] In some embodiments, the pulser and plasma system 100 may include a filter capacitor 185 and / or a filter inductor 180. The filter capacitor 185 may, for example, filter low-frequency signals from the pulser stage 101. These low-frequency signals may, for example, have frequencies of approximately 100 kHz and 10 MHz (e.g., most of the spectral content), such as approximately 10 MHz. The filter capacitor 185 may, for example, have a value of approximately 1 pF to 1 nF, such as less than approximately 100 pF.

[0094] In some embodiments, the filter inductor 180 may, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may have frequencies ranging from 1 MHz to 200 MHz, for example, greater than about 1 MHz or 10 MHz. The filter inductor 180 may have a value ranging from about 10 nH to 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance value across its terminals. In some embodiments, the coupling capacitance value may be less than 1 nF.

[0095] In some embodiments, one or both of the filter capacitor 185 and the filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulse generator stage 101 (or vice versa). For example, the filter capacitor 185 can isolate pulses generated by the pulse generator stage 101 from pulses generated by the RF generator 108. The filter inductor 180 can isolate pulses generated by the RF generator 108 from pulses generated by the pulse generator stage 101.

[0096] Figure 3 This is an example of two waveforms generated by a power supply system that does not have RF power (e.g., no RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 305 is the chuck voltage (e.g., circuit point 121) and wafer waveform 310 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 75mΩ, the capacitance of buffer capacitor C5 is 12μF, the pulse width is 100ns, and the inductance of filter inductor 180 can be, for example, approximately 100nH. The DC voltage provided by voltage source V1 is 500V. As shown, wafer waveform 310 is largely flat between pulses. For example, between pulses, wafer waveform 310 has a slope of less than 1V / ns, 0.5V / ns, 0.2V / ns, 0.1V / ns, etc.

[0097] Figure 4 This is an example of two waveforms generated by a power supply system having RF power (e.g., an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 405 is the chuck voltage (e.g., circuit point 121) and wafer waveform 410 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 75mΩ, the capacitance of buffer capacitor C5 is 12μF, the pulse width is 100ns, and the inductance of filter inductor 180 can be, for example, approximately 100nH. The DC voltage provided by voltage source V1 is 500V. As shown, wafer waveform 410 is largely flat between pulses. For example, between consecutive pulses, wafer waveform 410 can vary with small consecutive pulse variations of less than 1V / ns.

[0098] Figure 5This is an example of two waveforms generated by a power supply system that does not have RF power (e.g., no RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 505 is the chuck voltage (e.g., circuit point 121) and wafer waveform 510 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 10mΩ, the capacitance of buffer capacitor C5 is 35μF, the pulse width is 150ns, and the inductance of filter inductor 180 is 0nH. The DC voltage provided by voltage source V1 is 750V. As shown, wafer waveform 510 is largely flat between pulses. For example, between pulses, wafer waveform 510 has a slope of less than 1V / ns, 0.5V / ns, 0.2V / ns, 0.1V / ns, etc.

[0099] Figure 6 This is an example of two waveforms generated by a power supply system having RF power (e.g., an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 605 is the chuck voltage (e.g., circuit point 121) and wafer waveform 610 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 10mΩ, the capacitance of buffer capacitor C5 is 35μF, the pulse width is 150ns, and the inductance of filter inductor 180 is 0nH. The DC voltage provided by voltage source V1 is 750V. As shown, wafer waveform 610 is largely flat between pulses. For example, between pulses, wafer waveform 610 has a slope of less than 1V / ns, 0.5V / ns, 0.2V / ns, 0.1V / ns, etc.

[0100] Figure 7 This is an example of two waveforms generated by a power supply system that does not have RF power (e.g., no RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 705 is the chuck voltage (e.g., circuit point 121) and wafer waveform 710 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 10mΩ, the capacitance of buffer capacitor C5 is 35μF, the pulse width is 250ns, and the inductance of filter inductor 180 is 0nH. The DC voltage provided by voltage source V1 is 700V. As shown, wafer waveform 710 is largely flat between pulses. For example, between pulses, wafer waveform 710 has a slope of less than 1V / ns, 0.5V / ns, 0.2V / ns, 0.1V / ns, etc.

[0101] Figure 8This is an example of two waveforms generated by a power supply system having RF power (e.g., an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 805 is the chuck voltage (e.g., circuit point 121) and wafer waveform 810 is the voltage measured on the wafer (e.g., circuit point 122). In this example, the resistance of buffer resistor R3 is 10mΩ, the capacitance of buffer capacitor C5 is 35μF, the pulse width is 250ns, and the inductance of filter inductor 180 is 0nH. The DC voltage provided by voltage source V1 is 800V. As shown, wafer waveform 810 is largely flat between pulses. For example, between pulses, wafer waveform 810 has a slope of less than 1V / ns, 0.5V / ns, 0.2V / ns, 0.1V / ns, etc.

[0102] Figure 9 These are side-by-side waveforms with and without droop compensation generated by a nanosecond pulser without a system, according to some embodiments. In this example, chuck waveform 905 is a chuck voltage without droop compensation, and chuck waveform 915 is a chuck voltage with droop compensation. In this example, wafer waveform 910 is a wafer voltage without droop compensation, and wafer waveform 920 is a wafer voltage with droop compensation. In this example, the resistance value of the buffer resistor R3 without droop compensation is 1.25Ω, and the capacitance value of the buffer capacitor C5 is 2μF, while the resistance value of the buffer resistor R3 with droop compensation is reduced to 75Ω, and the capacitance value of the buffer capacitor C5 is 12μF.

[0103] Figure 10A This is a bar chart of wafer potential without downside correction according to some embodiments. Figure 10B It is a bar chart of wafer potential with a downward correction according to some embodiments.

[0104] Figure 11This is a circuit diagram of a power system 1100 for driving a plasma chamber 106 by a descent compensation circuit 165 according to some embodiments. In some embodiments, the descent compensation circuit 165 may include a crowbar diode 130 and a descent capacitor 170. The descent capacitor 170 may have a capacitance of approximately 1 nF to approximately 100 nF. In this example, with the addition of the descent capacitor 170, the current flowing through the crowbar diode 130 and the energy recovery circuit 110 may cause a voltage change across the descent capacitor 170, which may cancel out any descent. The descent capacitor 170 may limit the flow of current unless the descent capacitor 170 is fully charged, thus eliminating the descent. A switch 171 may be used to release the charge from the descent capacitor 170 to ground during a pulse. The switch 171 may be switched with the same switching frequency and / or period as the switch 170, for example, using the same signal. For example, when the switch 171 is closed, the pulser phase 101 pulses, and the switch 171 stops the discharge of the descent capacitor 170.

[0105] In some embodiments, power supply 174 may allow DC compensation or bias if needed. In some embodiments, power supply 174 may also be charged when the charge of drop capacitor 170 is depleted.

[0106] In some embodiments, inductor 172 may be a current-limiting inductor. For example, inductor 172 may have an inductance value of approximately 10 nH to 500 nH. Diode 173 and / or diode 175 may be crowbar diodes. For example, diode 175 may allow current to flow and may allow voltage spikes to flow to ground when switch 171 is open.

[0107] In some embodiments, inductor 172, diode 173 and / or diode 175 may be replaced by resistors.

[0108] Switch 171 may include any type of switch capable of switching high voltage at high frequencies. In some embodiments, switch 171 includes the high voltage switches described in U.S. Patent Application No. US62 / 717,637, entitled “High Voltage Switch for Nanosecond Pulses” and U.S. Patent Application No. US16 / 178,565, entitled “High Voltage Switch for Nanosecond Pulses”, which are incorporated herein by reference in their entirety for all purposes.

[0109] In some embodiments, the energy recovery circuit 110 may be removed or replaced by the main sink circuit and / or the resistor output stage. In some embodiments, the energy recovery circuit 110 may be connected to ground after the energy recovery inductor 115.

[0110] In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes a compensation supply voltage V5, which can, for example, bias the output voltage in either the forward or reverse direction. In some embodiments, the compensation supply voltage V5 can be adjusted to change the potential between the wafer voltage and the chuck voltage. In some embodiments, the compensation supply voltage V5 can have a voltage of approximately ±5kV, ±4kV, ±3kV, ±2kV, ±1kV, etc. The power supply system 1100 may or may not include the DC bias circuit 104.

[0111] The power supply system 1100 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may have frequencies ranging from approximately 1 MHz to 200 MHz, for example, greater than approximately 1 MHz or 10 MHz. The filter inductor 180 may have a value ranging from approximately 10 nH to approximately 10 μH, for example, greater than approximately 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance value across its terminals. In some embodiments, the coupling capacitance value may be less than 1 nF.

[0112] Figure 12 This is a circuit diagram of a pulsed plasma system 1200 driven by a droop compensation circuit in plasma chamber 106 according to some embodiments. The droop compensation circuit 190 may include a reverse DC power supply 182, a switch 181, and a current-limiting resistor 183 or a current-limiting inductor 184. The current-limiting resistor 183 may, for example, have a resistance value of approximately 0.1 Ω to approximately 50 Ω or approximately 10 mΩ to approximately 500 Ω. The current-limiting inductor 184 may, for example, have an inductance value of approximately 1 nH to approximately 100 nH. When the switch 181 is closed, the reverse DC power supply 182 can pull the voltage low, removing and limiting the droop.

[0113] Switch 181 may include any type of switch capable of switching high voltage at high frequencies. In some embodiments, switch 181 includes the high voltage switches described in U.S. Patent Application No. US62 / 717,637, entitled "High Voltage Switch for Nanosecond Pulses" and U.S. Patent Application No. US16 / 178,565, entitled "High Voltage Switch for Nanosecond Pulses," which are incorporated herein by reference in their entirety for all purposes.

[0114] In some embodiments, the pulser and plasma system 1200 may include an energy recovery circuit (e.g., energy recovery circuit 110) instead of the resistive output stage 220.

[0115] The power supply system 1200 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may have frequencies ranging from approximately 1 MHz to 200 MHz, for example, greater than approximately 1 MHz or 10 MHz. The filter inductor 180 may have a value ranging from approximately 10 nH to approximately 10 μH, for example, greater than approximately 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance value across its terminals. In some embodiments, the coupling capacitance value may be less than 1 nF.

[0116] Figure 13 This is a circuit diagram of a pulser and plasma system 1300 according to some embodiments. The pulser and plasma system 1300 may include, for example, a pulse driver 1305, shown in a full-bridge configuration but also potentially in a half-bridge configuration; a droop compensation circuit 1310; a transformer 1345; and a voltage source V1. The droop compensation circuit 1310 may, for example, mitigate or reduce voltage droop.

[0117] In this example, the pulser and plasma system 1300 may include a pulse driver 1305. The pulse driver 1305 may be, for example, a half-bridge driver or a global driver. The pulse driver 1305 may include a voltage source V1, which may be a DC voltage source (e.g., a capacitor source, an AC-DC converter, etc.). In some embodiments, the pulse driver 1305 may include four bridge switches 661, 662, 664, and 664. In some embodiments, the pulse driver 1305 may include multiple switches 661, 662, 664, and 664 connected in series or parallel. These switches 661, 662, 664, and 664 may include, for example, any type of solid-state switch such as IGBTs, MOSFETs, silicon carbide MOSFETs, silicon carbide interconnect transistors, FETs, silicon carbide switches, gallium nitride switches, photoconductive switches, etc. These switches 661, 662, 664, and 664 may switch at high frequencies and / or may generate high-voltage pulses. These frequencies may include, for example, approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0118] Each of switches 661, 662, 664, and 664 can be coupled in parallel with a corresponding bridge diode and can include stray inductance. In some embodiments, the stray inductances of the bridge switches can be equal. In some embodiments, the stray inductances of the bridge switches can be less than approximately 50nH, 100nH, 150nH, 500nH, 1,000nH, etc. The combination of switches (661, 662, 664, or 664) and the corresponding bridge diode can be connected in series with the corresponding bridge inductor. For example, the bridge inductor associated with switches 663 and 664 can be connected to ground. For example, the bridge inductor associated with switch 661 can be electrically connected to bridge switch 664 and resistor 1315 and / or inductor 1316 of droop compensation circuit 1310. And the bridge inductor associated with switch 662 can, for example, be electrically connected to bridge switch 663 and diode 1313 of droop compensation circuit 1310.

[0119] If the switch in pulse driver 1305 is at the resonant frequency f resonant When the switch is turned on, the output voltage on transformer 1345 can be amplified. In some embodiments, the resonant frequency can be approximately 400kHz, 0.5MHz, 2.0MHz, 4.0MHz, 13.56MHz, 27.12MHz, 40.68MHz, 50MHz, etc.

[0120] In some embodiments, transformer 1345 (or transformer T1) may include the high-voltage transformer described in U.S. Patent Application No. US15 / 365,094, entitled “High-Voltage Transformer”, which is incorporated herein for all purposes.

[0121] For example, the duty cycle of the switch can be adjusted by changing the duty cycle of signal Sig1, which turns the switch 661 on and off; changing the duty cycle of signal Sig2, which turns the switch 662 on and off; changing the duty cycle of signal Sig3, which turns the switch 664 on and off; and changing the duty cycle of signal Sig4, which turns the switch 664 on and off.

[0122] In some embodiments, each bridge switch 661, 662, 664, or 664 in the pulse driver 1305 can be switched independently or in conjunction with one or more other switches. For example, signal Sig1 may be the same as signal Sig3. As another example, signal Sig2 may be the same as signal Sig4. As yet another example, each signal may be independent and can independently or separately control each bridge switch 661, 662, 664, or 664.

[0123] In some embodiments, the output of the droop compensation circuit 1310 may be coupled to a half-wave rectifier, which may include a blocking diode located on the secondary side or the primary side of the transformer 1345.

[0124] In some embodiments, the output of the descent compensation circuit 1310 may be related to the resistor output stage, for example as... Figure 12 The resistor output stage 220 shown is coupled.

[0125] The resistor output stage can include any known resistor output stage. For example, the resistor output stage can include U.S. Patent Application No. 16 / 178,538, entitled "High Voltage Resistor Output Stage Circuit", which is incorporated herein by reference for all purposes.

[0126] The pulser and plasma system 1300 does not include a conventional matching network, such as a 50Ω matching network, an external matching network, or a separate matching network. Indeed, the embodiments described in this document do not require a 50Ω matching network to adjust the switching power applied in the wafer cavity. Additionally, the embodiments described in this document provide a variable output impedance RF generator without a conventional matching network. This allows for rapid changes in the power consumed by the plasma cavity. Conventionally, such adjustments to the matching network can take at least 100μs–200μs. In some embodiments, the power change can occur within one or two RF cycles, for example, 2.5μs–5.0μs at 400kHz.

[0127] In some embodiments, the pulse driver 1305 may include switches configured as a full-bridge topology as shown or a half-bridge topology with two switches. Switches 661, 662, 663, and 664 can switch the DC charge stored in the energy storage capacitor C7. A voltage source V1, which may be a DC voltage source (e.g., a capacitor source, an AC-DC converter, etc.), can charge the energy storage capacitor C7. The pulse driver 1305 may or may not drive a dropout compensation circuit 1310 having a pulse frequency that is substantially equivalent to or not substantially equivalent to the resonant frequency of the dropout compensation circuit 1310.

[0128] In some embodiments, the pulse driver 1305 can be replaced by a half-bridge topology with two switches.

[0129] The droop compensation circuit 1310 may include a diode 1313, an inductor 1312, an inductor 1314, an inductor 1316, a resistor 1315, and / or a resistor 1311. The diode 1313 may be forward biased between the pulse driver 1305 and the transformer 1345. The resistor 1315 may be, for example, very small. For example, the resistor 1315 may have a resistance value less than approximately 1 Ω, such as approximately 50, 25, 10, 5, etc. mΩ. As another example, the resistor 1315 may be as low as 0 Ω. The resistor 1311 may be, for example, very small. For example, the resistor 1311 may have a resistance value less than approximately 5 Ω, such as approximately 10, 5, 2, 1, 0.75, 0.5, 0.25 Ω, etc. Inductor 1316 and / or inductor 1314 may, for example, have an inductance value of less than about 100 nH, such as about 75, 50, 25, 10, 5, etc. nH.

[0130] Inductor 1312 may, for example, have an inductance value of less than about 50 μH, such as 25, 10, 5, 2.51 μH, etc.

[0131] The pulser and plasma system 1300 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high-frequency signals from the RF generator 108. These high-frequency signals may, for example, have frequencies from about 1 MHz to 200 MHz, e.g., greater than about 1 MHz or 10 MHz. The filter inductor 180 may, for example, have a value from about 10 nH to 10 μH, e.g., greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance value. In some embodiments, the coupling capacitance value may be less than 1 nF.

[0132] Figure 14 This is a circuit diagram of a pulser and plasma system that combines a pulser with a plasma system having an energy recovery circuit, according to some embodiments. As another example, instead of combining the energy recovery circuit 110 with the pulser and plasma system 1300, the descent compensation circuit 190 may be combined with the pulser and plasma system 1300.

[0133] Unless otherwise stated, the term "substantially" means within 5% or 10% of the value involved or within manufacturing tolerances. Unless otherwise stated, the term "approximately" means within 5% or 10% of the value involved or within manufacturing tolerances.

[0134] The conjunction "or" is open.

[0135] The terms “first,” “second,” “third,” etc., are used to distinguish the corresponding elements and are not used to identify a specific order of these elements unless otherwise stated or explicitly stated or required.

[0136] Numerous specific details are provided to provide a comprehensive understanding of the subject matter claimed in the claims. However, those skilled in the art will understand that the subject matter claimed in the claims can be practiced without these specific details. In other instances, methods, apparatus, or systems that should be known to those skilled in the art are not described in detail to avoid obscuring the subject matter claimed in the claims.

[0137] The disclosed method embodiments can be implemented by operating such a computer device. The order of the blocks presented in the above examples can be varied—for example, the blocks can be reordered, combined, and / or broken into sub-blocks. Some blocks or processes can be executed in parallel.

[0138] The use of "applies to" or "configured to" implies open-ended and inclusive language, which does not preclude the device from being suitable for or configured to perform additional tasks or steps. Similarly, the use of "based on" implies open-ended and inclusive language, where a process, step, calculation, or other behavior "based on" one or more referenced conditions or values ​​may in practice be based on additional conditions or values ​​beyond those referenced. Included headings, lists, and numbers are for convenience of interpretation only and are not intended to be limiting.

[0139] Although the subject matter has been described in detail by way of these specific embodiments, those skilled in the art will appreciate that, upon understanding the foregoing, changes, variations, and equivalent features can be readily made to these embodiments. Accordingly, it is understood that the content described herein is for illustrative purposes and not for limitation, and does not exclude the inclusion of such modifications, variations, and / or additions that would be readily apparent to those skilled in the art.

Claims

1. Power supply system, including: An RF driver that generates an RF signal with an RF frequency; A nanosecond pulse generator generates a high-voltage pulse with a pulse repetition frequency less than the RF frequency, a pulse width, and a peak voltage greater than 2kV. The nanosecond pulse generator includes a buffer circuit, which comprises: A buffer resistor with a resistance value of 7.5mΩ–1.25Ω; and Buffer capacitors with capacitance values ​​of 2μF–35μF; and A filter circuit is disposed between the RF driver and the power output terminal for connecting the plasma chamber.

2. The power supply system according to claim 1, wherein, The nanosecond pulser generates a square wave.

3. The power supply system according to claim 1, wherein, The filter circuit includes a filter inductor with an inductance value of 0–2.5 μH.

4. The power supply system according to claim 1, wherein, The power supply includes a stray inductance of less than 800nH.

5. The power supply system according to claim 1, wherein, The pulse width has a duration of 100-250 ns.

6. The power supply system according to claim 1, wherein, The voltage change between two consecutive pulses without an RF signal is less than 1V / ns.

7. The power supply system according to claim 1, wherein, The average voltage change between two consecutive pulses is less than 1V / ns.

8. The power supply system according to claim 1, wherein, Between each of the multiple high-voltage pulses, the power supply outputs a waveform with an RF signal.

9. A semiconductor processing system, comprising: Plasma chamber; and The power supply system according to claim 1 is coupled to the plasma chamber to introduce the RF signal and drive pulse into the plasma chamber.

10. The semiconductor processing system according to claim 9, wherein, The plasma chamber has an inductance of less than 20 nH.

11. The semiconductor processing system according to claim 9, wherein, The chamber includes a chuck with a capacitance value of less than 10 nF.

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