Silicon nanowire arrayed accelerometer based on soi silicon wafer and its manufacturing process

Abstract

The present application relates to a silicon nanowire array type accelerometer based on SOI silicon wafer and its preparation process. The present application will adopt a bottom silicon of 100 type (111) SOI silicon wafer, utilize the characteristics of different crystal orientation distribution of (111) type silicon wafer and (100) type silicon wafer, and prepare a high-quality high-yield accelerometer through anisotropic etching, self-limiting thermal oxidation and ion implantation processes. The process retains the silicon nitride layer on the surface of the silicon wafer, effectively protects the silicon nanowire from breaking due to various reasons, and greatly improves the long-term stability of the silicon nanowire device. In addition, the present application uses a silicon nitride film and a silicon nanowire to support the mass together, and uses a single crystal silicon nanowire to replace the traditional piezoresistor as a sensitive unit. Since the piezoresistor coefficient of the silicon nanowire is higher than that of the piezoresistor, the silicon nanowire accelerometer of the present application has higher sensitivity.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) sensor design technology, specifically relating to a silicon nanowire array accelerometer based on SOI silicon wafer and its fabrication process. Background Technology

[0002] Traditional piezoresistive accelerometers use silicon piezoresistors as the sensing element. However, due to the small strain coefficient of silicon piezoresistors, as the sensor size decreases, piezoresistors produced by traditional doping processes can no longer meet the requirements of modern high-sensitivity testing. Summary of the Invention

[0003] The purpose of this invention is to address the above-mentioned problems by providing a silicon nanowire array accelerometer based on SOI silicon wafers and its fabrication process. By using a silicon nanowire array instead of a traditional varistor, the sensitivity of the device can be improved. Furthermore, the silicon nanowire array connects numerous silicon nanowires in parallel between two electrodes, allowing multiple signals to be superimposed, resulting in a stronger and more stable output signal.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] The fabrication process of a silicon nanowire array accelerometer based on SOI silicon wafers includes the following steps:

[0006] S1. Prepare a silicon nitride thin film on the top silicon surface of a (111) type SOI silicon wafer to form a dielectric mask layer;

[0007] S2. Transfer the triangular array pattern on the dielectric mask layer and etch the silicon nitride at the triangles to form a triangular array window; then dry etch the top silicon at the triangular array window and etch down to the oxide layer of the SOI silicon wafer to obtain vertical triangular trenches of the same depth to form a triangular array trench; wherein, the triangular array trench is an array structure with three vertical triangular trenches evenly distributed circumferentially as array units.

[0008] S3. Etch the oxide layer under all the vertical triangular trenches, then etch the bottom silicon, and then remove the photoresist.

[0009] S4. Perform anisotropic wet etching on the triangular array grooves to form hexagonal etching grooves with each sidewall belonging to the {111} crystal plane family. A single-crystal silicon thin-wall structure is formed between adjacent hexagonal etching grooves. Two opposing cone structures appear between every three adjacent hexagonal etching grooves. At the same time, etching grooves appear on the bottom silicon of the 100 crystal orientation to release the two cone structures on the top silicon to form a mass block.

[0010] S5. After oxidizing the silicon wafer using a self-limiting thermal oxidation process, single-crystal silicon nanowires are formed at the top center of all single-crystal silicon thin-walled structures.

[0011] S6. Erase silicon nitride at appropriate locations on the silicon wafer to form square windows, implant boron ions into the square windows and then anneal them, and then fabricate the positive and negative electrodes.

[0012] S7. Create isolation channels at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes;

[0013] S8. Remove the oxidized single-crystal silicon thin-wall structure to release the entire structure.

[0014] As a preferred embodiment, the three vertical triangular slots in the array unit are distributed such that two are located in the same row and the remaining one is located in another row.

[0015] As a preferred embodiment, adjacent array elements share two vertical triangular slots, and the four vertical triangular slots are distributed with two in the same row and the other two in another row.

[0016] As a preferred embodiment, the number of array units is 2-1000.

[0017] As a preferred embodiment, the depth of the vertical triangular groove is 1-100 μm.

[0018] As a preferred embodiment, the wet etching solution is a 10-80 wt% KOH solution at 10-100℃, and the wet etching time is 5 minutes to 10 hours.

[0019] As a preferred embodiment, the preset width of the single-crystal silicon thin-walled structure is less than 1 μm.

[0020] As a preferred embodiment, the width of the single-crystal silicon nanowire is 10-800 nm.

[0021] The present invention also provides a silicon nanowire array accelerometer prepared by the preparation method described in any of the preceding embodiments.

[0022] As a preferred embodiment, the core structure of the silicon nanowire array accelerometer consists of multiple mass blocks supported by a silicon nitride thin film and multiple silicon nanowires, and the entire structure presents a comb-like shape.

[0023] Compared with the prior art, the beneficial effects of the present invention are:

[0024] This invention uses a (111) type SOI silicon wafer. Since the entire silicon nanowire array device is on an oxide layer, the device and the silicon wafer substrate are in an insulating state. The silicon wafer is etched into the bottom silicon to create an isolation channel, thereby achieving physical isolation between the positive and negative electrodes of the device and achieving a good insulation effect.

[0025] The core structure of the SOI-based silicon nanowire array accelerometer of this invention consists of multiple mass blocks supported by a silicon nitride thin film and multiple silicon nanowires. This not only represents an innovation in device structure, but also addresses the fact that most current silicon nanowire structure devices lack protective measures for the silicon nanowires, making them prone to breakage and resulting in a lack of long-term device stability. This invention cleverly retains the silicon nitride thin film, enabling it to protect the silicon nanowires and prevent breakage due to various reasons, thus greatly improving the device yield.

[0026] Due to the special design of the mass block and silicon nanowire structure, the silicon nanowire accelerometer of the present invention can still produce a large deformation of the silicon nanowire under the action of a small acceleration, thereby improving the output sensitivity of the accelerometer.

[0027] This invention connects multiple silicon nanowires in parallel, forming a comb-like shape. When the accelerometer is working, multiple signals are superimposed, resulting in a stronger and more stable output signal. Attached Figure Description

[0028] Figure 1A This is a schematic diagram of fabricating a silicon nitride thin film on the top silicon layer.

[0029] Figure 1B This is a partial schematic diagram of a triangular array of slots fabricated on a silicon wafer.

[0030] Figure 1C This is a partial schematic diagram of silicon nanothin-walled arrays obtained by wet etching triangular array trenches.

[0031] Figure 1D This is a schematic diagram of silicon nanowires formed by the thermal oxidation of silicon nanowalls.

[0032] Figure 1E This is a side view of a silicon nanowire-supported mass block.

[0033] Figure 1F This is a schematic diagram of the silicon nanowire array accelerometer based on SOI silicon wafer according to Example 1 of the present invention.

[0034] Figure 2 This is a schematic diagram of the silicon nanowire array accelerometer based on SOI silicon wafer according to Example 2 of the present invention.

[0035] Figure 3 This is a schematic diagram of the silicon nanowire array accelerometer based on SOI silicon wafer according to Example 3 of the present invention.

[0036] Figure 4 , Figure 5 and Figure 6 This is a photo of the triangular groove after wet etching. Detailed Implementation

[0037] To more clearly illustrate the embodiments of the present invention, specific implementation methods will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0038] This invention discloses a method for fabricating a silicon nanowire array accelerometer based on an SOI silicon wafer. The silicon nanowire array accelerometer comprises silicon nanowires, a silicon nitride thin film, mass blocks, gold electrodes, and a silicon substrate. The gold electrodes are located on the bulk silicon. The silicon nanowires have a special protective structure. The core structure of the silicon nanowire array accelerometer consists of multiple mass blocks supported by a silicon nitride thin film and multiple silicon nanowires, and the entire structure exhibits a comb-like shape.

[0039] Specifically, the fabrication method of the silicon nanowire array accelerometer based on SOI silicon wafer includes the following steps:

[0040] S1. Select a (111) type SOI silicon wafer and prepare a silicon nitride thin film on its top silicon surface to form a dense dielectric mask layer. Form an array of tilted triangular patterns in the dielectric mask layer by photolithography, and simultaneously perform RIE process to etch the silicon nitride at the pattern to form a triangular window array.

[0041] S2. Dry etching is performed on the silicon at the triangular window array in step S1 until the oxide layer of the SOI silicon wafer is etched, to prepare vertical triangular array trenches of consistent depth.

[0042] S3. Use dry etching to remove the silicon oxide layer under the vertical triangular array trenches in step S2, and then etch the underlying silicon.

[0043] S4. Remove the photoresist, then perform anisotropic wet etching on the triangular array trenches from step S3 to form hexagonal etching trenches with each sidewall belonging to the {111} crystal plane family. Adjacent hexagonal etching trenches form single-crystal silicon wall structures, and a conical structure appears between every three adjacent hexagonal etching trenches. Simultaneously, a large etching trench appears on the bottom silicon layer with the 100 crystal orientation, releasing two connected conical structures on the top silicon layer to form a mass block.

[0044] S5. Based on the self-limiting thermal oxidation process, a single-crystal silicon nanowire is formed at the top center of the single-crystal silicon nanowall.

[0045] S6. Erase silicon nitride at appropriate locations on the chip to form square windows, implant boron ions into the square windows and then anneal them, and then fabricate gold electrodes in this area.

[0046] S7. Create isolation channels at appropriate locations on the chip to achieve physical isolation between the positive and negative electrodes of the device.

[0047] S8. Remove the silicon oxide wall array using BOE (buffer oxide etching solution) to release the entire structure.

[0048] In a preferred embodiment, the silicon nitride thin film in step S1 is prepared using low-stress CVD thin film growth technology and the thickness of the silicon nitride thin film is 50nm-5μm.

[0049] In a preferred embodiment, the triangular array in step S1 consists of two basic units. The first basic unit has one triangle on top and two triangles below; the second basic unit has two triangles on top and one triangle below. The two basic units are arranged sequentially, and a triangular array is formed by 1 to 1000 such arrangements. It should also be noted that the triangular array can also be formed by either of the basic units alone.

[0050] In a preferred embodiment, the dry etching of the triangular array window in step S2 is to etch to the oxide layer of the (111) type SOI silicon wafer to prepare vertical triangular grooves with a consistent depth of 1-100 μm.

[0051] In a preferred embodiment, the etching depth of silicon oxide in step S3 is equal to the thickness of the silicon oxide layer, and the etching depth of the underlying silicon is 1-100 μm.

[0052] In a preferred embodiment, the wet etching solution in step S4 is a 10-80 wt% KOH solution at 10-100°C, and the wet etching time is 5-10 minutes.

[0053] In a preferred embodiment, the width of the single-crystal silicon thin-walled structure formed in step S4 is less than 1 μm.

[0054] In a preferred embodiment, the width of the single-crystal silicon nanowires formed in step S5 is 10-800 nm.

[0055] In a preferred embodiment, the ion implantation process in step S6 uses an ion implantation energy of 5-100 keV and an ion implantation metering of 0.1E15 cm⁻¹. -2 -10E15cm -2 The annealing temperature is 200-4000℃, and the annealing time is 5 minutes to 10 hours.

[0056] In a preferred embodiment, the isolation channel in step S7 is created by etching the silicon wafer into the underlying silicon.

[0057] In a preferred embodiment, after releasing the entire structure in step S8, the released silicon nanowires use the silicon nitride film generated in step S1 as a special protective structure.

[0058] The following detailed description is provided through specific embodiments:

[0059] Example 1:

[0060] The following will be accompanied by the appendix Figures 1A to 1F as well as Figure 4 The present invention will be described in detail below.

[0061] 1. First, prepare a (111) type SOI silicon wafer with a bottom silicon type of 100. On its surface, use low-stress CVD thin film growth technology to prepare a silicon nitride thin film 1 with a thickness of 50nm-5μm to form a dense dielectric mask layer. Figure 1A As shown.

[0062] 2. A triangular pattern array 5 is formed on the dielectric mask layer using photolithography. The triangular pattern array consists of two basic units: the first basic unit has one triangle on top and two triangles on the bottom; the second basic unit has two triangles on top and one triangle on the bottom. These two basic units are arranged sequentially, and several such arrangements form the triangular array. A RIE process is performed on the triangular pattern array 5 to etch away the silicon nitride layer 1 at the triangular pattern array, forming a triangular window array. Then, dry etching is performed on the silicon at the triangular window array to etch away the top silicon layer 2 to a depth of 1-100 μm, creating vertical triangular array trenches of uniform depth. Then, dry etching continues downwards to etch away the silicon oxide layer 3 of the SOI silicon wafer, with the thickness of the etched silicon oxide layer equal to the thickness of the silicon oxide layer. Next, the bottom silicon layer 4 is etched downwards to a depth of approximately 1-100 μm. Figure 1B and Figure 1E As shown.

[0063] 3. Remove the photoresist, and then perform anisotropic wet etching on the triangular array trenches from step 1 in a 10-80 wt% KOH solution at 10-100℃ for 5 minutes to 10 hours, forming hexagonal etched trenches 6 with each sidewall belonging to the {111} crystal plane family. Figure 1C and Figure 4 As shown. A single-crystal silicon thin-wall structure 7 with a preset width of less than 1 μm is formed between two adjacent hexagonal etching grooves 6. Two opposing cone structures appear between every three adjacent hexagonal etching grooves 6; these two opposing cone structures constitute the mass block 9 of the accelerometer. Simultaneously, a large etching groove 10 appears on the bottom silicon layer with a 100-degree crystal orientation, releasing the two connected cone structures on the top silicon layer to form the mass block. (As shown...) Figure 1C and Figure 1E As shown.

[0064] 4. Based on the self-limiting thermal oxidation process, a single-crystal silicon nanowire 8 will be formed at the very center of the top of the single-crystal silicon thin-walled structure 7. For example... Figure 1D As shown.

[0065] 5. A square window is formed by etching silicon nitride layer 1 at the lower left and lower right corners of the device. Boron ions are implanted into the square window, followed by annealing. The ion implantation metering is 0.1E15cm. -2 -10E15cm -2 The annealing temperature is 200-4000℃, and the annealing time is 5 minutes to 10 hours. Afterwards, gold electrodes are fabricated in this area. Silicon wafers are etched into the underlying silicon at appropriate locations on the chip to create isolation channels, achieving physical isolation between the positive and negative electrodes of the device. For example... Figure 1F As shown.

[0066] 6. Finally, the silicon oxide wall array is removed using BOE (buffer oxide etching solution) to release the entire structure.

[0067] Example 2:

[0068] This second embodiment is basically the same as the first embodiment in terms of preparation process and technology, but there are slight differences in the device structure, such as... Figure 2 and Figure 5 As shown: In Example 2, the etched triangular array is a basic unit consisting of one triangle on top and two triangles below, and the array contains several such basic units.

[0069] Additionally, when creating isolation channels, an isolation channel is created between the lower right triangle of a basic unit and the lower left triangle of its adjacent basic unit, while an isolation channel is also created between the upper triangle and the lower right triangle inside each basic unit.

[0070] Other examples can be found in Example 1.

[0071] Example 3:

[0072] This third embodiment is basically the same as the first embodiment in terms of preparation process and technology, but there are slight differences in the device structure, such as... Figure 3 and Figure 6 As shown: In Example 3, the etched triangular array is composed of a basic unit with one triangle at the bottom and two triangles at the top, and several such basic units form a triangular array.

[0073] Additionally, when creating isolation channels, isolation channels are created between the upper triangles between basic units, and isolation channels are also created between the lower triangle and the upper right triangle inside each basic unit.

[0074] Other examples can be found in Example 1.

[0075] The above description is merely a detailed explanation of preferred embodiments and principles of the present invention. For those skilled in the art, there may be changes in specific implementation methods based on the ideas provided by the present invention, and these changes should also be considered within the scope of protection of the present invention.

Claims

1. A fabrication process for a silicon nanowire array accelerometer based on SOI silicon wafers, characterized in that, The core structure of the silicon nanowire array accelerometer consists of multiple mass blocks supported by a silicon nitride thin film and multiple silicon nanowires, and the entire structure has a comb-like shape; the fabrication process includes the following steps: S1. Prepare a silicon nitride thin film on the top silicon surface of a (111) type SOI silicon wafer with a bottom silicon of type 100 to form a dielectric mask layer. S2. Transfer the triangular array pattern on the dielectric mask layer and etch the silicon nitride at the triangles to form a triangular array window; then dry etch the top silicon at the triangular array window and etch down to the oxide layer of the SOI silicon wafer to obtain vertical triangular trenches of the same depth to form a triangular array trench; wherein, the triangular array trench is an array structure with three vertical triangular trenches evenly distributed circumferentially as array units. S3. Etch the oxide layer under all the vertical triangular trenches, then etch the bottom silicon, and then remove the photoresist. S4. Perform anisotropic wet etching on the triangular array grooves to form hexagonal etching grooves with each sidewall belonging to the {111} crystal plane family. A single-crystal silicon thin-wall structure is formed between adjacent hexagonal etching grooves. Two opposing cone structures appear between every three adjacent hexagonal etching grooves. At the same time, etching grooves appear on the bottom silicon of the 100 crystal orientation to release the two cone structures on the top silicon to form a mass block. S5. After oxidizing the silicon wafer using a self-limiting thermal oxidation process, single-crystal silicon nanowires are formed at the top center of all single-crystal silicon thin-walled structures. S6. Erase silicon nitride at appropriate locations on the silicon wafer to form square windows, implant boron ions into the square windows and then anneal them, and then fabricate the positive and negative electrodes. S7. Create isolation channels at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes; S8. Remove the oxidized single-crystal silicon thin-wall structure to release the entire structure.

2. The preparation process according to claim 1, characterized in that, The three vertical triangular slots in the array unit are arranged such that two are located in the same row and the remaining one is located in another row.

3. The preparation process according to claim 1, characterized in that, Adjacent array cells share two vertical triangular slots, and the four vertical triangular slots are distributed with two in the same row and the other two in another row.

4. The preparation process as described in claim 2 or 3, characterized in that, The number of array units is 2-1000.

5. The preparation process according to claim 1, characterized in that, The depth of the vertical triangular groove is 1-100 μm.

6. The preparation process according to claim 1, characterized in that, The wet etching solution is a 10-80 wt% KOH solution at 10-100℃, and the wet etching time is 5 minutes to 10 hours.

7. The preparation process according to claim 1, characterized in that, The preset width of the single-crystal silicon thin-walled structure is less than 1 μm.

8. The preparation process according to claim 1, characterized in that, The width of the single-crystal silicon nanowires is 10-800 nm.

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