Polynomial operation circuit and signal processing device
By employing an alternating design of multipliers and adders in the signal processing device, combined with a pipelined register, the polynomial operation circuit structure is simplified, the problem of low frequency caused by long operation paths is solved, and the operation efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PANGO MICROSYST CO LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-07-14
AI Technical Summary
In existing signal processing techniques, polynomial operation circuits have long operation paths, resulting in low operating frequencies, especially at higher orders where the problem becomes more pronounced.
The design employs multiple multipliers and adders that are alternately connected in sequence, combined with the use of pipelined registers, which simplifies the arithmetic circuit structure, reduces the number of arithmetic units, and increases the operating frequency.
By reducing the number of multipliers and optimizing the circuit structure, the operating frequency of the polynomial operation circuit was increased, especially at higher orders.
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Figure CN115774542B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, specifically to a polynomial operation circuit and a signal processing device. Background Technology
[0002] Signal processing technology is increasingly widely used in fields such as data monitoring and graphics processing. Current signal processing techniques, such as signal fitting, typically involve polynomial fitting of floating-point numbers. This means converting the input signal into a floating-point number conforming to the IEEE 754 standard before feeding it into a polynomial arithmetic processing circuit to perform calculations and obtain the fitted result.
[0003] However, the computational complexity of polynomial fitting is affected by the order and coefficients of the polynomial; as the order increases, the computational area increases linearly. For example, the fitting formula for a 4th-order polynomial is y = a⁴x. 4 +a3x 3 +a2x 2 +a1x+a0. The architecture of the circuit for implementing the operation of a 4th-order polynomial is as follows: Figure 1 As shown. In Figure 1 In the diagram, the arithmetic circuit implementing the fourth-order polynomial includes eight floating-point multipliers and four floating-point adders (here we consider all floating-point computation units to be combinational logic). Because the computation path of this circuit is relatively long, for example... Figure 1 The operations in the polynomial arithmetic circuit require four floating-point multiplications and two floating-point additions. Combined with the relatively long path of floating-point operations, this results in a low operating frequency for the entire polynomial arithmetic circuit. Generalizing this to higher orders yields a floating-point polynomial multiplier (N...). mult ) and adder (N add ) in polynomial order (N) Tap The relationship between N and N is: mult =2×N Tap -1, N add =N Tap Therefore, the higher the order of the floating-point polynomial, the lower the operating frequency of the entire polynomial operation circuit. Summary of the Invention
[0004] To address the aforementioned shortcomings of polynomial operation processing circuits in signal processing devices, this application provides a polynomial operation circuit and a signal processing device that reduce the number of operation units in polynomial operations, simplify the operation circuit structure, reduce computational costs, and increase the operating frequency of the polynomial operation circuit.
[0005] On one hand, an embodiment of this application provides a polynomial operation circuit comprising: a plurality of multipliers; a plurality of adders corresponding one-to-one with the plurality of multipliers, wherein the plurality of adders alternate with the plurality of multipliers and are connected sequentially; wherein each of the multipliers includes a first multiplication input terminal, a second multiplication input terminal, and a multiplication output terminal, and each of the adders includes a first addition input terminal, a second addition input terminal, and an addition output terminal; the plurality of second multiplication input terminals of the plurality of multipliers are connected to each other, the multiplication output terminal of a target multiplier among the plurality of multipliers is connected to the second addition input terminal of a target adder corresponding to the target multiplier, and the addition output terminal of the target adder is connected to the first multiplication input terminal of a multiplier of one lower order than the target multiplier.
[0006] Furthermore, the polynomial operation circuit is used to calculate floating-point polynomials, the number of the plurality of adders and the number of the plurality of multipliers are equal to the highest order of the floating-point polynomial, and the plurality of adders and the plurality of multipliers correspond to the order of the multi-order variables of the floating-point polynomial.
[0007] Furthermore, the second multiplication input of each of the plurality of multipliers is used to input the variables of the floating-point polynomial; the first addition input of the adder is used to input the coefficients in the floating-point polynomial that correspond to the order one lower than that of the adder.
[0008] Furthermore, the polynomial operation circuit also includes a first pipelined register, which is connected between the second multiplication input terminals of each of the two adjacent multipliers.
[0009] Furthermore, the polynomial operation circuit also includes a second pipeline register, which is connected between the addition output of the adder and the first multiplication input of a multiplier of a lower order than the adder.
[0010] Furthermore, each of the multipliers has a built-in third pipeline register.
[0011] Furthermore, each of the adders has a built-in fourth pipeline register.
[0012] Furthermore, the polynomial operation circuit also includes a fifth pipelined register and a sixth pipelined register, which are connected and disposed between the second multiplication input terminals of two adjacent multipliers.
[0013] On the other hand, an embodiment of this application provides a signal processing device, for example, including the polynomial operation circuit described in any of the foregoing claims.
[0014] Furthermore, the signal processing device also includes a signal conversion module, which is connected to the polynomial operation circuit.
[0015] This application's embodiments, by employing a design that alternates and sequentially connects multiple multipliers and multiple adders, can reduce the number of arithmetic units, such as multipliers, in polynomial operations, simplify the arithmetic circuit structure, lower computational costs, and increase the operating frequency of the polynomial arithmetic circuit. The higher the order of the floating-point polynomial, the more floating-point multipliers are saved. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0017] Figure 1 This is a schematic diagram of the logic structure of a polynomial operation circuit in the prior art.
[0018] Figure 2 This is a schematic diagram of the structure of a signal processing device provided in an embodiment of this application.
[0019] Figure 3 for Figure 2 The diagram shows a logic structure schematic of a polynomial operation circuit.
[0020] Figure 4 for Figure 3 The diagram shows a logical structure of a multiplier.
[0021] Figure 5 for Figure 3 The diagram shows a logical structure of an adder.
[0022] Figure 6 for Figure 2 The diagram shows another logic structure of a polynomial operation circuit.
[0023] Figure 7 for Figure 2 The diagram shows another logic structure of a polynomial operation circuit.
[0024] Figure 8 for Figure 3 The diagram shows another logic structure of a multiplier.
[0025] Figure 9 for Figure 3The diagram shows another logic structure of an adder.
[0026] Figure 10 for Figure 2 The diagram shows another logic structure of a polynomial operation circuit. Detailed Implementation
[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0028] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0030] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.
[0031] like Figure 2 As shown in the figure, this application provides a signal processing device 800. The signal processing device 800 is, for example, a signal processing device used in fields such as data monitoring and graphics processing, which needs to convert and fit the input signal.
[0032] Specifically, such as Figure 2As shown, the signal processing device 800 includes, for example, a signal conversion module 810 and a polynomial operation circuit 10. The signal conversion module is used to convert the input signal into a floating-point number. Here, the signal conversion module 810, for example, converts the signal into a floating-point number conforming to the IEEE 754 standard. The signal conversion module 810 here is, for example, a mature conversion circuit or unit in the prior art, and will not be described in detail here. The converted floating-point number can be represented by a polynomial. The polynomial operation circuit 10 is used to perform operations on the floating-point polynomial obtained by the signal conversion module 810 to obtain the result of the operation.
[0033] It is worth mentioning here that the floating-point polynomial y can be represented by the following equation (1):
[0034] y-(a N x N-1 +a N-1 x N-2 +a N-2 x N-2 +…+a2x 2 +a1x+a0 (I)
[0035] Decomposing the above equation (1) into an iterative structure yields the following equation (2):
[0036] y-(a N x N-1 +a N-1 x N-2 +a N-2 x N-3 +…+a2x 1 +a1)x+a0=((a N x N-2 +a N-1 x N-3 +a N-2 x N-4 +…+a3x 1 +a2)x+a1)x+a0=(((a N x N-3 +a N-1 x N-4 +a N-2 x N-5 +…+a4x+a3)x+a2)x+a1)x+a0=((…(((a N x+a N-1 )x+a N-2 )x+a N-3 )x+a N-4 …)x+a1)x+a0, (2)
[0037] Where N is greater than or equal to 1, x is a variable of a polynomial, {a N a N-1a N-2 {a1, a0} are the coefficients of the polynomial corresponding to each order of variable x. For example, a... N The coefficients of the Nth-order variable, a N-1 The coefficients are for variables of order (N-1). The maximum order of the polynomial y is N.
[0038] Specifically, such as Figure 3 As shown, the polynomial operation circuit 10 includes, for example, a plurality of multipliers 100 and a plurality of adders 200. The plurality of adders 200 correspond one-to-one with the plurality of multipliers 100, and the plurality of adders 200 and multipliers 100 are alternately connected and sequentially connected. For example, as... Figure 3 As shown, the multipliers arranged from left to right are: the Nth multiplier, the Nth adder, the (N-1)th multiplier, the (N-1)th adder, ..., the 1st multiplier, and the 1st adder.
[0039] More specifically, such as Figure 4 As shown, each of the multipliers 100 includes, for example, a first multiplication input 101, a second multiplication input 102, and a multiplication output 103. Figure 5 As shown, each adder 200 includes, for example, a first adder input terminal 201, a second adder input terminal 202, and an adder output terminal 203.
[0040] like Figure 3 As shown, the plurality of second multiplication input terminals 102 of the plurality of multipliers 100 are connected, the multiplication output terminal 103 of the target multiplier 100 among the plurality of multipliers 100 is connected to the second addition input terminal 202 of the target adder 200 corresponding to the target multiplier 100, and the addition output terminal 203 of the target adder 200 is connected to the first multiplication input terminal 101 of the multiplier 100 which is one order lower than the target multiplier 100.
[0041] Therefore, the polynomial operation circuit 10 can be used to calculate the floating-point polynomial y. The number of the plurality of adders 200 and the plurality of multipliers 100 are equal to the highest order N of the floating-point polynomial, and the plurality of adders 200 and the plurality of multipliers 100 correspond to the orders of the multi-order variables of the floating-point polynomial. For example, the Nth multiplier corresponds to the Nth-order variable X. N .
[0042] Specifically, the second multiplication input terminal 102 of each of the plurality of multipliers 100 is used to input the variable x of the floating-point polynomial, and is used to perform multiplication operations with the value input at the first multiplication input terminal 101 of the multiplier 100 of that order. The first addition input terminal 201 of the adder 200 is used to input the coefficients in the floating-point polynomial that correspond to the order one lower than that of the adder 200.
[0043] For example, in the polynomial operation circuit 10, the second multiplication inputs 102 of the N multipliers are all input to the variable x. The first multiplication input 101 of the Nth multiplier is input to the coefficient a of the Nth-order variable x. N . x and a N The result of the Nth multiplication operation is output through the multiplication output terminal 103 of the Nth multiplier to the second addition input terminal 202 of the Nth adder. The coefficient a of the (N-1)th order variable x is input to the first addition input terminal 201 of the Nth adder. N-1 The result is then added to the result output by the multiplication output terminal 103 of the Nth multiplier to obtain the Nth addition result. This process continues until the first adder performs the addition operation to obtain the first addition result, which is the result of the polynomial operation.
[0044] In this way, only N multipliers and N adders are used in this application, which reduces the number of multipliers compared to the prior art. That is, by adopting a design in which multiple multipliers 100 and multiple adders 200 are alternately connected in sequence, the number of arithmetic units in polynomial operations can be reduced, the arithmetic circuit structure can be simplified, the computational cost can be reduced, and the operating frequency of the polynomial arithmetic circuit can be increased.
[0045] Preferably, such as Figure 6 As shown, the polynomial operation circuit 10 may further include a first pipeline register 300. The first pipeline register 300 is connected between the second multiplication input terminals 102 of each of two adjacent multipliers 100 for storage. A pipeline register stores the calculation result of a certain pipeline stage during the operation, allowing the stored data or calculation result to be directly retrieved from the pipeline register when executing the next pipeline stage to complete the calculation of the next pipeline stage. The pipeline register can separate the work of each stage, preventing mutual interference, saving the processing results of each stage, and passing them to subsequent stages. Furthermore, a first pipeline register 300 is set between the second multiplication input terminals 102 of any two adjacent multipliers 100, that is, a total of N-1 first pipeline registers 300 are set. By setting the first pipeline registers 300, the problem of low operating frequency caused by excessive line delay can be solved, improving the efficiency of the operation.
[0046] More preferably, such as Figure 7 As shown, the polynomial operation circuit 10 further includes, for example, a second pipelined register 400, which is connected between the addition output terminal 203 of the adder 200 and the first multiplication input terminal 101 of the multiplier 100, which is one order lower than the adder 200. For example, the second pipelined register 400 is provided between the addition output terminal 203 of the Nth adder and the first multiplication input terminal 101 of the (N-1)th multiplier. By providing the second pipelined register 400, the problem of low operating frequency caused by excessive line delay can be further solved, and the efficiency of computation processing can be improved.
[0047] In other embodiments of this application, such as Figure 8 and Figure 9 As shown, in the polynomial operation circuit 10, each multiplier 100 has a built-in third pipeline register 110, and each adder 200 has a built-in fourth pipeline register 210.
[0048] Accordingly, such as Figure 10 As shown, the polynomial operation circuit 10 also includes, for example, a fifth pipeline register 500 and a sixth pipeline register 600, which are connected and disposed between the second multiplication input terminals 102 of each of the two adjacent multipliers 100.
[0049] For example, Figure 10 As shown, a fifth pipelined register 500 and a sixth register 600 are provided between the second multiplication input terminal 102 of the Nth multiplier and the second multiplication input terminal 102 of the (N-1)th multiplier. Preferably, a fifth pipelined register 500 and a sixth pipelined register 600 are provided between the second multiplication input terminals 102 of any two adjacent multipliers 100. By embedding pipelined registers in the multipliers and adders respectively, and providing fifth and sixth pipelined registers at the second multiplication input terminals of adjacent multipliers, the problem of low operating frequency caused by excessive line delay can be solved, thereby improving the efficiency of computation and processing.
[0050] In summary, the embodiments of this application, by employing a design in which multiple multipliers 100 and multiple adders 200 are alternately and sequentially connected, can reduce the number of arithmetic units such as multipliers in polynomial operations, simplify the arithmetic circuit structure, reduce computational costs, and increase the operating frequency of the polynomial arithmetic circuit. The higher the order N of the floating-point polynomial, the more floating-point multipliers are saved. By setting a first pipeline register 300, the problem of low operating frequency caused by excessive line delay can be solved, improving the efficiency of arithmetic processing. By setting a second pipeline register 400, the problem of low operating frequency caused by excessive line delay can be further solved, and the efficiency of arithmetic processing can be improved. By embedding pipeline registers in the multipliers and adders respectively, and setting a fifth and sixth pipeline register at the second multiplication input of two adjacent multipliers, the problem of low operating frequency caused by excessive line delay can also be solved, improving the efficiency of arithmetic processing.
[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A polynomial operation circuit, characterized in that, include: Multiple multipliers; Multiple adders correspond one-to-one with multiple multipliers, and the multiple adders and multiple multipliers alternate and are connected in sequence; Each of the multipliers includes a first multiplication input terminal, a second multiplication input terminal, and a multiplication output terminal, and each of the adders includes a first addition input terminal, a second addition input terminal, and an addition output terminal; The plurality of second multiplication inputs of the plurality of multipliers are connected together, the multiplication output of the target multiplier among the plurality of multipliers is connected to the second addition input of the target adder corresponding to the target multiplier, and the addition output of the target adder is connected to the first multiplication input of the multiplier which is one order lower than the target multiplier; The polynomial operation circuit is used to calculate floating-point polynomials. The number of the plurality of adders and the plurality of multipliers are equal to the highest order of the floating-point polynomial, and the plurality of adders and the plurality of multipliers correspond to the order of the multi-order variables of the floating-point polynomial, respectively. The second multiplication input of each of the plurality of multipliers is used to input the variables of the floating-point polynomial; the first addition input of the adder is used to input the coefficients of the floating-point polynomial that are one order lower than the order of the adder.
2. The polynomial operation circuit as described in claim 1, characterized in that, The polynomial operation circuit further includes a first pipelined register, which is connected between the second multiplication inputs of two adjacent multipliers.
3. The polynomial operation circuit as described in claim 2, characterized in that, The polynomial operation circuit further includes a second pipelined register, which is connected between the addition output of the adder and the first multiplication input of a multiplier of a lower order than the adder.
4. The polynomial operation circuit as described in claim 1, characterized in that, Each of the multipliers has a built-in third pipeline register.
5. The polynomial operation circuit as described in claim 4, characterized in that, Each of the adders has a built-in fourth pipeline register.
6. The polynomial operation circuit according to claim 5, characterized in that, The polynomial operation circuit also includes a fifth pipelined register and a sixth pipelined register, which are connected and disposed between the second multiplication input terminals of two adjacent multipliers.
7. A signal processing apparatus, characterized in that, Includes the polynomial operation circuit as described in any one of claims 1-6.
8. The signal processing apparatus according to claim 7, characterized in that, The signal processing device further includes a signal conversion module, which is connected to the polynomial operation circuit.