A method of accessing shared memory and a data processing apparatus

Abstract

A method for accessing shared memory comprises: after obtaining an instruction, determining a target quotient and a target remainder according to an address carried by the instruction and a preset prime number; determining a target memory bank group corresponding to the target remainder, determining a storage space corresponding to the address in the target memory bank group according to the target quotient, and then executing an operation corresponding to the target instruction on data of the storage space. When the difference between two addresses is an integer power of 2, the probability that the two remainders obtained according to the above addresses are the same is small, resulting in a small possibility that the two addresses pass through the same channel at the same time, and thus the possibility of memory access conflict can be reduced. The application further provides a data processing device capable of implementing the above method for accessing shared memory.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method for accessing shared memory and a data processing apparatus. Background Technology

[0002] Shared memory is a large amount of memory in a multi-processor system that can be accessed simultaneously by different processors. Shared memory can facilitate communication between multi-core programs, avoid redundant copying, and improve read and write speeds.

[0003] One existing method for writing data from shared memory is roughly as follows: A write command is received via a port. Based on two bits of the address in the write command, a target memory subset is determined from all memory subsets, where the total number of memory subsets is a power of 2. The target memory within the target memory subset is determined based on three bits, and the storage space within the target memory is determined based on the remaining bits. Data is then written starting from this storage space.

[0004] In practical applications, the difference between addresses received simultaneously from two ports is usually a power of 2. This can easily lead to two addresses corresponding to the same subset of memory. In such memory access conflicts, arbitration is required to ensure that the two addresses pass through a single write channel sequentially before being transmitted to the subset of memory, which reduces data processing efficiency. Summary of the Invention

[0005] In view of this, this application provides a method for accessing shared memory, which can distribute storage addresses that differ by an integer power of 2 to different memory banks to reduce memory access conflicts.

[0006] The first aspect provides a method for accessing shared memory. This method includes: after fetching an instruction, determining a target quotient and a target remainder based on the address carried by the instruction and a preset prime number; then determining a target memory bank group corresponding to the target remainder; determining the storage space corresponding to the address within the target memory bank group based on the target quotient; and then executing the operation corresponding to the target instruction on the data in the storage space. The cache size of the shared memory is equal to the product of a prime number and an integer power of 2, meaning the cache size of the shared memory is not an integer power of 2. For such shared memory, when the difference between address 1 and address 2 is an integer power of 2, the quotient 1 and remainder 1 are determined based on address 1 and the prime number, and the quotient 2 and remainder 2 are determined based on address 2 and the prime number. Thus, the probability of remainder 1 and remainder 2 being the same is very small, and the probability of remainder 1 and remainder 2 corresponding to the same memory bank group is very small. Therefore, the possibility of two addresses being transmitted through the same channel simultaneously is low, thereby reducing the possibility of memory access conflicts.

[0007] In one possible implementation, determining the target quotient and target remainder based on the address and a preset prime number includes dividing the address by the prime number to obtain the target quotient and target remainder. This provides a method for calculating the quotient and remainder.

[0008] In another possible implementation, determining the target quotient and target remainder based on the address and a preset prime number includes:

[0009] Step A: Divide the address by the divisor to obtain the first quotient and the first remainder;

[0010] Step B: Store the first quotient;

[0011] Step C: Determine that the target dividend is equal to the product of the difference and the first quotient plus the first remainder;

[0012] Step D: Divide the target dividend by the divisor to obtain the second quotient and the second remainder.

[0013] Step E: When the second quotient is not equal to 0, update the first quotient to the second quotient and the first remainder to the second remainder, triggering steps B to D, until the second quotient equals 0;

[0014] Step F: When the second quotient is equal to 0 and the second remainder is less than a prime number, determine the target quotient as the sum of all stored first quotients, and determine the target remainder as the second remainder;

[0015] Step G: When the second quotient is equal to 0 and the second remainder is greater than or equal to a prime number, determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus a prime number.

[0016] This provides a method for calculating the target quotient and target remainder, which is applicable to digital circuits.

[0017] In another possible implementation, determining the storage space corresponding to the address in the target memory bank group based on the target quotient includes: determining the target memory bank of the target memory bank group based on the first part of the target quotient; and determining the storage space corresponding to the address in the target memory bank based on the second part of the target quotient. Optionally, the first part is 3 bits and the second part is 12 bits.

[0018] A second aspect provides a data processing apparatus, which includes a processing module and shared memory. The processing module is used to acquire instructions carrying addresses. The shared memory includes a division module, an interleaving module, and a cache. The division module is used to determine a target quotient and a target remainder based on the address and a preset prime number. The cache size of the shared memory is equal to the product of the prime number and an integer power of 2. The module determines a target memory bank group corresponding to the target remainder. The interleaving module is used to determine the storage space corresponding to the address in the target memory bank group based on the target quotient. The cache is used to execute the operation corresponding to the target instruction on the data in the storage space.

[0019] In one possible implementation, the division module is specifically used to divide the address by a prime number to obtain the target quotient and the target remainder.

[0020] In another possible implementation, the division module is specifically used to perform the following steps:

[0021] Step A: Divide the address by the divisor to obtain the first quotient and the first remainder;

[0022] Step B: Store the first quotient;

[0023] Step C: Determine that the target dividend is equal to the product of the difference and the first quotient plus the first remainder;

[0024] Step D: Divide the target dividend by the divisor to obtain the second quotient and the second remainder.

[0025] Step E: When the second quotient is not equal to 0, update the first quotient to the second quotient and the first remainder to the second remainder, triggering steps B to D, until the second quotient equals 0;

[0026] Step F: When the second quotient is equal to 0 and the second remainder is less than a prime number, determine the target quotient as the sum of all stored first quotients, and determine the target remainder as the second remainder;

[0027] Step G: When the second quotient is equal to 0 and the second remainder is greater than or equal to a prime number, determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus a prime number.

[0028] In another possible implementation, the interleaving module is specifically used to determine the target memory bank of the target memory bank group based on the first part of the target quotient; and to determine the storage space corresponding to the address in the target memory bank based on the second part of the target quotient.

[0029] In another possible implementation, the division module includes *a* division units, each of which includes *b* ports, *b* dividers, and *b*b* channels, with a one-to-one correspondence between ports and dividers; the interleaving module includes *b* interleaving units, each of which includes *a** channels; and there is one channel pair between the *i*-th division unit and the *j*-th interleaving unit. *a* and *b* are positive integers, *i* is a positive integer not greater than *a*, and *j* is a positive integer not greater than *b*.

[0030] The explanation of the names in the second aspect, the steps performed by each unit in the data processing device, and the beneficial effects can be found in the corresponding description in the first aspect.

[0031] The third aspect provides a shared memory, which is used to receive instructions carrying addresses; determine the target quotient and target remainder based on the address and a preset prime number, the cache size of the shared memory is equal to the product of the prime number and an integer power of 2; determine the target memory bank group corresponding to the target remainder; determine the storage space corresponding to the address in the target memory bank group based on the target quotient; and execute the operation corresponding to the target instruction on the data in the storage space.

[0032] In one possible implementation, the shared memory includes a port, a division unit, an interleaving unit, and a cache; the port is used to receive instructions carrying addresses; the division unit is used to determine the target quotient and target remainder based on the address and a preset prime number; the cache size of the shared memory is equal to the product of the prime number and an integer power of 2; the interleaving unit is used to determine the target memory bank group corresponding to the target remainder; the cache is used to determine the storage space corresponding to the address in the target memory bank group based on the target quotient; and the operation corresponding to the target instruction is performed on the data in the storage space.

[0033] The fourth aspect provides a computing device including a processor and a memory. The processor is used to fetch instructions carrying addresses; the memory is used to determine a target quotient and a target remainder based on the address and a preset prime number, wherein the cache size of the shared memory is equal to the product of the prime number and an integer power of 2; to determine a target memory bank group corresponding to the target remainder; to determine the storage space corresponding to the address in the target memory bank group based on the target quotient; and to execute the operation corresponding to the target instruction on the data in the storage space.

[0034] The fifth aspect provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method of the first aspect.

[0035] The sixth aspect provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the method of the first aspect.

[0036] A seventh aspect provides a chip system including a plurality of processors coupled to a memory for storing computer programs or instructions, the processors for executing the computer programs or instructions to implement the method of the first aspect. Attached Figure Description

[0037] Figure 1 This is a structural diagram of a data processing device in an embodiment of this application;

[0038] Figure 2 A diagram of the existing shared memory structure;

[0039] Figure 3 This is a schematic diagram showing the correspondence between the addresses, intra-cell channels, and inter-cell channels of an existing first-level interleaving unit;

[0040] Figure 4 This is a schematic diagram illustrating the correspondence between addresses and storage spaces in existing shared memory.

[0041] Figure 5 A diagram illustrating address conflicts in existing shared memory;

[0042] Figure 6 This is a flowchart of a method for accessing shared memory in an embodiment of this application;

[0043] Figure 7 This is a flowchart illustrating the calculation of the target quotient and target remainder in an embodiment of this application;

[0044] Figure 8 This is another structural diagram of the data processing device in the embodiments of this application;

[0045] Figure 9 This is a structural diagram of shared memory in an embodiment of this application;

[0046] Figure 10 This is a schematic diagram of a method for accessing shared memory in an embodiment of this application;

[0047] Figure 11 This is a schematic diagram illustrating the correspondence between addresses and storage spaces in an embodiment of this application;

[0048] Figure 12 This is a structural diagram of a computing device in an embodiment of this application. Detailed Implementation

[0049] The method for accessing shared memory described in this application can be applied to data processing devices that include shared memory. The data processing device can be a system-on-a-chip (SoC), a computing device, or a computing device with a virtual machine deployed. An SoC is a complete system integrated on a single chip, a technique that groups all or some of the necessary electronic circuitry together. A complete system generally includes a central processing unit (CPU), memory, and peripheral circuitry.

[0050] See Figure 1 In one example, the data processing device 10 includes processing cores 111, 112, 113, and 114, intellectual property units 12, and shared memory 13 connected via a bus 14. It should be understood that the number of processing cores, intellectual property units, and shared memory in the multi-core device 10 is not limited to the examples above.

[0051] The following describes an existing 24-port shared memory architecture. (See also...) Figure 2 In one example, shared memory 13 includes interleaving units 211, 212, 213, 214, 215, 216, 217, 218, 221, 222, 223, 224, and memory bank groups 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, and 246. It should be understood that the number of interleaving units and memory bank groups in shared memory 13 is not limited to the examples above.

[0052] Interleaving units 211, 212, 213, 214, 215, 216, 217, and 218 belong to the first-level interleaving units. Interleaving units 221, 222, 223, and 224 belong to the second-level interleaving units. The i-th first-level interleaving unit and the j-th second-level interleaving unit are connected by one pair of channels. 1≤i≤8, 1≤j≤4, where i and j are positive integers. The channels between first-level and second-level interleaving units can be considered as inter-unit channels.

[0053] The first-level interleaving unit consists of 3 ports and 12 pairs of channels. Each port connects to 4 pairs of channels, and the 12 pairs of channels are intra-unit channels. In each pair of channels, one channel is used for reading data, and the other channel is used for writing data. The bits corresponding to the 4 pairs of channels are 00, 01, 10, and 11, respectively. In this way, the first-level interleaving unit can find the second-level interleaving unit connected to the subset of the target memory based on 2 bits.

[0054] For example, a 16-bit address can be represented as ADDR[15:0]. See also... Figure 3 Interleaving unit 211 includes ports 31, 32, and 33. Taking address 0x0000 as an example, port 31 of interleaving unit 211 receives the address. Based on the 3rd and 4th bits (i.e., 00) of address 1, interleaving unit 211 determines the corresponding inter-cell channel. The inter-cell channel corresponding to 00 is connected to interleaving unit 211, thus outputting the remaining part of the address to interleaving unit 221 through this channel.

[0055] Each second-level interleaving unit comprises 64 pairs of channels, which are intra-unit channels. Each second-level interleaving unit connects to a subset of memory banks through 8 pairs of channels. Each subset of memory banks comprises 4 memory bank groups, and each memory bank group comprises 2 memory banks. The number of channels for shared memory = 3*4*8*2 + 4*8*2 + 8*8*4*2 + 8*4*2 = 832 channels. The second-level interleaving unit can determine the memory bank within the subset of memory banks based on the remaining part of the address.

[0056] The correspondence between memory bank groups, memory banks, memory spaces, and addresses is shown in Table 1:

[0057] ADDR[15:5] Storage space within the storage unit ADDR[4] Storage bank number in storage bank group ADDR[3:0] Storage group number ADDR[3:2] Storage subset number

[0058] Table 1

[0059] ADDR[15:5] represents bits 6 to 16 of the address. ADDR[4] represents bit 5 of the address. ADDR[3:0] represents bits 1 to 4 of the address. ADDR[3:2] represents bits 3 to 4 of the address. It should be understood that the address order is from right to left.

[0060] The correspondence between addresses and storage spaces in the aforementioned shared memory is as follows: Figure 4 As shown. In each memory bank, adjacent addresses differ by 32. For the m-th memory bank group and the (m+1)-th memory bank group, the address of the k-th memory space of the n-th memory bank in the m-th memory bank group differs by 1 from the address of the k-th memory space of the n-th memory bank in the (m+1)-th memory bank group.

[0061] The following example illustrates the existing access sharing method; please refer to [link / reference]. Figure 5When multiple ports receive write commands simultaneously, the correspondence between the bits, interleaving units, and memory subsets corresponding to the port, command, address, and channel is shown in Table 2.

[0062] Port 31 Instruction 1 Ox0000 00 Interleaving unit 221 Storage subset 1 Port 32 Instruction 2 Ox0002 10 Interleaving unit 223 Storage subset 3 Port 33 Instruction 3 Ox0004 00 Interleaving unit 221 Storage subset 1

[0063] Table 2

[0064] As shown in Table 2, the bits corresponding to the two channels are 00, indicating that the inter-unit channels for instructions 1 and 3 are the same. This inter-unit channel refers to the channel between interleaving unit 211 and interleaving unit 221. Since a channel cannot transmit two addresses simultaneously, write instruction 1 and write instruction 3 conflict. When a conflict occurs, all instructions in the queue containing one instruction will be delayed by one clock cycle, which reduces program processing efficiency.

[0065] The address arrangement of existing addressing methods is as follows: Figure 4 As shown, this method requires the number of storage volumes in shared memory to be an integer power of 2. Figure 2 The shared memory shown uses 32 memory banks to meet bandwidth requirements, with a maximum bandwidth of 24 gigabytes per second. However, in practical applications, the number of memory banks required by applications is often not an integer power of 2. In such cases, a sufficiently large shared memory configuration is needed to meet the application's needs. For example, if the application requires 36 memory banks, then the application needs shared memory including 64 memory banks. Since only 36 memory banks are used, 28 of the 64 memory banks are idle. It can be seen that many memory banks in this shared memory are not fully utilized, resulting in a waste of storage resources. It should be noted that the more memory banks in a shared memory, the larger the area of ​​the shared memory. The area of ​​shared memory including 64 memory banks is approximately twice that of shared memory including 32 memory banks. When the on-chip system requires that the shared memory area cannot exceed a preset area, taking 50 memory banks as an example, a shared memory including 64 memory banks would not meet the requirements.

[0066] To address the aforementioned issues, this application provides a method for accessing shared memory, which calculates a target remainder based on the address and a prime number. When two addresses differ by a power of 2, the remainder points to different memory banks, thus distributing addresses across different channels and reducing the likelihood of memory access conflicts. The shared memory in this application does not have a number of memory banks that is a power of 2, allowing for the provision of shared memory in various sizes. For applications with bandwidth requirements that are not powers of 2, selecting appropriate shared memory can improve the utilization of storage resources. Compared to existing shared memory, the shared memory in this application can meet maximum bandwidth requirements with fewer memory banks, resulting in a smaller area and meeting the miniaturization requirements of chip designs.

[0067] See Figure 6 One embodiment of the method for accessing shared memory in this application includes:

[0068] Step 601: Receive the instruction carrying the address.

[0069] In this embodiment, the instruction can originate from the processing core or an intellectual property (IP) unit. After receiving the instruction, the shared memory can obtain the address carried by the instruction.

[0070] Step 602: Determine the target quotient and target remainder based on the address and the preset prime number.

[0071] The size of a shared memory cache is equal to the product of a prime number and a power of 2. The size of a single memory block can be a power of 2. Since the shared memory cache size is equal to the product of a prime number and a power of 2, the shared memory cache can be divided into M memory blocks. Let the prime number be P, then M = P * 2. n , where n is an integer.

[0072] Step 603: Determine the target memory group corresponding to the target remainder.

[0073] Shared memory can include, but is not limited to, P memory banks. There is a one-to-one correspondence between the remainder and the memory bank. If remainder 1 and remainder 2 are not equal, then the memory bank corresponding to remainder 1 is different from the memory bank corresponding to remainder 2, and therefore a single channel is not needed to transmit two addresses to a single memory bank simultaneously.

[0074] Step 604: Determine the storage space corresponding to the address in the target memory group based on the target quotient.

[0075] The size of the storage space can be set according to the actual situation, and there is no specific limit to the size. For example, a storage block may include 256 storage spaces. It should be understood that the depth of this storage block is 256.

[0076] Step 605: Execute the operation corresponding to the target instruction on the data in the storage space.

[0077] When the target instruction is a read instruction, data or an address is read from this memory space. When the target instruction is a write instruction, data or an address is written to this memory space.

[0078] This embodiment provides a method for determining the storage space corresponding to an address based on the quotient and remainder. When the difference between address 1 and address 2 is an integer power of 2, the quotient 1 and remainder 1 are determined based on address 1 and a prime number, and the quotient 2 and remainder 2 are determined based on address 2 and a prime number. This reduces the probability that remainder 1 and remainder 2 are the same, and similarly, reduces the probability that remainder 1 and remainder 2 correspond to the same memory bank group. Therefore, the likelihood of two addresses simultaneously passing through the same inter-unit channel is low, thus reducing the possibility of memory access conflicts.

[0079] Secondly, the cache size of the shared memory in this application is equal to the product of a prime number and an integer power of 2, meaning the number of storage units included in the shared memory is not an integer power of 2, thus providing a novel shared memory approach. When the number of storage units in the shared memory is less than the number of storage units in existing shared memory, the number of free storage units is reduced, effectively minimizing storage resource waste. For example, if the number of storage units in the shared memory is 24, and the application requires 36 storage units, then two shared memory modules (i.e., 48 storage units) need to be configured, leaving only 12 free shared memory units. Compared to existing technologies, this shared memory has higher resource utilization, thus reducing storage resource waste.

[0080] Furthermore, the shared memory of this application can meet bandwidth requirements with fewer storage banks. For example, the shared memory of this application only requires 24 storage banks to meet the bandwidth requirement of 24 gigabytes per second. Compared with existing shared memory, such shared memory occupies a smaller area and is more in line with the miniaturization design requirements of on-chip systems.

[0081] In an optional embodiment, step 602 includes: dividing the address by a prime number to obtain a target quotient and a target remainder.

[0082] In this embodiment, since addresses are not divisible by prime numbers, the probability of different addresses having the same remainder after being divided by a prime number is relatively small. For example, address 1 is 0x0000, address 2 is 0x0004, and the prime number is 3. After dividing address 1 by 3, the remainder is 0, while the remainder after dividing address 2 by 3 is 1. Since 0 and 1 correspond to different memory banks, transmitting address 0 and address 1 simultaneously through different channels will not cause memory access conflicts. Since the difference between different addresses is usually an integer power of 2, and prime numbers are not divisible by integer powers of 2, addresses can be distributed across different memory banks, i.e., a hash method can be used to obtain the target quotient and target remainder.

[0083] See Figure 7 In another alternative embodiment, step 602 includes:

[0084] Step 701: Divide the address by a preset divisor to obtain the first quotient and the first remainder.

[0085] Optionally, the divisor is the smallest value chosen from the integer powers of 2 that are greater than the prime number.

[0086] Alternatively, the divisor d is an integer power of 2, and the prime number p and the divisor d satisfy the following formula:

[0087]

[0088] The prime numbers can be set according to the shared memory cache size or the number of ports; this application does not impose any restrictions. For example, p is 3 and d is 4. p is 5 and d is 8.

[0089] Step 702: Store the first quotient.

[0090] Step 703: Determine that the target dividend is equal to the product of the preset difference and the first quotient plus the first remainder.

[0091] Specifically, the difference Δx, the divisor d, and the prime number p satisfy the following formula:

[0092] Δx = dp.

[0093] The difference Δx, the first quotient q1, the first remainder r1, and the target dividend sum satisfy the following formula:

[0094] sum = q1 * Δx + r1.

[0095] Step 704: Divide the target dividend by the divisor to obtain the second quotient and the second remainder.

[0096] Step 705: Determine if the second quotient is equal to 0. If yes, proceed to step 706; otherwise, proceed to step 707.

[0097] Step 706: When the second quotient is not equal to 0, update the first quotient to the second quotient and update the first remainder to the second remainder, triggering steps 702 to 704.

[0098] Step 707: When the second quotient is equal to 0, determine whether the second remainder is less than a prime number. If yes, proceed to step 708; otherwise, proceed to step 709.

[0099] Step 708: Determine the target quotient as the sum of all stored first quotients, and determine the target remainder as equal to the second remainder.

[0100] Step 709: Determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus the prime number.

[0101] To facilitate understanding, the process of finding the quotient and remainder will be explained through several examples below. In these examples, the addresses are represented in decimal.

[0102] In one example, the address is 193, the prime number is 5, the divisor is 8, and the difference is 3. The process of calculating the first quotient, the first remainder, the second quotient, and the second remainder is as follows:

[0103] 193 = 8 * 24 + 1, the first quotient is 24, and the first remainder is 1.

[0104] (24*3)+1=8*9+1, the second quotient is 9, and the second remainder is 1.

[0105] (9*3)+1=8*3+4, the second quotient is 3, and the second remainder is 4.

[0106] (3*3)+4=8*1+5, the second quotient is 1, and the second remainder is 5.

[0107] (1*3)+5=8*1+0, the second quotient is 1, and the second remainder is 0.

[0108] (1*3)+0=8*0+3, the second quotient is 0, and the second remainder is 3.

[0109] When the second quotient is 0, the second remainder is 3. Since the second remainder is less than 5, the target quotient is determined to be the sum of all stored first quotients. The stored first quotients include: 24, 9, 3, 1, and 1. The sum of all stored first quotients is 38, meaning the target quotient is 38. The target remainder is 3.

[0110] In another example, the address is 195, the prime number is 5, the divisor is 8, and the difference is 3. The process of calculating the first quotient, the first remainder, the second quotient, and the second remainder is as follows:

[0111] 195 = 8 * 24 + 3, the first quotient is 24, and the first remainder is 3.

[0112] (24*3)+3=8*9+3, the second quotient is 9, and the second remainder is 3.

[0113] (9*3)+3=8*3+6, the second quotient is 3, and the second remainder is 6.

[0114] (3*3)+6=8*1+7, the second quotient is 1, and the second remainder is 7.

[0115] (1*3)+7=8*1+2, the second quotient is 1, and the second remainder is 2.

[0116] (1*3)+2=8*0+5, the second quotient is 0, and the second remainder is 5.

[0117] When the second quotient is 0, the second remainder is 5. Since the second remainder is 5, the target quotient is determined to be the sum of all stored first quotients plus one. The stored first quotients include: 24, 9, 3, 1, and 1. The sum of all stored first quotients is 38. The target quotient = 38 + 1 = 39. The target remainder = 5 - 5 = 0.

[0118] In another example, the address is 196, the prime number is 5, the divisor is 8, and the difference is 3. The process of calculating the first quotient, the first remainder, the second quotient, and the second remainder is as follows:

[0119] 196 = 8 * 24 + 4, the first quotient is 24, and the first remainder is 4.

[0120] (24*3)+4=8*9+4, the second quotient is 9, and the second remainder is 4.

[0121] (9*3)+4=8*3+7, the second quotient is 3, and the second remainder is 7.

[0122] (3*3)+7=8*2+0, the second quotient is 2, and the second remainder is 0.

[0123] (2*3)+0=8*0+6, the second quotient is 0, and the second remainder is 6.

[0124] When the second quotient is 0, the second remainder is 6. Since the second remainder is greater than 5, the target quotient is determined to be the sum of all stored first quotients plus one. The stored first quotients include: 24, 9, 3, and 2. The sum of all stored first quotients is 38. The target quotient = 38 + 1 = 39. The target remainder = 6 - 5 = 1.

[0125] This provides a method for calculating the target quotient and target remainder, making the implementation of the scheme more flexible.

[0126] In another alternative embodiment, determining the storage space corresponding to the address in the target memory group based on the target quotient includes: determining the target memory of the target memory group based on a first part of the target quotient; and determining the storage space corresponding to the address in the target memory based on a second part of the target quotient.

[0127] Optionally, the first part of the quotient comprises 3 bits, and the second part comprises 12 bits. It should be understood that the number of bits in the first and second parts is not limited to the examples above. In one optional embodiment, the first part of the quotient consists of bits 1 to 3, and the second part consists of bits 4 to 15. It should be understood that the positions of the first and second parts in the quotient are not limited to the examples above.

[0128] See Figure 8 One embodiment of the data processing apparatus 80 of this application includes:

[0129] Processing module 81 and shared memory 82;

[0130] Processing module 81 is used to obtain instructions carrying addresses;

[0131] Shared memory 82 includes a division module 83, an interleaving module 84, and a cache 85;

[0132] The division module 83 is used to determine the target quotient and target remainder based on the address and a preset prime number. The cache size of the shared memory is equal to the product of the prime number and an integer power of 2. The module also determines the target memory block corresponding to the target remainder.

[0133] Interleaving module 84 is used to determine the storage space corresponding to the address in the target memory bank group based on the target quotient;

[0134] Cache 85 is used to perform operations corresponding to the target instructions on the data in the storage space.

[0135] In this embodiment, the processing module 81 can be a processing core or an intellectual property unit. Both the division module 83 and the interleaving module 84 include multiple pairs of channels; in each pair, one channel is a read channel and the other is a write channel. The remainder corresponds one-to-one with the memory bank group, and the remainder is the memory bank group number. The total number of ports in the shared memory is equal to the product of a prime number and an integer power of 2.

[0136] In an optional embodiment, the division module 83 includes *a* division units, each including *b* ports, *b* dividers, and *b*b* pairs of channels, with a one-to-one correspondence between ports and dividers; the interleaving module 83 includes *b* interleaving units, each including *a* pairs of channels, with one channel pair between the *i*th division unit and the *j*th interleaving unit. *a* and *b* are positive integers, *i* is a positive integer not greater than *a*, and *j* is a positive integer not greater than *b*. Optionally, the total number of ports in the shared memory is equal to *a*b.

[0137] To make it easier to understand, the following example illustrates shared memory 82:

[0138] See Figure 9The shared memory 82 includes division units 831, 832, 833, 834, 835, 836, 837, and 838; interleaving units 841, 842, and 843; and memory banks 8501, 8502, 8503, 8504, 8505, and 8506. Storage bank 8507, storage bank 8508, storage bank 8509, storage bank 8510, storage bank 8511, storage bank 8512, storage bank 8513, storage bank 8514, storage bank 8515, storage bank 8516, storage bank 8517, storage bank 8518, storage bank 8519, storage bank 8520, storage bank 8521, storage bank 8522, storage bank 8523 and storage bank 8524.

[0139] Division units 831, 832, 833, 834, 835, 836, 837, and 838 belong to division module 83. Each division unit in division module 83 includes three ports, each port connecting to a divider, and each divider connecting to three pairs of channels. Each division unit is connected to an interleaving unit through one pair of channels, and each interleaving unit is connected to a memory bank group through eight pairs of channels. Each memory bank group includes eight memory banks; for example, the first memory bank group includes memory banks 8501, 8502, 8503, 8504, 8505, 8506, 8507, and 8508. The second memory bank group includes memory banks 8509, 8510, 8511, 8512, 8513, 8514, 8515, and 8516. The third memory bank group includes memory banks 8517, 8518, 8519, 8520, 8521, 8522, 8523, and 8524.

[0140] The total number of channels for all division units = 3 * 3 * 8 * 2 = 144. The total number of channels for all interleaving units = 8 * 8 * 3 * 2 = 384. The channels between division units and interleaving units can be called inter-unit channels. The number of inter-unit channels = 3 * 8 * 2 = 48. The number of channels between interleaving units and the memory bank = 8 * 3 * 2 = 48. The total number of channels = 144 + 384 + 48 + 48 = 624.

[0141] The number of channels in the shared memory and Figure 2 Compared to the number of channels of shared memory shown, the number of channels of shared memory in this application (i.e., 624) is 208 fewer than the number of channels of existing shared memory (i.e., 832), which is a reduction of 25%.

[0142] Figure 9 The shared memory shown includes 24 ports, 8 division units, 3 interleaving units, and 24 memory banks. It should be understood that the number of ports, division units, interleaving units, and memory banks in the shared memory is not limited to the examples above.

[0143] See Figure 10 The following example illustrates the method for accessing shared memory in this application:

[0144] Taking the three addresses received by the three ports of division unit 831 as examples (0x0000, 0x0002, and 0x0004), and the prime number as 3, the inter-unit channels correspond to 0, 1, and 2 respectively. Dividing each of the three addresses by 3 using the divider yields remainders of 0, 1, and 2 respectively. Based on the correspondence between the remainders and channels, these remainders are output from the three inter-unit channels, allowing the three addresses to be passed to interleaving units 841, 842, and 843 respectively, thus preventing memory access conflicts. Similarly, when the addresses received by other ports differ by an integer power of 2, the probability of the same remainder is low, thereby reducing the possibility of memory access conflicts.

[0145] In another alternative embodiment, the division module 83 is specifically used to divide the address by a prime number to obtain the target quotient and the target remainder.

[0146] In another alternative embodiment, the division module 83 is specifically used to perform the following steps:

[0147] Step A: Divide the address by the divisor to obtain the first quotient and the first remainder;

[0148] Step B: Store the first quotient;

[0149] Step C: Determine that the target dividend is equal to the product of the difference and the first quotient plus the first remainder;

[0150] Step D: Divide the target dividend by the divisor to obtain the second quotient and the second remainder.

[0151] Step E: When the second quotient is not equal to 0, update the first quotient to the second quotient and the first remainder to the second remainder, triggering steps B to D, until the second quotient equals 0;

[0152] Step F: When the second quotient is equal to 0 and the second remainder is less than a prime number, determine the target quotient as the sum of all stored first quotients, and determine the target remainder as the second remainder;

[0153] Step G: When the second quotient is equal to 0 and the second remainder is greater than or equal to a prime number, determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus a prime number.

[0154] In another optional embodiment, the interleaving module 84 is specifically configured to determine the target memory bank of the target memory bank group based on a first part of the target quotient; and to determine the storage space corresponding to the address within the target memory bank based on a second part of the target quotient. The first part of the quotient is the number of the target memory bank in the target memory bank group. The second part of the quotient is the number of the storage space within the target memory bank.

[0155] In another alternative embodiment, within each memory bank, the address difference between adjacent memory spaces is a*b. The address difference between the k-th memory space of the n-th memory bank and the k-th memory space of the (n+1)-th memory bank is a. For the m-th memory bank group and the (m+1)-th memory bank group, the address difference between the k-th memory space of the n-th memory bank in the m-th memory bank group and the k-th memory space of the n-th memory bank in the (m+1)-th memory bank group is 1. m is an integer in [0, a-1]. n is an integer in [0, b-1]. k is an integer in [0, 2]. b-1 Integers in ].

[0156] In one example, a = 3, b = 8. The correspondence between the numbers and addresses of memory groups, memory banks, and memory spaces is as follows: Figure 11 As shown.

[0157] Within each memory bank, the address difference between adjacent memory spaces is 24. The address difference between the k-th memory space of the n-th memory bank and the k-th memory space of the (n+1)-th memory bank is 3.

[0158] For the m-th and (m+1)-th memory groups, the address difference between the k-th memory space of the n-th memory group in the m-th memory group and the k-th memory space of the n-th memory group in the (m+1)-th memory group is 1. m is an integer in [0, 2]. n is an integer in [0, 7]. k is an integer in [0, 255]. N / A indicates no address. That is, there are no addresses greater than 0xFFFF in the shared memory.

[0159] It should be understood that the values ​​of a and b are not limited to the examples above. The correspondence between the numbers and addresses of memory groups, memory banks, and memory spaces is not limited to... Figure 11 As shown in the diagram. The arrangement order or position can be set according to the actual situation.

[0160] Figure 8 The data processing device in the illustrated embodiment can achieve Figure 6 The method for accessing shared memory in an optional embodiment. Figure 8 For a glossary of terms, the steps performed by each module, and their beneficial effects in the illustrated embodiments, please refer to [link / reference needed]. Figure 6The corresponding descriptions in the illustrated embodiments or optional embodiments.

[0161] See Figure 12 One embodiment of the computing device 1200 provided in this application includes:

[0162] Processing cores 1211, 1212, 1213, and 1214, intellectual property unit 122, and shared memory 123 are connected via bus 124.

[0163] Shared memory 123 includes port 1231, divider 1232, memory bus 1233, and cache 1234.

[0164] In this embodiment, the processing cores 1211, 1212, 1213, and 1214 of the computing device 1200 can implement... Figure 8 The functions of the processing module 81 in the illustrated embodiment can be achieved through shared memory 123. Figure 8 The illustrated embodiment demonstrates the functions of the division module 83, the interleaving module 84, and the cache 85. The memory bus 1233 can implement... Figure 8 The function of the interleaving module 84 in the illustrated embodiment can also realize the channel function of the division unit 83.

[0165] It should be understood that the number of processing cores, intellectual property units, and shared memory in computing device 1200 are not limited to the examples above. Similarly, the number of ports 1231, dividers 1232, memory buses 1233, and caches 1234 in shared memory 123 are not limited to the examples above.

[0166] This application provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the method for accessing shared memory as described in the above embodiments or optional embodiments.

[0167] This application also provides a computer program product that, when run on a computer, causes the computer to perform a method for accessing shared memory as described in the above embodiments or alternative embodiments.

[0168] This application also provides a chip system comprising a processor and a memory coupled to each other. The memory stores computer programs or instructions, and the processor executes the computer programs or instructions stored in the memory to cause the chip system entity to perform the steps performed by the data processing device in the above embodiments. Optionally, the memory is on-chip memory, such as registers, caches, etc., or it can be off-chip memory located within a site, such as read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM), etc. The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for implementing the above-described methods of accessing shared memory.

[0169] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can specifically be implemented as one or more communication buses or signal lines.

[0170] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, and of course, it can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memory, special components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments of this application. The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for accessing shared memory, characterized in that, include: Retrieve the instruction carrying the address; The target quotient and target remainder are determined based on the address and a preset prime number, and the cache size of the shared memory is equal to the product of the prime number and an integer power of 2; Determine the target memory group corresponding to the target remainder; The storage space corresponding to the address in the target memory group is determined based on the target quotient. The operation corresponding to the instruction is executed on the data in the storage space.

2. The method according to claim 1, characterized in that, The step of determining the target quotient and target remainder based on the address and a preset prime number includes: Divide the address by the prime number to obtain the target quotient and the target remainder.

3. The method according to claim 1, characterized in that, The step of determining the target quotient and target remainder based on the address and a preset prime number includes: Step A: Divide the address by a preset divisor to obtain a first quotient and a first remainder, wherein the divisor is the smallest value selected from integer powers of 2 greater than the prime number; Step B: Store the first quotient; Step C: Determine that the target dividend is equal to the product of the preset difference and the first quotient plus the first remainder, wherein the difference is equal to the divisor minus the prime number; Step D: Divide the target dividend by the divisor to obtain the second quotient and the second remainder; Step E: When the second quotient is not equal to 0, update the first quotient to the second quotient and update the first remainder to the second remainder, triggering steps B to D until the second quotient equals 0; Step F: When the second quotient is equal to 0 and the second remainder is less than the prime number, determine that the target quotient is the sum of all the stored first quotients, and determine that the target remainder is the second remainder; Step G: When the second quotient is equal to 0 and the second remainder is greater than or equal to the prime number, determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus the prime number.

4. The method according to any one of claims 1 to 3, characterized in that, Determining the storage space corresponding to the address in the target memory group based on the target quotient includes: The target memory of the target memory group is determined based on the first part of the target quotient; The storage space corresponding to the address in the target memory is determined based on the second part of the target quotient.

5. A data processing apparatus, characterized in that, The data processing device includes a processing module and shared memory, and the shared memory includes a division module, an interleaving module and a cache. The processing module is used to obtain instructions carrying addresses; The division module is used to determine the target quotient and target remainder based on the address and a preset prime number, and the cache size of the shared memory is equal to the product of the prime number and an integer power of 2; Determine the target memory group corresponding to the target remainder; The interleaving module is used to determine the storage space corresponding to the address in the target memory group based on the target quotient; The cache is used to perform the operation corresponding to the instruction on the data in the storage space.

6. The data processing apparatus according to claim 5, characterized in that, The division module is specifically used to divide the address by the prime number to obtain the target quotient and the target remainder.

7. The data processing apparatus according to claim 5, characterized in that, The division module is specifically used to perform the following steps: Step A: Divide the address by the divisor to obtain a first quotient and a first remainder, wherein the divisor is the smallest value selected from the integer powers of 2 greater than the prime number; Step B: Store the first quotient; Step C: Determine that the target dividend is equal to the product of the difference and the first quotient plus the first remainder; Step D: Divide the target dividend by the divisor to obtain the second quotient and the second remainder; Step E: When the second quotient is not equal to 0, update the first quotient to the second quotient and update the first remainder to the second remainder, triggering steps B to D until the second quotient equals 0; Step F: When the second quotient is equal to 0 and the second remainder is less than the prime number, determine that the target quotient is the sum of all the stored first quotients, and determine that the target remainder is the second remainder; Step G: When the second quotient is equal to 0 and the second remainder is greater than or equal to the prime number, determine that the target quotient is equal to the sum of all stored first quotients plus one, and determine that the target remainder is equal to the second remainder minus the prime number.

8. The data processing apparatus according to any one of claims 5 to 7, characterized in that, The interleaving module is specifically used to determine the target memory of the target memory group based on the first part of the target quotient; and to determine the storage space in the target memory corresponding to the address based on the second part of the target quotient.

9. The data processing apparatus according to any one of claims 5 to 7, characterized in that, The division module includes *a* division units, each division unit including *b* ports, *b* dividers, and *b*... b pairs of channels, the ports and the dividers correspond one-to-one, and a and b are positive integers; The interleaving module includes b interleaving units, and each interleaving unit includes a a pair of channels; There is a pair of channels between the i-th division unit and the j-th interleaving unit, where i is a positive integer not greater than a and j is a positive integer not greater than b.

10. A computer-readable storage medium comprising instructions, characterized in that, When it is run on a computer, it causes the computer to perform the method as described in any one of claims 1 to 4.

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