Preventing unauthorized transition access using address signatures

Abstract

A host can use address translation to translate a virtual address to a physical address of an endpoint, which can then submit a memory access request to the physical address. The host can incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to the translation request. The endpoint can treat the incorporation as the translated address by storing the incorporation in an entry of a translation cache and accessing the entry included in the memory access request. The host can generate a signature of the translated address from the request using the private key and compare the result to the signature from the request. When the compared values match, the memory access request can be verified and the memory access can be performed using the translated address.

Description

Background Technology

[0001] PCI Express (PCIe) provides Address Translation Service (ATS), where a host can use a translation agent to translate virtual addresses provided by an endpoint (e.g., a device connected to the root port interface) into physical addresses in memory. The endpoint can cache the translations from the translation agent and subsequently use the physical address obtained from the cached translation to request a Direct Memory Access (DMA) transfer. This may eliminate the need for the translation agent to perform translations for DMA transfers, reducing memory access latency and the burden on the translation agent to perform address translations. Furthermore, the cache size used for address translation is scaled with the endpoint, not the host, which is more suitable for defining an appropriate cache size. However, when requesting a DMA transfer, there is a chance that the physical address included in the request is not the physical address that the endpoint is authorized to access. In various cases, such as when the endpoint corresponds to an external device, it may be unreliable that the endpoint will not attempt unauthorized access, and therefore ATS is often disabled. As a further complexity, the host may include multiple virtual machines (VMs), where the endpoint is part of a Trusted Execution Environment (TEE) of one VM and not another. In this scenario, the host should be able to ensure that the endpoint cannot access the VM's memory (which is not included in its TEE), but this may not be possible.

[0002] One method for preventing unauthorized endpoint access to physical memory using an ATS involves the managed software maintaining a separate table—per endpoint—that allows endpoints to access memory blocks containing that table. The host hardware can then cache and / or look up the table as needed to verify that the physical addresses included in DMA requests from endpoints are authorized for those endpoints. This shifts the scaling cache size back to the host, which is typically not in a position to define an appropriate cache size. Consequently, the latency of DMA requests using an ATS can be variable and uncertain because the host's cache is often too small to hold a large number of tables. Additionally, the managed software may need to be modified to handle cache invalidation when endpoint access is terminated. Summary of the Invention

[0003] Embodiments of this disclosure relate to using address signing to prevent unauthorized translational access. The systems and methods disclosed herein can verify whether a request for memory access from an endpoint using a translated address includes a cryptographically modified version of the translated address provided to the endpoint. The disclosed methods can be used to ensure that an endpoint is authorized for memory access.

[0004] Compared to conventional systems (such as those described above), the disclosed method can provide an endpoint with a cryptographically modified version of a second address translated from a first address. A request for memory access from said endpoint using the translated address can then be verified by determining that the request includes the cryptographically modified version of the translated address.

[0005] In at least one embodiment, the first address may be a virtual address and the second address may be a physical address. The cryptographically modified version of the second address may be a hash of the second address generated using a private key, and may be provided in response to a conversion request. For example, a combination of the hash and the second address (which is encrypted in some embodiments) may be included in the converted address field of a response to a conversion request, rather than being included separately in the converted address. An endpoint can treat the combination as a converted address by storing it in an entry in a conversion cache and accessing that entry to include it in a memory access request. To verify the memory access request, the converted address can be extracted from the request and hashed using the private key, and the result compared to the hash in the request. When the compared values ​​match, the memory access request can be verified, and memory access can be performed using the converted address. Attached Figure Description

[0006] The system and method for preventing unauthorized translational access using address signatures are described in detail below with reference to the accompanying drawings, wherein:

[0007] Figure 1 These are example diagrams of an address translation system according to some embodiments of the present disclosure;

[0008] Figure 2 The use of some embodiments according to this disclosure is illustrated. Figure 1 An example process for address signing in an address translation system to prevent unauthorized translation access;

[0009] Figure 3 This is a flowchart illustrating a method by which a host can use physical address signatures to prevent unauthorized translation access according to some embodiments of the present invention;

[0010] Figure 4 This is a flowchart illustrating a method by which a host can prevent unauthorized conversion access using a version of a passwordally modified address, according to some embodiments of the present invention;

[0011] Figure 5 This is a flowchart illustrating a method by which a device according to some embodiments of the present disclosure can use address signing to prevent unauthorized translation access;

[0012] Figure 6This is a block diagram of an example computing device suitable for implementing some embodiments of the present disclosure; and

[0013] Figure 7 This is a block diagram of an example data center suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0014] Systems and methods relating to preventing unauthorized translated access using address signatures are disclosed. The systems and methods disclosed herein can verify whether a request from an endpoint for memory access using a translated address includes a cryptographically modified version of the translated address provided to the endpoint. The disclosed methods can be used to ensure that an endpoint is authorized for memory access.

[0015] Compared to conventional systems (such as those described above), the disclosed method can provide the endpoint with a cryptographically modified version of a second address translated from the first address. A request from the endpoint for memory access using the translated address can then be verified by determining that the request includes the cryptographically modified version of the translated address.

[0016] In at least one embodiment, the first address may be a virtual address and the second address may be a physical address. A cryptographically modified version of the second address may be a hash (or other form of digital signature) of the second address generated using a private key, and may be provided in response to a conversion request. For example, a combination of the hash and the second address (which is encrypted in some embodiments) may be included in the converted address field of a response to a conversion request, rather than being included separately in the converted address. An endpoint can treat the combination as a converted address by storing it in an entry in a conversion cache and accessing that entry to include it in a memory access request. To verify the memory access request, the converted address can be extracted from the request and hashed using the private key, and the result compared to the hash in the request. When the compared values ​​match, the memory access request can be verified, and memory access can be performed using the converted address.

[0017] By way of example and not limitation, the disclosed method can be implemented using the Address Translation Service (ATS) provided by PCI Express (PCIe), whereby a host can use a translation agent to translate a virtual address provided by an endpoint (e.g., a device connected to a root port interface) into a physical address in memory. Instead of providing the physical address to the endpoint, the host can provide a cryptographically modified version of the physical address, in addition to or as an alternative to the physical address. For example, a combination of hash and physical address can be provided in the Translated Address field of the ATS protocol. Thus, the endpoint may not be aware that the received data has been cryptographically modified and may treat the data as a translated address. When the endpoint provides a memory access request for the translated address, it can subsequently include the received translated address in the Translated Address field of the ATS protocol. Therefore, this data can be used to verify whether the address included in the request is an address that the endpoint is authorized to access.

[0018] In at least one embodiment, the cache size for address translation can still scale with the endpoints because the host only needs to store keys used to verify memory access requests (e.g., one key per endpoint, process, and / or function). Additionally, the host can include multiple virtual machines (VMs), and an endpoint can be part of a trusted execution environment (TEE) of one VM rather than another. Using the disclosed method, the host can guarantee that an endpoint cannot access memory of a VM that is not included in its TEE.

[0019] The disclosed embodiments may be included in a variety of different systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aerial systems, inside systems, rowing systems, intelligent area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems implemented using edge devices, systems that combine one or more virtual machines (VMs), systems implemented at least partially in a data center, systems implemented at least partially using cloud computing resources, and / or other types of systems.

[0020] refer to Figure 1 , Figure 1This is an example diagram of an address translation system 100 according to some embodiments of the present disclosure. It should be understood that such and other arrangements described herein are merely illustrative examples. Other arrangements and elements (e.g., machines, interfaces, functions, sequences, functional groups, etc.) may be used in addition to or instead of the arrangements and elements shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that can be implemented as discrete or distributed components or combined with other components, and in any suitable combination and location. The various functions described herein as being performed by entities can be performed by hardware, firmware, and / or software. For example, the various functions can be implemented by a processor that executes instructions stored in memory.

[0021] Address translation system 100 may include host 102, one or more devices (such as device 104A and / or device 104B (which may also be collectively referred to as "device 104" or individually as "device 104")), managed software 106, one or more memories 108, one or more translation tables 110, and one or more verification entries 118, as well as other elements. Host 102 may include interface manager 112 and memory manager 114. Device 104A or 104B may include one or more translation caches, such as translation cache 120A of device 104A and translation cache 120B of device 104B (which may also be collectively referred to as "translation cache 120" or individually as "translation cache 120").

[0022] For the purposes of this overview, host 102 may host managed software 106, which may include managing the execution of managed software 106. Interface manager 112 may be configured to manage communication between host 102, managed software 106, and device 104. For example, device 104 may submit a request to access one or more portions of memory 108. Memory manager 114 may be configured to manage memory 108, for example, to facilitate access to one or more portions of memory 108. For example, memory manager 114 may perform functions such as translating memory addresses using translation tables 110, updating translation tables 110, reading data from or writing data to locations corresponding to memory addresses, and / or allocating one or more portions of memory to one or more entities of managed software 106. In one or more embodiments, memory manager 114 is configured to generate a cryptographically modified version of the translated addresses, which may be provided to one or more devices 104 for storage in one or more translation caches 120. Moreover, in at least one embodiment, the memory manager 114 may be configured to verify memory access requests based on a cryptographically modified version of the translated address, such as memory access requests provided by the device 104 using the translation cache 120.

[0023] As described herein, host 102 may host managed software 106, which may include managing the execution of managed software 106. Host 102 may include any combination of hardware, software, and / or firmware that facilitates the hosting of managed software 106. By way of example and not limitation, host 102 may include one or more virtual machine managers (VMMs) of virtualization software such as a hypervisor, and managed software 106 may include one or more virtual machines (VMs) supported by the hypervisor, such as guest operating systems. Additionally or alternatively, at least one entity of managed software 106 may include one or more processes, services, applications, and / or other software entities. Although verification entry 118, memory 108, managed software 106, translation table 110, and device 104 are shown outside host 102, any of these components may be included in host 102 and / or on a system-on-a-chip (SoC) of host 102. Furthermore, verification entry 118 and / or translation table 110 may be stored at least partially in memory 108 and / or in different memories. In at least one embodiment, memory 108 includes volatile memory, such as random access memory (RAM), which may include dynamic RAM (DRAM). In at least one embodiment, device 104 may include a VM or other software entity, such as the VM hosting software 106.

[0024] Interface Manager 112 can be configured to manage communication between Host 102, Hosting Software 106, and Device 104. Interface Manager 112 can support any of a variety of host controller interfaces, such as those for Universal Serial Bus (USB), FireWire, Bluetooth, Ethernet, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Near Field Communication (NFC), Vehicle-to-Everything (V2X), Car-to-Car, Cellular, WiFi, or other types of communication.

[0025] In at least one embodiment, interface manager 112 may provide address translation through one or more host controller interfaces, thereby enabling device 104 or other endpoints to access one or more portions of memory 108. When providing translation services, interface manager 112 may use memory manager 114 to translate addresses provided by device 104 or other endpoints into translated addresses in memory 108. Specifically, memory manager may use one or more translation tables 110 and / or other means to determine the translated address from the address. The translated address may be provided to device 104, which may store the translated address in translation cache 120. Subsequently, device 104 may use the translated address from translation cache 120 to provide a memory access request to memory 108. For example, device 104 may use the translated address to request a direct memory access (DMA) transfer with memory 108. By using the translated address, memory manager 114 does not need to perform DMA address translation.

[0026] In one or more embodiments, the address provided by device 104 may be a virtual address and the translated address may be a physical address of memory 108 determined using one or more translation tables 110 (e.g., page tables and / or address translation and protection tables). However, aspects of the invention are more generally applicable to address translation, which may or may not include virtual-to-physical address translation. As an example, in at least one embodiment, interface manager 112 supports PCIe and includes a root complex (RC) to provide address translation service (ATS), and device 104 can communicate with host 102 via a root port managed by the RC. When providing ATS, interface manager 112 may use a translation agent of memory manager 114 to translate virtual addresses, assuming device 104 is a physical address in memory 108. For example, memory manager 114 may include an input-output memory management unit (IOMMU) using one or more page tables of a system memory management unit (SMMU) for ATS.

[0027] When a DMA transfer is requested, there is a chance that the address provided by device 104 is not an address that device 104 is authorized to access. As a further layer of complexity, device 104 may be part of a Trusted Execution Environment (TEE) of a VM or other entity hosting software 106, rather than another. Embodiments of this disclosure allow host 102 to guarantee that device 104 cannot access one or more portions of memory 108 associated with a VM in which device 104 is not included in its TEE, even if device 104 provides a physical address associated with the VM. To this end, memory manager 114 may generate cryptographic information, such as a cryptographically modified version of a translated address, which may be provided to device 104 for storage in translation cache 120 of device 104. For example, memory manager 114 may provide cryptographic information in addition to or instead of a translated address. When device 104 provides a memory access request, memory manager 114 may cryptographically verify the request to determine whether the request is authorized. For example, memory manager 114 may determine whether the data provided by device 104 associated with the request matches or otherwise corresponds to the cryptographic information provided to device 104. If the memory manager 114 determines that the request does not correspond to password information, it may reject the request. In at least one embodiment, in response to an unauthorized request, a status code, such as an error or fault code, may be provided to the device 104.

[0028] The memory manager 114 can implement various potential pathways to generate cryptographic information. In at least one embodiment, the memory manager 114 can use one or more keys to cryptographically modify the translated address, such as a session key. A session key may refer to a key used to cryptographically modify data within a specific communication session, for example, using encryption (asymmetric or symmetric), hashing, cyclic redundancy check generation, salting out, expansion, and / or other cryptographic functions. In at least one embodiment, the session may be terminated in association with the invalidation of the endpoint's translation cache (e.g., upon determining that a predetermined period of time has elapsed, upon determining that the entity managing the software 106 has revoked access to and / or modified the translated address, upon determining that the translated address no longer belongs to the entity, based on termination of the entity owning the translated address, etc.).

[0029] In at least one embodiment, the memory manager 114 uses a key (e.g., a private key) to generate a digital signature, such as a hash, from the translated address. For example, the memory manager 114 may use a hash function to hash the translated address or data derived from or otherwise corresponding to the translated address. Non-limiting examples include MD5, SHA-1, RIPEMD-160, Whirlpool, SHA-2, SHA-3, BLAKE2, BLAKE3, etc. Additionally or alternatively, the memory manager 114 may use one or more keys to implement a message authentication code (MAC), such as hash-based MAC (HMAC). Additionally or alternatively, the memory manager 114 may encrypt the translated address, hash, MAC, and / or other data derived from or otherwise corresponding to it. For example, the memory manager 114 may encrypt a combination of the translated address and the hash.

[0030] Memory manager 114 can assign one or more keys to one or more specific entities (e.g., device 104), functions, processes, and / or converted addresses. Furthermore, memory manager 114 can store such assignments in verification entries 118 for cryptographically verifying future communications from entities and / or for providing cryptographic information to entities (e.g., in response to a conversion request). Memory manager 114 can generate and / or assign keys at any appropriate time.

[0031] In embodiments where managed software 106 includes a VM, memory manager 114 may assign keys to devices, functions, processes, etc., at least based on the movement of entities (e.g., endpoints) into the TEE of the VM. For example, in response to a request to move an entity into the TEE, memory manager 114 may generate one or more keys and / or assign one or more keys to the entity (e.g., one key or key pair per entity, process, and / or function). As a further example, keys may be generated or assigned in response to an address translation request from an entity. In various embodiments, entities do not receive any assigned keys from host 102, and keys may be stored in secure storage that is inaccessible to the entity (e.g., memory 108 and / or other memory) in verification entry 118. In at least one embodiment, memory manager 114 may store keys in verification entry 118 indexed by the entity, function, process, session, and / or the owner of the translated address (e.g., the VM that allocated the corresponding page) for later retrieval by memory manager 114. Alternatively or additionally, memory manager 114 may store cryptographic information generated using the keys in the corresponding entry in verification entry 118 (e.g., using an index).

[0032] The memory manager 114 can access the keys stored in the verification entry 118 to generate and / or provide password information corresponding to the translated address to an entity and / or verify one or more requests from that entity. For example, the memory manager 114 can use information provided by the entity and / or associated with the entity (e.g., in a request from the entity) as a lookup criterion to access the associated keys used to generate password information and / or pre-computed password information that can be stored in the index of the verification entry 118.

[0033] In at least one embodiment, cryptographic information is provided to device 104 in response to a conversion request. For example, memory manager 114 may include cryptographic information other than or replacing the conversion address. In at least one embodiment, memory manager 114 may receive a conversion request from device 104. Among other potential information, the conversion request may include data indicating the address to be converted (e.g., a virtual address). In response to the request, memory manager 114 may look up the address in conversion table 110 and receive the corresponding converted address (e.g., a system physical address). Memory manager 114 may also generate and / or retrieve cryptographic information associated with the converted address and include the cryptographic information in the response. For example, at least a portion of the cryptographic information may be included in at least a portion of the converted address field in the response (e.g., as specified by a communication protocol). By storing the cryptographic information in the converted address field, the cryptographic information can be provided to device 104 without modifying existing protocols and / or the various entities of address translation system 100. Furthermore, device 104 may not be able to distinguish the cryptographic information from the converted address.

[0034] In one or more embodiments, the response to the conversion request includes the converted address and cryptographic information. For example, the converted address may be N bits long, and the cryptographic information (e.g., a hash or signature) may be M bits long. The response may then include a combination of the converted address and M+N bits of cryptographic information. As an example, and not a limitation, the cryptographic information may be appended to the most significant bit (MSB) of the address to form a new value comprising the M bits of the cryptographic information, followed by the N bits of the converted address. However, the cryptographic information may be stored in another location or may be encoded by the bits. In embodiments that include encryption, the memory manager 114 may encrypt the combined cryptographic information and the converted address, for example, to reduce the probability that an entity could attack host 102 with a synthesized address.

[0035] By way of example and not limitation, the translation address field used to store the combined value can be anywhere from 40 to 80 bits long. In at least one embodiment, host 102 allocates fewer bits to the translated address than to the address to be translated (e.g., 48 or 40 bits for the physical address and 64 bits for the virtual address). At least some of the extra bits can be used to interpret cryptographic information. For example, if there are 40 bits for the physical address and 64 bits for the virtual address, then up to 24 bits can be used to store cryptographic information.

[0036] In at least one embodiment, memory manager 114 can verify a translated request based on cryptographic information associated with one or more translated addresses. For example, host 102 may receive a translated request (e.g., a memory access request, such as a DMA request) from device 104. Memory manager 114 can analyze cryptographic information extracted from the translated request to verify that the extracted cryptographic information corresponds to cryptographic information associated with a translated address authorized for requesting an endpoint, process, and / or function. In at least one embodiment, the cryptographic information may be extracted from the translated address field of the request (e.g., a signature may be extracted from the MSB, or otherwise extracted using knowledge of how and / or where the various items should be stored). Memory manager 114 can also retrieve associated keys and / or pre-computed cryptographic information for use in verifying the extracted cryptographic information.

[0037] If the memory manager 114 fails to recognize the assigned key or other cryptographic information, the request may result in an error or fault code, which may be provided to the device 104. In the case of identification information, the memory manager 114 may verify that the extracted cryptographic information matches or is otherwise cryptographically compatible with cryptographic information assigned to endpoints, processes, functions, etc. (e.g., the extracted signature matches a signature provided to an endpoint). In embodiments employing encryption, the memory manager 114 may first decrypt the cryptographic information using one or more retrieved keys, and then verify the decrypted cryptographic information (e.g., using another key to hash a potential transformed address). If one or more retrieved keys are used for verification, a signature or other cryptographic information for verification may be generated on the fly using one or more keys. Additionally or alternatively, pre-computed cryptographic information for verification may be retrieved from memory as described herein and compared with the value provided by the request.

[0038] If memory manager 114 determines that the password information does not match or is otherwise incompatible with the assigned password information, the request may result in an error or fault code, which may be provided to device 104. Otherwise, memory manager 114 may use the translated address provided by the request, for example, to perform a memory access at the corresponding location in memory 108. Memory manager 114 may also, in response to the request, provide device 104 with data indicating successful verification and / or execution of the translated request, such as a success code and / or retrieved data.

[0039] The disclosed method can be implemented entirely in hardware without requiring modification to the managed software 106. Furthermore, any latency added to the processing of the transformation service (e.g., encryption, signature computation, and verification of incoming signatures) can be fixed (e.g., a few clock cycles). This provides consistent and predictable timing to the transformation service, allowing the system to have deterministic performance and workload while avoiding bottlenecks.

[0040] See now Figure 2 , Figure 2 Some embodiments of the present disclosure are shown. Figure 1 Example process 200 for address signing in address translation system 100 to prevent unauthorized translation access. Process 200 may include device 104A providing translation request 202 (e.g., ATS request) to host 102. Interface manager 112 may receive translation request 202 and provide data corresponding to translation request 202 to memory manager 114. Memory manager 114 may use translation table 110 to perform translation 204 of the address provided in translation request 202. For example, memory manager 114 may retrieve the translated address from translation table 110. Memory manager 114 may also perform cryptographic function 206 to generate cryptographic information. This may include, for example, hashing the translated address with a key (and / or generating and storing a key or retrieving pre-generated cryptographic information in other examples) stored in authentication entry 118 for device 104A, function, and / or process. Memory manager 114 may provide cryptographic information and / or the translated address (e.g., a cryptographically modified version) for translation response 208, and interface manager 112 may provide device 104A.

[0041] Device 104A can perform a translation cache 210, such as an ATS completion, on the information extracted from the translation response 208 (e.g., the value in the translated address field), in translation cache 120A. Subsequently, device 104A can perform a cache access 212 of translation cache 120A to retrieve cached information, such as a DMA request, to be included in access request 214 (or translation request). Device 104A can provide access request 214 to host 102. Interface manager 112 can receive access request 214 and provide data corresponding to access request 214 to memory manager 114. Memory manager 114 can perform cryptographic verification 216 on the data provided in access request 214 (e.g., the value in the translated address field). For example, memory manager 114 can look up a key in verification entry 118 using device 104A, functions, and / or processes identified from or associated with access request 214. The memory manager 114 may use a key to hash the translated address extracted from the access request 214 (e.g., data in one or more access request 214 messages that occupies bits specified for the translated address and / or bits generated according to the translated address extraction algorithm), and compare the hashed address with a potential hash of the translated address extracted from the access request 214 (e.g., data in one or more access request 214 messages that occupies bits specified for the hash and / or bits generated according to the hash extraction algorithm).

[0042] If the hashed address (or more generally, the signature) matches a potential hash, memory manager 114 can determine that access request 214 is authorized. In response to determining that access request 214 is authorized, memory manager 114 can perform memory access 218 of memory 108 at the location corresponding to the translated address (e.g., to retrieve the corresponding page). In embodiments where memory access 218 is used to retrieve data, memory manager 114 can provide the data retrieved by memory access 218 to be included in one or more access responses 220 sent to device 104A. Otherwise, memory manager 114 can provide a status code or other indicator for a successful memory access to device 104A. In embodiments where the hashed address does not match a potential hash, the access response may include a status code or other indicator for an unsuccessful memory access, such as a fault or error code.

[0043] See now Figure 3Each block of method 300, and other methods described herein, includes a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, individual functions can be implemented by a processor executing instructions stored in memory. The methods can also be implemented as computer-usable instructions stored on a computer storage medium. The methods can be provided by a standalone application, service, or managed service (standalone or in combination with other managed services), or as a plug-in to another product, to name a few. Furthermore, by way of example, regarding Figure 1 The system describes the methods. However, these methods may be performed additionally or alternatively by any system or any combination of systems, including but not limited to those described herein.

[0044] Figure 3 This is a flowchart illustrating a method 300 by which a host can use a signature of a physical address to prevent unauthorized translation access according to some embodiments of the present invention. At block B302, method 300 includes generating a signature of the physical address. For example, the memory manager 114 of host 102 may generate a signature of the physical address translated from the virtual address based at least on a request for translation of the virtual address from device 104.

[0045] At box B304, method 300 includes providing data corresponding to the physical address and signature. For example, interface manager 112 may provide data corresponding to the signature and physical address to device 104 in response to a request to translate a virtual address.

[0046] At box B306, method 300 includes enabling memory access to the physical address based at least on determining that the request includes the signature and the physical address. For example, memory manager 114 may enable memory access to the physical address based at least on determining that the request for memory access includes a signature and a physical address.

[0047] Reference Figure 4 , Figure 4 This is a flowchart illustrating a method 400 by which a host can prevent unauthorized translation access using a cryptographically modified version of an address, according to some embodiments of the present invention. At block B402, method 400 includes providing a cryptographically modified version of a second address translated from a first address. For example, memory manager 114 may provide a cryptographically modified version of the second address translated from the first address, at least based on a request from device 104 to translate the first address.

[0048] At box B404, method 400 includes receiving a cryptographically modified version of the second address associated with the request. For example, memory manager 114 may receive a cryptographically modified version of the second address associated with a request from device 104 for a memory access transfer having the second address.

[0049] At box B406, method 400 includes initiating a memory access transfer based at least on a password-modified version of the second address. For example, memory manager 114 may initiate a memory access transfer with device 104 based at least on a password-modified version of the second address.

[0050] refer to Figure 5 , Figure 5 This is a flowchart illustrating a method 500 by which a device, according to some embodiments of the present invention, can use address signing to prevent unauthorized translation access. At block B502, method 500 includes receiving a cryptographically modified version of a second address translated from a first address. For example, device 104 may receive the cryptographically modified version of the second address translated from the first address from host 102 in response to a request from device 104 to translate the first address.

[0051] At block B504, method 500 includes providing a cryptographically modified version of a second address associated with the request. For example, device 104 may provide host 102 with a request for memory access to a second address, the request including a cryptographically modified version of the second address received in a response to the request.

[0052] At block B506, method 500 includes receiving data corresponding to a memory access to a second address based at least on a request for a cryptographically modified version including the second address. For example, device 104 may receive data corresponding to a memory access to a second address from host 102 based at least on a request for a memory access to a cryptographically modified version including the second address.

[0053] Example computing device

[0054] Figure 6The block diagram is provided for an example computing device 600 suitable for implementing some embodiments of the present disclosure. The computing device 600 may include an interconnect system 602 directly or indirectly coupled to the following devices: memory 604, one or more central processing units (CPUs) 606, one or more graphics processing units (GPUs) 608, a communication interface 610, input / output (I / O) ports 612, input / output components 614, a power supply 616, one or more presentation components 618 (e.g., displays), and one or more logic units 620. In at least one embodiment, the computing device 600 may include one or more virtual machines (VMs), and / or any component thereof may include virtual components (e.g., virtual hardware components). For a non-limiting example, one or more GPUs 608 may include one or more vGPUs, one or more CPUs 606 may include one or more vCPUs, and / or one or more logic units 620 may include one or more virtual logic units. Therefore, computing device 600 may include discrete components (e.g., a complete GPU dedicated to computing device 600), virtual components (e.g., a portion of the GPU dedicated to computing device 600), or a combination thereof.

[0055] although Figure 6 The various blocks are shown connected via an interconnect system 602 with wiring, but this is not intended to be limiting and is merely for clarity. For example, in some embodiments, a presentation component 618, such as a display device, may be considered an I / O component 614 (e.g., if the display is a touchscreen). As another example, CPU 606 and / or GPU 608 may include memory (e.g., memory 604 may represent a storage device other than the memory of GPU 608, CPU 606, and / or other components). In other words, Figure 6 The computing devices mentioned are merely illustrative. No distinction is made between categories such as "workstation," "server," "laptop," "desktop," "tablet," "client device," "mobile device," "handheld device," "game console," "electronic control unit (ECU)," "virtual reality system," and / or other device or system types, as all of these are considered within the same category. Figure 6 Within the scope of computing devices.

[0056] Interconnect system 602 may represent one or more links or buses, such as address buses, data buses, control buses, or combinations thereof. Interconnect system 602 may include one or more link or bus types, such as Industry Standard Architecture (ISA) bus, Extended Industry Standard Architecture (EISA) bus, Video Electronics Standards Association (VESA) bus, Peripheral Component Interconnect (PCI) bus, Peripheral Component Interconnect Fast (PCIe) bus, and / or another type of bus or link. In some embodiments, there is a direct connection between components. As an example, CPU 606 may be directly connected to memory 604. Furthermore, CPU 606 may be directly connected to GPU 608. In cases where there is a direct or point-to-point connection between components, interconnect system 602 may include a PCIe link to perform the connection. In these examples, a PCI bus is not required in computing device 600.

[0057] The memory 604 may include any medium of a wide variety of computer-readable media. A computer-readable medium can be any available medium that can be accessed by the computing device 600. Computer-readable media may include volatile and non-volatile media, as well as removable and non-removable media. For example and without limitation, computer-readable media may include computer storage media and communication media.

[0058] Computer storage media may include volatile and non-volatile media and / or removable and non-removable media, implemented in any way or by any method or technique for storing information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 604 may store computer-readable instructions (e.g., representing programs and / or program elements, such as an operating system). Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by computing device 600. As used herein, computer storage media does not include the signal itself.

[0059] Computer storage media may contain computer-readable instructions, data structures, program modules, and / or other data types in modulated data signals such as carrier waves or other transmission mechanisms, and include any information transport medium. The term "modulated data signal" can refer to a signal whose characteristics are set or altered in a manner that encodes information into that signal. For example and without limitation, computer storage media may include wired media such as wired networks or direct wired connections, and wireless media such as sound, RF, infrared, and other wireless media. Any combination of the above should also be included within the scope of computer-readable media.

[0060] CPU 606 may be configured to execute at least some of computer-readable instructions to control one or more components of computing device 600 to perform one or more of the methods and / or processes described herein. Each of CPU 606 may include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of processing a large number of software threads simultaneously. CPU 606 may include any type of processor and may include different types of processors depending on the type of computing device 600 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). For example, depending on the type of computing device 600, the processor may be an advanced RISC mechanism (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or supplementary coprocessors such as math coprocessors, computing device 600 may also include one or more CPUs 606.

[0061] In addition to or replacing CPU 606, GPU 608 may also be configured to execute at least some computer-readable instructions to control one or more components of computing device 600 to perform one or more of the methods and / or processes described herein. One or more GPUs 608 may be integrated GPUs (e.g., having one or more CPUs 606) and / or one or more GPUs 608 may be discrete GPUs. In embodiments, one or more GPUs 608 may be coprocessors of one or more CPUs 606. Computing device 600 may use GPU 608 to render graphics (e.g., 3D graphics) or perform general-purpose computing. For example, GPU 608 may be used for general-purpose computing on a GPU (GPGPU). GPU 608 may include hundreds or thousands of cores capable of processing hundreds or thousands of software threads simultaneously. GPU 608 may generate pixel data for outputting an image in response to rendering commands (e.g., rendering commands received via a host interface from CPU 606). GPU 608 may include graphics memory, such as display memory, for storing pixel data or any other suitable data (e.g., GPGPU data). Display memory may be included as part of memory 604. GPU 608 may include two or more GPUs operating in parallel (e.g., via links). The links may connect the GPUs directly (e.g., using NVLINK) or via a switch (e.g., using NVSwitch). When combined, each GPU 608 may generate different portions of pixel data or GPGPU data for different outputs (e.g., the first GPU for a first image, the second GPU for a second image). Each GPU may include its own memory or may share memory with other GPUs.

[0062] In addition to or replacing CPU 606 and / or GPU 608, logic unit 620 may be configured to execute at least some computer-readable instructions to control one or more components of computing device 600 to perform one or more methods and / or processes described herein. In embodiments, CPU 606, GPU 608, and / or logic unit 620 may perform any combination of methods, processes, and / or portions thereof discretely or jointly. One or more logic units 620 may be part of and / or integrated into one or more CPUs 606 and / or one or more GPUs 608, and / or one or more logic units 620 may be discrete components of CPU 606 and / or GPU 608 or otherwise external thereto. In embodiments, one or more logic units 620 may be processors of one or more CPUs 606 and / or one or more GPUs 608.

[0063] Examples of logic unit 620 include one or more processing cores and / or components thereof, such as data processing unit (DPU), tensor core (TC), tensor processing unit (TPU), pixel vision core (PVC), vision processing unit (VPU), graphics processing cluster (GPC), texture processing cluster (TPC), streaming multiprocessor (SM), tree traversal unit (TTU), artificial intelligence accelerator (AIA), deep learning accelerator (DLA), arithmetic logic unit (ALU)), application-specific integrated circuit (ASIC), floating-point unit (FPU), input / output (I / O) element, peripheral component interconnect (PCI) or peripheral component interconnect fast (PCIe) element, etc.

[0064] The communication interface 610 may include one or more receivers, transmitters, and / or transceivers that enable the computing device 600 to communicate with other computing devices via electronic communication networks, including wired and / or wireless communications. The communication interface 610 may include components and functions that enable communication via any of several different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communication via Ethernet or InfiniBand), low-power wide area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet. In one or more embodiments, one or more logic units 620 and / or the communication interface 610 may include one or more data processing units (DPUs) for directly transmitting data received via a network and / or via interconnect system 602 to one or more GPUs 608 (e.g., their memory).

[0065] I / O port 612 enables computing device 600 to be logically coupled to other devices, including I / O component 614, presentation component 618, and / or other components, some of which may be built into (e.g., integrated into) computing device 600. Illustrative I / O component 614 includes microphones, mice, keyboards, joysticks, game pads, game controllers, satellite dish antennas, browsers, printers, wireless devices, and so on. I / O component 614 can provide a Natural User Interface (NUI) for processing user-generated air gestures, voice, or other physiological input. In some instances, the input may be transmitted to appropriate network elements for further processing. The NUI can implement any combination of voice recognition, stylus recognition, facial recognition, biometric recognition, on-screen and adjacent-screen gesture recognition, air gestures, head and eye tracking, and touch recognition associated with the display of computing device 600 (described in more detail below). Computing device 600 may include depth cameras such as stereo camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations thereof for gesture detection and recognition. In addition, computing device 600 may include an accelerometer or gyroscope that enables motion detection (e.g., as part of an inertial measurement unit (IMU)). In some examples, the output of the accelerometer or gyroscope may be used by computing device 600 to render immersive augmented reality or virtual reality.

[0066] Power supply 616 may include a hard-wired power supply, a battery power supply, or a combination thereof. Power supply 616 may supply power to computing device 600 so that components of computing device 600 can operate.

[0067] The presentation component 618 may include a display (such as a monitor, touch screen, television screen, head-up display (HUD), other display types, or combinations thereof), speakers, and / or other presentation components. The presentation component 618 may receive data from other components (such as GPU 608, CPU 606, DPU, etc.) and output that data (e.g., as an image, video, sound, etc.).

[0068] Example Data Center

[0069] Figure 7 An example data center 700 is shown, which can be used in at least one embodiment of this disclosure. The data center 700 may include a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0070] like Figure 7As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (CPUs) or other processors (including DPUs, accelerators, field-programmable gate arrays (FPGAs), graphics processing units or graphics processing units (GPUs), etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (NW I / O) devices, network switches, virtual machines (VMs), power modules, and cooling modules, etc. In some embodiments, one or more nodes CR 716(1)-716(N) may correspond to servers having one or more of the aforementioned computing resources. In addition, in some embodiments, nodes CR716(1)-716(N) may include one or more virtual components, such as vGPU, vCPU, etc., and / or one or more of nodes CR716(1)-716(N) may correspond to virtual machines (VMs).

[0071] In at least one embodiment, the grouped computing resources 714 may include individual groups (not shown) of nodes CR716 housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. Individual groups of nodes CR716 within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several nodes CR716, including CPUs, GPUs, DPUs, and / or other processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. One or more racks may also include any number of power modules, cooling modules, and / or network switches in any combination.

[0072] Resource coordinator 712 can be configured or otherwise controlled to control one or more nodes CR716(1)-716(N) and / or groups of computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (SDI) management entity for data center 700. Resource coordinator 712 may include hardware, software, or some combination thereof.

[0073] In at least one embodiment, such as Figure 7As shown, framework layer 720 may include a job scheduler 744, a configuration manager 734, a resource manager 736, and a distributed file system 738. Framework layer 720 may include a framework of software 732 supporting software layer 730 and / or one or more applications 742 of application layer 740. Software 732 or application 742 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. Framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 738 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 744 may include a Spark driver for facilitating the scheduling of workloads supported by various layers of data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as software layer 730 and framework layer 720 including Spark and a distributed file system 738 for supporting large-scale data processing. The resource manager 736 is able to manage cluster or grouped computing resources mapped to or allocated to support the distributed file system 738 and the job scheduler 744. In at least one embodiment, the cluster or grouped computing resources may include grouped computing resources 714 at data center infrastructure layer 710. The resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0074] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the nodes CR716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus browsing software, database software, and streaming video content software.

[0075] In at least one embodiment, the application layer 740 may include one or more applications 742 that can be used by at least a portion of the nodes CR716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and / or other machine learning applications used in conjunction with one or more embodiments.

[0076] In at least one embodiment, any of the configuration manager 734, resource manager 736, and resource coordinator 712 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. Self-modification actions can alleviate the risk of data center operators of data center 700 making potentially poor configuration decisions and can prevent underutilization and / or skewed portions of the data center.

[0077] Data center 700 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, by using weight parameters calculated through one or more training techniques, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks, such as, but not limited to, those described herein, using the resources described above with respect to data center 700.

[0078] In at least one embodiment, the data center 700 may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, and / or other hardware (or corresponding virtual computing resources) to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0079] Example network environment

[0080] A network environment suitable for implementing embodiments of this disclosure may include one or more client devices, servers, network-attached storage (NAS), other backend devices, and / or other device types. Client devices, servers, and / or other device types (e.g., each device) may... Figure 6 The implementation is carried out on one or more instances of computing device 600—for example, each device may include similar components, features, and / or functions of computing device 600. Furthermore, in the case of implementing backend devices (e.g., servers, NAS, etc.), the backend devices may be included as part of data center 700, examples of which are described herein. Figure 7 To describe in more detail.

[0081] Components of a network environment can communicate with each other via a network, which can be wired, wireless, or both. A network can include multiple networks, or networks within multiple networks. For example, a network can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks (such as the Internet and / or the Public Switched Telephone Network (PSTN)), and / or one or more private networks. In cases where the network includes a wireless telecommunications network, components such as base stations, communication towers, or even access points (and other components) can provide wireless connectivity.

[0082] A compatible network environment may include one or more peer-to-peer network environments (in which case the server may not be included in the network environment) and one or more client-server network environments (in which case one or more servers may be included in the network environment). In a peer-to-peer network environment, the server functionality described herein can be implemented on any number of client devices.

[0083] In at least one embodiment, the network environment may include one or more cloud-based network environments, distributed computing environments, combinations thereof, etc. A cloud-based network environment may include a framework layer, a job scheduler, a resource manager, and a distributed file system implemented on one or more servers, which may include one or more core network servers and / or edge servers. The framework layer may include a framework for supporting software at the software layer and / or one or more applications at the application layer. The software or applications may respectively include network-based service software or applications. In embodiments, one or more client devices may use the network-based service software or applications (e.g., by accessing the service software and / or applications via one or more application programming interfaces (APIs)). The framework layer may be, but is not limited to, a type of free and open-source software network application framework, such as one that can use a distributed file system for large-scale data processing (e.g., "big data").

[0084] A cloud-based network environment can provide cloud computing and / or cloud storage for any combination of the computing and / or data storage functions (or one or more portions thereof) described herein. Any of these various functions can be distributed across multiple locations from a central or core server (e.g., distributed across one or more data centers at the state, region, country, global, etc.). If the connection to a user (e.g., a client device) is relatively close to an edge server, the core server can assign at least a portion of the functionality to the edge server. A cloud-based network environment can be private (e.g., limited to a single organization), public (e.g., available to many organizations), and / or a combination thereof (e.g., a hybrid cloud environment).

[0085] Client devices may include those described in this article. Figure 6 The example computing device 600 described includes at least some components, features, and functions. By way of example and not limitation, the client device may be a personal computer (PC), laptop computer, mobile device, smartphone, tablet computer, smartwatch, wearable computer, personal digital assistant (PDA), MP3 player, virtual reality headset, global positioning system (GPS) or device, video player, camera, surveillance equipment or system, vehicle, ship, aircraft, virtual machine, drone, robot, handheld communication device, hospital equipment, gaming equipment or system, entertainment system, in-vehicle computer system, embedded system controller, remote control, electrical appliance, consumer electronics device, workstation, edge device, any combination of these described devices, or any other suitable device.

[0086] This disclosure can be described in the general context of machine-usable instructions or computer code, including computer-executable instructions such as program modules, which are executed by a computer or other machine such as a personal digital assistant or other handheld device. Typically, a program module, including routines, programs, objects, components, data structures, etc., refers to code that performs a specific task or implements a specific abstract data type. This disclosure can be practiced in a wide variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. This disclosure can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked via a communication network.

[0087] As used herein, the phrase "and / or" relating to two or more elements should be interpreted as referring to only one element or a combination of elements. For example, "element A, element B, and / or element C" could include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. Furthermore, "at least one of element A or element B" could include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, "at least one of element A and element B" could include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

[0088] The subject matter of this disclosure is described in detail herein to satisfy legal requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have envisioned that the claimed subject matter may also be embodied in other ways to include steps different from or similar combinations of steps described herein in conjunction with other current or future techniques. Moreover, although the terms “step” and / or “block” may be used herein to imply different elements of the method employed, these terms should not be construed as implying any particular order among or between the various steps disclosed herein, unless the order of the steps is explicitly described.

Claims

1. A system comprising: One or more processing units; as well as One or more memory cells storing instructions, which, when executed by the one or more processing units, cause the one or more processing units to perform the following operations: In response to a request to move an entity into a Trusted Execution Environment (TEE) of a virtual machine (VM), a key corresponding to the VM is assigned to the entity; At least based on the request to translate the virtual address, the key is used to generate a signature for the physical address translated from the virtual address; In response to the request to translate the virtual address, data corresponding to the signature and the physical address is provided; and Access to the memory at the physical address is enabled at least based on the determination that the request for memory access includes the signature and the physical address.

2. The system of claim 1, wherein the data is provided in the address field of the converted response.

3. The system of claim 1, wherein determining the request for memory access includes the signature and the physical address, comprising: Using the key associated with the request, a reference signature is generated from the potential physical address included in the request for access to the memory; as well as The reference signature is determined to match the signature included in the request for access to the memory.

4. The system of claim 1, wherein the data represents at least an encrypted version of at least the combination of the signature and the physical address, and the determination is based at least on decrypting the encrypted version of at least the combination of the signature and the physical address.

5. The system of claim 1, wherein the request for access to the memory includes a direct memory access transfer request.

6. The system of claim 1, wherein determining the request for access to the memory includes the signature and the physical address, comprising: A reference signature is generated from the physical address using a key associated with at least the entity that provided the request for access to the memory; as well as The reference signature is determined to match the signature included in the request for access to the memory.

7. The system of claim 1, wherein determining the request for access to the memory includes the signature and the physical address, comprising: A reference signature is generated from the physical address using a key associated with at least a device function indicated by the request for access to the memory; as well as The reference signature is determined to match the signature included in the request for access to the memory.

8. The system of claim 1, wherein the generation, provisioning, and enabling are performed by a host of one or more virtual machines, and the physical address is assigned to one of the virtual machines.

9. The system of claim 1, wherein the generation, provisioning, and enabling are performed by a host of one or more processes, and the physical address is assigned to a process among the one or more processes.

10. A processor, comprising: One or more circuits are used for: In response to a request to move an entity into a Trusted Execution Environment (TEE) of a virtual machine (VM), a key corresponding to the VM is assigned to the entity. At least based on the request to convert the first address, the key is used to provide a cryptographically modified version of the second address converted from the first address. Receive the cryptographically modified version of the second address associated with the request for memory access transmission using the second address, and The memory access transfer is initiated based at least on the version of the password modification verified by the second address.

11. The processor of claim 10, wherein the first address is a virtual address and the second address is a physical address.

12. The processor of claim 10, wherein the cryptographically modified version of the second address includes a signature generated from the second address.

13. The processor of claim 10, wherein the cryptographically modified version of the second address includes at least an encrypted version of the second address.

14. The processor of claim 10, wherein the cryptographically modified version of receiving the second address is in the address field of the requested conversion.

15. The processor of claim 10, wherein verifying the cryptographically modified version of the second address comprises: A signature is generated based at least on a cryptographically modified version of the second address, decrypted using a key associated with at least the entity that provided the request for access to the memory. as well as Determine if the reference signature associated with the entity matches the signature.

16. The processor of claim 10, wherein the processor is comprised of at least one of the following: Control systems for autonomous or semi-autonomous machines; Sensing systems for autonomous or semi-autonomous machines; A system used to perform simulation operations; A system used to perform deep learning operations; Systems implemented using edge devices; Systems implemented using robots; A system that merges one or more virtual machines (VMs); A system that is at least partially implemented in a data center; or A system that utilizes cloud computing resources at least in part.

17. A method comprising: In response to a request to translate a first address, a cryptographically modified version of a second address translated from the first address is received, wherein the cryptographically modified version of the second address is generated using a key corresponding to a virtual machine (VM), and the key is assigned to the entity in response to a request to move the entity into a Trusted Execution Environment (TEE) of the VM; A request is provided for memory access to the second address, the request including a cryptographically modified version of the second address received in the response to the request; and At least based on the request for access to the memory, data corresponding to the memory access to the second address is received.

18. The method of claim 17, further comprising storing the cryptographically modified version of the second address received in the response in a translation cache, wherein the request for access to the memory is based at least on retrieving the cryptographically modified version of the second address from the translation cache.

19. The method of claim 17, wherein the cryptographically modified version of the second address corresponds to a combination of the second address and the signature of the second address.

20. The method of claim 17, wherein the request to convert the first address, the request to access the memory, and the data corresponding to the memory access are communicated via an interface of the host device.

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