Memory and method of operating memory

Abstract

The present disclosure provides a memory and an operating method of the memory, and relates to the technical field of memories. The memory comprises a memory cell, a charge pump, a first bit line segment, a second bit line segment, an isolation tube, a bit line pre-charging tube, and a controller. The first bit line segment is connected between the memory cell and the isolation tube, and the second bit line segment is connected between the isolation tube and the bit line pre-charging tube. During an erasing operation of the memory cell, the controller controls the charge pump to apply an erasing voltage to a substrate of the memory cell, controls the bit line pre-charging tube to be turned on for a specified time duration and then turned off, and controls the isolation tube to be turned on after the bit line pre-charging tube is turned off. Through the technical solution of the present disclosure, the problem of overvoltage of the bit line pre-charging tube can be solved, so as to reduce the probability of damage of the bit line pre-charging tube due to overvoltage and prolong the service life of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more particularly to a memory and a method of operating the memory. Background Technology

[0002] NAND flash is a type of non-volatile memory that stores data through memory cells.

[0003] When erasing a Nand flash memory, the charge pump unit applies a voltage to the substrate of the memory cell, causing the voltage of the bit line connected to the memory cell to rise to near the substrate voltage, which in turn leads to overvoltage of the low-voltage transistor that is in the same path as the bit line.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a memory and a method of operating the memory, which at least to some extent overcomes the problem of overvoltage of low-voltage transistors on the same path as the bit line caused by the increase in bit line voltage in related technologies.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a memory is provided, comprising: a memory cell; a charge pump; a first bit segment; a second bit segment; an isolation transistor; a bit line precharge transistor; and a controller, wherein the first bit segment is connected between the memory cell and the isolation transistor, the second bit segment is connected between the isolation transistor and the bit line precharge transistor, and during an erase operation, the controller controls the charge pump to apply an erase voltage to the substrate of the memory cell, the controller controls the bit line precharge transistor to be turned on for a specified duration and then turned off, and controls the isolation transistor to be turned on with a delay after the bit line precharge transistor is turned off.

[0008] In one embodiment of this disclosure, the controller is further configured to: after controlling the bit line precharge transistor to turn off for a specified duration, when the voltage of the second bit line segment is coupled to a voltage greater than a specified voltage by the voltage of the first bit line segment, control the isolation transistor to turn on, wherein the specified voltage is determined based on the difference between the gate voltage of the isolation transistor and the threshold voltage of the isolation transistor.

[0009] In one embodiment of this disclosure, the drain of the isolation transistor is connected to the source of the bit line precharge transistor via the second bit line segment, the source of the isolation transistor is connected to the first bit line segment, the gate of the bit line precharge transistor receives a first enable signal, and the gate of the isolation transistor receives a second enable signal.

[0010] In one embodiment of this disclosure, the erase voltage is first increased to an intermediate value, and then increased to a target value. During the process of the erase voltage increasing to the intermediate value, the bit line precharge tube is turned on.

[0011] In one embodiment of this disclosure, the device further includes: a capacitor, the first end of which is connected to the bit line precharge transistor and is grounded; a first switch transistor disposed between a power supply terminal and the first end of the capacitor; a second switch transistor, the first end of which is grounded and a control terminal connected to the first end of the capacitor; and a latch module, the input terminal of which is connected to the second end of the second switch transistor.

[0012] In one embodiment of this disclosure, the memory is flash memory.

[0013] According to another aspect of this disclosure, a method of operating a memory is provided, comprising: applying an erase voltage to a substrate of a memory cell; and during the application of the erase voltage to the substrate of the memory cell, controlling the bit line precharge transistor to be turned on for a specified duration and then turned off, and controlling an isolation transistor to be turned on with a delay after the bit line precharge transistor is turned off.

[0014] In one embodiment of this disclosure, the control isolation tube is delayed in turning on after the bit line precharge tube is turned off, specifically including: after the bit line precharge tube is turned off for a specified period of time, when the voltage of the second bit line segment is greater than a specified voltage, determining the delayed turn-on time of the isolation tube.

[0015] In one embodiment of this disclosure, the method further includes determining the specified voltage based on the difference between the gate voltage of the isolation transistor and the threshold voltage of the isolation transistor.

[0016] In one embodiment of this disclosure, the erase voltage is first increased to an intermediate value, and then increased to a target value. During the process of the erase voltage increasing to the intermediate value, the bit line precharge tube is turned on.

[0017] The memory solution provided in the embodiments of this disclosure does not turn on the isolation transistor immediately after the bit line precharge transistor is turned off. Compared with the solution where the bit line precharge transistor is turned off and the isolation transistor is turned on simultaneously, this can reduce the voltage rise of the isolation transistor during the delayed turn-on period. This voltage rise is the voltage rise caused by the first bit segment directly charging the second bit segment. This eliminates the voltage rise of the second bit segment after the bit line precharge transistor is turned off, thereby helping to solve the bit line precharge transistor overvoltage problem, reducing the probability of overvoltage damage to the bit line precharge transistor, and extending the service life of the memory.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 A schematic block diagram of the memory in an embodiment of this disclosure is shown; Figure 2 A schematic diagram of the structure of the memory cell array in an embodiment of this disclosure is shown; Figure 3 A cross-sectional view of a memory along the bit line direction is shown in an embodiment of the present disclosure; Figure 4 This diagram illustrates the structure of a sensitive amplifier according to an embodiment of the present disclosure; Figure 5 This diagram shows an equivalent schematic of the P-trap positioning line during the erasure operation in an embodiment of this disclosure. Figure 6 A schematic diagram showing multiple voltage signals in a memory in the related art is shown; Figure 7 A schematic diagram of multiple voltage signals in the memory is shown in an embodiment of this disclosure; Figure 8 This diagram illustrates the use of memory to perform a flash memory recovery operation in an embodiment of this disclosure. Figure 9 A flowchart illustrating an operation method of a memory according to an embodiment of this disclosure is shown.

[0021] in, Figures 1 to 8 The annotations in the accompanying drawings are explained as follows: 10 memory, 100 controller, 200 memory array, 300 address register, 400 row decoder, 450 readout circuit, 500 column decoder, 600 charge pump, 700 page buffer, 202 memory cells, BL1 first bit segment, BL2 second bit segment, MN1 first switch, MN2 bit precharge transistor, HV isolation transistor, MN3 second switch, MN4 third switch, MN5 fourth switch, D0 diode, C0 first parasitic capacitance, C1 second parasitic capacitance, C2 capacitor, I1 first inverter, I2 second inverter. Detailed Implementation

[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0023] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0024] like Figure 1 As shown, memory 10 is electrically connected to an electronic device. Memory 10 can be a built-in or external storage device of the electronic device. Memory 10 can be non-volatile memory. Non-volatile memory can retain stored data even when power is off, and includes, for example, NAND flash memory, NOR flash memory, electrically erasable programmable ROM (EEPROM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0025] Specifically, the memory 10 includes a controller 100, a memory array 200, an address register 300, a row decoder 400, a read circuit 450, a column decoder 500, a charge pump 600, and a page cache 700.

[0026] The following description uses NAND flash memory as an example.

[0027] Storage array 200 comprises multiple blocks. Figure 2This is a schematic diagram of a block of a NAND flash memory storage array.

[0028] like Figure 2 As shown, a block of memory array 200 includes multiple memory cells 202, such as 64 rows and n columns of memory cells. A memory cell is, for example, a transistor with a floating gate. The transistor also includes a substrate, source, drain, and control gate. The transistor has a programmed state and an erased state (unprogrammed state). The floating gate of a transistor in the programmed state has more electrons than that of a transistor in the erased state. The threshold voltage of a transistor in the programmed state is higher than that of a transistor in the erased state. A transistor in the programmed state stores "0", and a transistor in the erased state stores "1". The control gate of a memory cell is connected to the corresponding word line (WL). Specifically, each row of memory cells is connected to the same word line, forming a page. A page is the smallest read / write unit on NAND Flash, and a block is the smallest erased unit. Each block consists of multiple pages.

[0029] Specifically, memory cells 202 in the same column of the memory array 200 are connected in series. Specifically, memory cells in the same column form a memory cell string through the interconnection of their drain and source terminals. The two ends of the memory cell string are a string selection transistor (SST) and a ground selection transistor (GST), respectively. The memory cell string is connected to the bit line BL via the string selection transistor SST and to the common source line CSL via the ground selection transistor GST. The gate of the string selection transistor SST is connected to the string selection line SSL, and the gate of the ground selection transistor GST is connected to the ground selection line GSL. A row decoder 400 is used to address word lines based on address information. A column decoder 500 is used to address bit lines based on address information. The operations of the memory 10 include read operations, write operations (also called programming operations), erase operations, and verification operations. A charge pump 600 is used to generate the operating voltage required for various operations, such as the erase voltage in the erase operation. A read circuit 450 is used to perform read operations and verification operations. The readout circuit 450 includes multiple sense amplifiers SA, such as Figure 2 As shown, each sensitive amplifier SA is connected to the corresponding bit line BL.

[0030] Figure 4The circuit structure of an exemplary sensitive amplifier SA and its corresponding page buffer is shown. The page buffer is, for example, a static random access memory (SRAM) comprising multiple latch cells, each latch cell connected to a corresponding sensitive amplifier SA. Bit line BL is connected to the sensitive amplifier SA via an isolation transistor HV. The isolation transistor HV is a high-voltage transistor. The sensitive amplifier SA includes a first switching transistor MN1, a bit line precharge transistor MN2, a capacitor C2, and a second switching transistor MN3. The first switching transistor MN1, bit line precharge transistor MN2, and second switching transistor MN3 are all low-voltage transistors. The first switching transistor MN1 is positioned between the power supply terminal and the first terminal of capacitor C2. The first terminal of the bit line precharge transistor MN2 is connected to the isolation transistor HV, and the second terminal is connected to the first terminal of capacitor C2. Here, the bit line BL between the isolation transistor HV and the memory cell string is called the first bit segment BL1, and the bit line BL between the isolation transistor HV and the sensitive amplifier SA is called the second bit segment BL2. The second switching transistor MN3 is positioned between the ground terminal and the input terminal of the latch cell, and the gate of the second switching transistor MN3 is connected to the first terminal of capacitor C2.

[0031] Figure 8 The circuit diagram of the latch unit is shown. The latch unit is, for example, a 6-transistor SRAM cell, including cross-connected inverters I1 and I2. The input of inverter I1 is connected to the first terminal of the second switch MN3 via a third switch MN4, and the output of inverter I1 is connected to the first terminal of the second switch MN3 via a fourth switch MN5. The outputs of inverters I1 and I2 are a pair of complementary outputs, OUT and OUT_N. The gates of the third switch MN4 and the fourth switch MN5 receive the SET and RESET signals, respectively. The isolation transistor HV is a high-voltage device used to protect the low-voltage components in the erase operation's sensitive amplifier SA and page buffer. During the read operation, an appropriate voltage SEL is applied to turn on the isolation transistor HV.

[0032] Figure 3 This diagram shows a cross-sectional view of a memory 10 along the bitline direction according to an embodiment of the present disclosure. The memory 10 includes a memory device region 302 and a peripheral circuit region 304. A memory array 200 is formed in the memory device region 302. A controller 100, an address register 300, a row decoder 400, a read circuit 450, a column decoder 500, a charge pump 600, and a page cache 700 are formed in the peripheral circuit region 304. Figure 3As shown, memory cells are formed in P-wells; specifically, blocks of memory array 200 are formed in a common P-well. Memory cell 202 has a floating gate FG and a control gate CG. For NAND flash memory, the drain of the string select transistor SST is connected to the bit line BL via a bit line contact, specifically to the first bit segment BL1. The P-well and the drain of the string select transistor SST form a parasitic diode D0. During an erase operation, an erase voltage (e.g., 15 to 20 V) is applied to the P-well, turning on the parasitic diode D0, causing the bit line BL to be charged to a higher voltage. The memory cell, isolation transistor HV, and readout circuitry 450 are formed on the same layer, while the first bit segment BL1 is formed on a different layer, extending from the memory device region 302 to the peripheral circuit region 304. A first parasitic capacitance C0 exists between the first bit segment BL1 and the P-well. A second bit segment BL2 is formed in the peripheral circuit region 304. The second line segment BL2 and the first line segment BL1 are located on different layers and overlap with the first line segment BL1. Therefore, there is a second parasitic capacitance C1 between the second line segment BL2 and the first line segment BL1.

[0033] Figure 5 This diagram illustrates the P-well to-line during the erase operation in an embodiment of this disclosure. During the erase operation, an erase voltage Vtwp is applied to the P-well, and a PN junction exists between the P-well and the drain, equivalent to... Figure 3 and Figure 5 In the diode D0, the erase voltage causes the PN junction to be forward biased, so the first line segment BL1 is also at a high voltage. For example... Figure 5 As shown, there is a first parasitic capacitance C0 between the substrate and the first bit segment BL1. Furthermore, since the first bit segment BL1 and the second bit segment BL2 partially overlap, there is a second parasitic capacitance C1 between them. Therefore, the voltage of the second bit segment... It will also be coupled to a higher voltage value by the first bit segment BL1, while the bit line precharge transistor MN2 between the first bit segment BL1 and the second bit segment BL2 is a low-voltage transistor, therefore the voltage of the higher second bit segment... This poses a risk of overvoltage to the bit line precharge tube.

[0034] like Figure 4 As shown, the first bit segment BL1 is connected between the memory cell (specifically, the string selection transistor SST of the memory cell string) and the isolation transistor HV, and the second bit segment BL2 is connected between the isolation transistor HV and the bit line precharge transistor MN2. The bit line precharge transistor MN2 is used for pre-charging during the read operation.

[0035] During the charging phase of the read operation, a voltage VDD+ is applied to the gate of the first switching transistor MN1. , The threshold voltage of the first switching transistor MN1 is used to apply a voltage to the gate of the bit line precharge transistor MN2. And the isolation tube HV is turned on, at which point the second segment BL2 is charged to - .

[0036] When the bit line precharge transistor MN2 is turned off, the switching transistor of the memory cell string is turned on, and the discharge phase begins.

[0037] After discharge, bit line precharge tube MN2 applies If at this time < - The bit line precharge tube MN2 is turned on. = This indicates that storage unit 202 < This indicates that the memory cell is in a programming state; otherwise, the bit line precharge transistor MN2 is not conducting. =VDD indicates that the memory cell is in the erase state. Before the discharge phase, by applying a RESET signal to the gate of the fourth transistor MN5 in the latch cell, the output terminal OUT is set to low and the output terminal OUT_N is set to high. After the discharge phase, a SET signal is applied to the gate of the third transistor MN4, if... =VDD, the second switch MN3 is turned on, the output terminal OUT_N is set to low level, and the output terminal OUT is set to high level; if = The second switch MN3 is not turned on, the output terminal OUT remains low, and the output terminal OUT_N remains high. Thus, a complete read operation is completed.

[0038] like Figure 6 As shown, in the erasure operation of related technologies, a high erasure voltage, such as 20V, is applied to the P-well by a charge pump. The voltage rises to the intermediate value in the first time period T1, and to the target voltage value in the second time period T2. This is due to the presence of a parasitic diode D0, i.e., the voltage of the first segment. With the erase voltage of the P-well The voltage changes accordingly. During the first time period T1, the controller 100 outputs a high-level first enable signal BL_PREC, a low-level second enable signal SEL, an off-state isolation transistor HV, and an on-state bit-line pre-charge transistor MN2 and a high-level first switch transistor MN1. The voltage of the second bit segment... Because it is coupled to the first line segment BL1, it becomes high, but it will not exceed VDD. At this time, the second parasitic capacitance C1 is charged to VDD.

[0039] At the end of the first time period T1, which is the start of the second time period T2, the controller 100 controls the first enable signal BL_PREC to change from high to low, and the second enable signal SEL to change from low to high. The isolation transistor HV is in the on state, while the bit line precharge transistor MN2 and the first switch transistor MN1 are in the off state. In the second time period T2, the erase voltage... As the voltage gradually increases to the target value, the voltage of the first segment BL1 also gradually increases. The first segment BL1 not only... Figure 4 The isolation transistor HV in the middle charges the second bit segment BL2. When the voltage of the second bit segment... Reaching the second voltage value SEL- When the charging process ends, as the voltage of the first segment BL1 increases, the voltage of the second segment BL2 will also gradually increase. The bit line pre-charge transistor MN2 experiences overvoltage under the combined effects of charging and coupling from the first segment BL1. That is, when the second enable signal SEL is high, due to the conduction of the isolation transistor HV, the second segment BL2 will be charged by the first segment BL1 to SEL-. This causes the excess voltage in the second bit segment BL2 of the bit line precharge transistor MN2 to be precharged by the first bit segment BL1. Since the bit line precharge transistor MN2 is a low-voltage transistor, this results in a higher probability of overvoltage in the bit line precharge transistor MN2.

[0040] To reduce the probability of overvoltage in the bit line precharge transistor MN2, during the erase operation of the memory cell, the controller 100 controls the charge pump to apply an erase voltage to the substrate of the memory cell. The controller 100 controls the bit line precharge transistor MN2 to be turned on for a specified duration and then turned off, and controls the isolation transistor HV to be turned on with a delay after the bit line precharge transistor MN2 is turned off, i.e., relative to... Figure 6 In the proposed scheme, controller 100 controls the isolation tube HV to turn on with a delay in order to reduce the boost voltage of the second bit segment BL2.

[0041] In this embodiment, during the first time period of charging the substrate of the memory cell based on the erase operation, the bit line precharge transistor MN2 is in the on state, the isolation transistor HV is in the off state, and the erase voltage... The voltage gradually increases to the intermediate value, and the voltage of the first segment BL1... Follow The voltage of the second segment BL2 increases due to the coupling effect of the second parasitic capacitance C1. Follow The voltage increases with the increase of [the voltage]. Afterwards, the erase voltage [is increased]. Gradually increase the voltage from the intermediate value to the target voltage value. After the bit line precharge transistor MN2 is turned off, do not turn on the isolation transistor HV first. Instead, increase the voltage of the second bit line segment BL2. By continuing to boost the voltage under coupling, compared to the scheme where the bit line precharge transistor MN2 is disconnected and the isolation transistor HV is simultaneously turned on, the voltage of the second bit line segment BL2 caused by the turned-on isolation transistor HV can be reduced. The boost voltage is the voltage increase caused by the first bit segment BL1 directly charging the second bit segment BL2, which helps to solve the overvoltage problem of the bit line precharge tube MN2, thereby reducing the probability of overvoltage damage to the bit line precharge tube MN2 and extending the service life of the memory.

[0042] In one embodiment of this disclosure, the controller 100 is further configured to: after the control bit line precharge transistor MN2 has been turned off for a specified period of time, when the voltage of the second bit line segment... Voltage of the first line segment When coupled to a voltage greater than a specified voltage, the isolation transistor HV is turned on. The specified voltage is determined based on the difference between the gate voltage and the threshold voltage of the isolation transistor HV. Specifically, the controller 100 controls the isolation transistor HV to remain off for a specified time after the bit line precharge transistor MN2 is turned off, and then turns it on after the specified time. During this specified time, the voltage of the second bit line segment... Voltage of the first line segment Coupled to a voltage greater than the specified voltage.

[0043] When the isolation transistor HV is turned on, its gate voltage is the voltage of the first segment. The threshold voltage of the isolation transistor HV refers to the gate-source voltage when strong inversion occurs at the source end of the channel region. The difference between the gate voltage and the threshold voltage of the isolation transistor HV is recorded as the specified voltage because it represents the voltage of the second segment. The charging process ends when the voltage reaches the difference between the gate voltage and the threshold voltage of the isolation transistor HV. Therefore, the voltage in the second bit segment... When the voltage reaches a value greater than the specified voltage, the isolation transistor HV is then turned on, thereby reducing the voltage of the second bit segment. The boost voltage is increased to reduce the probability of overvoltage in the bit precharge tube MN2.

[0044] Specifically, in combination Figure 4 and Figure 7 As shown, during the first time period T1, the voltage applied to the substrate of the memory cell is... When the voltage rises to the intermediate value, the bit line precharge transistor MN2 and the first switching transistor MN1 are in the conducting state, ensuring that even if the voltage of the second bit line segment is increased... Even when coupled higher, the maximum value will not exceed VDD.

[0045] During the second time period T2, due to As the voltage continues to increase, both the bit line precharge transistor MN2 and the isolation transistor HV are disconnected, and the voltage of the second bit line segment... It only continues to increase under the effect of coupling, thereby eliminating the voltage increment caused by the first segment BL1 directly charging the second segment BL2 when the isolation tube HV is turned on.

[0046] In the third time period T3, As the voltage continues to increase to the target value, the isolation transistor HV turns on, at which point the voltage of the second segment... This includes the voltage portion transmitted through the conducting isolation tube HV and the coupled voltage portion.

[0047] In this embodiment, when the voltage of the second bit segment Voltage of the first line segment When coupled to a voltage greater than a specified voltage, the control isolation transistor HV is turned on, allowing the voltage of the second bit segment to be adjusted. Voltage of the first line segment The coupling reaches a point equal to or greater than the specified voltage, at which point the isolation transistor HV is turned on. Alternatively, the isolation transistor HV can be turned on for a limited time period. The start time of the limited time period is when the voltage is greater than or equal to the specified voltage, and the end time of the limited time period is after the start time. The voltage of the second bit segment is reduced at any point during the process of increasing the first value to the erase voltage. The amount of pressure increase.

[0048] In one embodiment of this disclosure, the drain of the isolation transistor HV is connected to the source of the bit line precharge transistor MN2 via a second bit line segment, the source of the isolation transistor HV is connected to the first bit line segment, the gate of the bit line precharge transistor MN2 receives a first enable signal BL_PREC, and the gate of the isolation transistor HV receives a second enable signal SEL.

[0049] In this embodiment, one end of the first bit segment is connected to the drain of the memory cell string (the string selection transistor SST), and the other end of the first bit segment is connected to the source of the isolation transistor HV. One end of the second bit segment is connected to the drain of the isolation transistor HV, and the other end of the second bit segment is connected to the source of the bit line precharge transistor MN2. The controller inputs a first enable signal BL_PREC to the gate of the bit line precharge transistor MN2 to control the switching on and off of the isolation transistor HV, and inputs a second enable signal SEL to the gate of the isolation transistor HV to control the switching on and off of the bit line precharge transistor MN2.

[0050] like Figure 9 As shown, a method for operating a memory according to an embodiment of the present disclosure includes: Step S902: Apply an erase voltage to the substrate of the memory cell.

[0051] During the substrate charging process of the memory cell based on the erase operation, the bit line precharge transistor is in the on state, the isolation transistor is in the off state, and the substrate voltage... After charging the first segment for a certain period of time, based on the coupling effect of the first parasitic capacitance C0, it enables... Follow The increase is due to the coupling effect of the second parasitic capacitance C1, causing... Follow It increases as it increases.

[0052] In step S904, during the process of applying an erase voltage to the substrate of the memory cell, the bit line precharge transistor is controlled to be turned on for a specified time and then turned off, and the isolation transistor is controlled to be turned on with a delay after the bit line precharge transistor is turned off.

[0053] In this embodiment, after the bit line precharge tube is disconnected, the isolation tube is not turned on immediately; instead, the isolation tube is... By continuing to boost voltage under coupling, compared with the scheme of disconnecting the bit line precharge transistor and simultaneously turning on the isolation transistor, the voltage boost during the delayed conduction period of the isolation transistor can be reduced. This voltage boost is the voltage boost caused by the first bit segment directly charging the second bit segment. This eliminates the voltage boost generated by the second bit segment after the bit line precharge transistor is disconnected, which helps to solve the bit line precharge transistor overvoltage problem, reduce the probability of overvoltage damage to the bit line precharge transistor, and extend the service life of the memory.

[0054] In one embodiment of this disclosure, the control isolation tube is delayed in conducting after the bit line precharge tube is turned off, specifically including: after the control bit line precharge tube is turned off for a specified period of time, when the voltage of the second bit line segment is greater than a specified voltage, determining the delayed conduction time of the isolation tube.

[0055] In one embodiment of this disclosure, the method further includes determining a specified voltage based on the difference between the gate voltage of the isolation transistor and the threshold voltage of the isolation transistor.

[0056] In this embodiment, when the voltage of the second bit segment is coupled to a voltage greater than a specified voltage by the voltage of the first bit segment, the isolation transistor is controlled to turn on. The isolation transistor can be controlled to turn on at the moment when the voltage of the second bit segment is coupled to a voltage equal to the specified voltage by the voltage of the first bit segment, or it can be controlled to turn on within a limited time period. The start time of the limited time period is the moment when the voltage is greater than or equal to the specified voltage, and the end time of the limited time period is any moment after the start time during the process of the substrate voltage increasing from the first value to the erase voltage, so as to reduce the voltage boost of the second bit segment.

[0057] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0058] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as “circuit,” “module,” or “system.”

[0059] The memory and its operation method disclosed herein, by not turning on the isolation transistor immediately after the bit line precharge transistor is turned off, but instead... By continuing to boost voltage under coupling, compared with the scheme of disconnecting the bit line precharge transistor and simultaneously turning on the isolation transistor, the voltage boost during the delayed conduction period of the isolation transistor can be reduced. This voltage boost is the voltage boost caused by the first bit segment directly charging the second bit segment. This eliminates the voltage boost generated by the second bit segment after the bit line precharge transistor is disconnected, which helps to solve the bit line precharge transistor overvoltage problem, reduce the probability of overvoltage damage to the bit line precharge transistor, and extend the service life of the memory.

[0060] In this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0061] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0062] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0063] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0064] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A memory, characterized in that, include: Storage unit; Charge pump; The first line segment; The second line segment; Isolation tube; Sensitive amplifier, including bit line precharge tube; as well as Controller The first bit segment connects the memory cell and the isolation tube, and the second bit segment connects the isolation tube and the bit line precharge tube. During the erase operation, the controller controls the charge pump to apply an erase voltage to the substrate of the memory cell, the controller controls the bit line precharge tube to be turned on for a specified time and then turned off, and controls the isolation tube to be turned on with a delay after the bit line precharge tube is turned off; The controller is further configured to: after controlling the bit line precharge transistor to turn off for a specified period of time, when the voltage of the second bit line segment is coupled to a voltage greater than a specified voltage by the voltage of the first bit line segment, control the isolation transistor to turn on. The specified voltage is determined based on the difference between the gate voltage of the isolation transistor and the threshold voltage of the isolation transistor.

2. The memory according to claim 1, characterized in that, The drain of the isolation tube is connected to the source of the bit line precharge tube via the second bit line segment, and the source of the isolation tube is connected to the first bit line segment. The gate of the bit line precharge transistor receives a first enable signal, and the gate of the isolation transistor receives a second enable signal.

3. The memory according to any one of claims 1 or 2, characterized in that, Also includes: A capacitor, wherein the first terminal of the capacitor is connected to the bit line precharge tube, and the second terminal of the capacitor is grounded; The first switching transistor is disposed between the power supply terminal and the first terminal of the capacitor. The second switching transistor has its first terminal grounded and its control terminal connected to the first terminal of the capacitor. as well as A latch module, wherein the input terminal of the latch module is connected to the second terminal of the second switching transistor.

4. The memory according to claim 1, characterized in that, The memory is flash memory.

5. The memory according to claim 1, characterized in that, The erase voltage first rises to an intermediate value, and then rises to the target value. During the process of the erase voltage rising to the intermediate value, the bit line precharge tube is turned on.

6. A method for operating a memory, characterized in that, The memory is the memory according to any one of claims 1 to 5, comprising: An erase voltage is applied to the substrate of the memory cell; and During the process of applying an erase voltage to the substrate of the memory cell, the bit line precharge transistor in the control sensitive amplifier is turned on for a specified time and then turned off, and the isolation transistor is turned on with a delay after the bit line precharge transistor is turned off.

7. The method of operating the memory according to claim 6, characterized in that, The control isolation transistor is delayed in conducting after the bit line precharge transistor is turned off, specifically including: After the bit line precharge tube is turned off for a specified period of time, the moment when the voltage of the second bit line segment is greater than the specified voltage is determined as the delayed turn-on time of the isolation tube.

8. The operating method according to claim 7, characterized in that, Also includes: The specified voltage is determined based on the difference between the gate voltage of the isolation transistor and the threshold voltage of the isolation transistor.

9. The operating method according to claim 6, characterized in that, The erase voltage first rises to an intermediate value, and then rises to the target value. During the process of the erase voltage rising to the intermediate value, the bit line precharge tube is turned on.

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