Semiconductor memory device

Abstract

The invention provides a semiconductor memory device that inhibits an increase in read operation time. A nonvolatile memory (2) of the invention includes a memory cell array (21), and a sequence generator (25) capable of performing a first write operation and a second write operation after the first write operation, and in the second write operation, performing a program operation of writing n-bit data and a test operation of testing the n-bit data written by the program operation. The sequence generator (25) reads data of two memory cells MT2 and MT3 adjacent to a memory cell MT1, sets a plurality of test voltage levels used in the test operation of the memory cell MT1 in the second write operation, based on the read data and data written in the memory cell MT1 by the first write operation.

Description

[0001] Related applications

[0002] The present application claims priority based on Japanese Patent Application No. 2021-145658 filed on September 7, 2021. The present application includes the entire content of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] There is a method for writing multi-value data by performing multiple write operations (write sequences) in a semiconductor memory device. In this method, the time required for writing multi-value data may be prolonged. In addition, the time required for reading data from the semiconductor memory device may be prolonged due to the writing of multi-value data. Summary of the Invention

[0005] An object of the embodiments is to provide a semiconductor memory device that suppresses prolongation of the time for a read operation or the time for a write operation.

[0006] A semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells each capable of storing n-bit data where n is an integer of 2 or more; and a control circuit capable of executing a first write operation of writing p-bit data where p<n out of n bits into each memory cell, and a second write operation of writing the n-bit data into each of the memory cells after the first write operation, wherein in the second write operation, the control circuit executes a program operation of writing the n-bit data, and a verify operation of verifying the n-bit data written by the program operation; and the control circuit reads at least one first data from at least one second memory cell adjacent to a first memory cell, and sets a plurality of verify voltage levels for the verify operation of the first memory cell used in the second write operation based on the read first data and second data written into the first memory cell through the first write operation. Brief Description of the Drawings

[0007] Figure 1 is a block diagram showing a configuration example of the memory system according to the first embodiment.

[0008] Figure 2 is a block diagram showing a configuration example of the non-volatile memory according to the first embodiment.

[0009] Figure 3 is a diagram showing a configuration example of a block of a three-dimensionally structured memory cell array according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view of a portion of a 3D constructed NAND (Not-AND) memory cell array according to the first embodiment.

[0011] Figure 5 This is a diagram showing the threshold voltage distribution of the memory cell in the first embodiment.

[0012] Figure 6 This is a circuit diagram illustrating an example of the specific configuration of one sensing amplifier unit of the sensing amplifier in the first embodiment.

[0013] Figure 7 This is a diagram showing the voltage changes of each wire during the write operation in the first embodiment.

[0014] Figure 8 This is a graph showing the voltage changes of each wiring during the inspection operation in the first embodiment.

[0015] Figure 9 This is a graph showing the distribution of threshold voltages in the two-stage writing method of the first embodiment.

[0016] Figure 10 This is a diagram showing the sequence of write operations in the two-stage write method of the first embodiment.

[0017] Figure 11 This is a diagram illustrating an example of the threshold voltage distribution of two adjacent memory cells on two adjacent word lines in the first embodiment.

[0018] Figure 12 This is a diagram illustrating an example of the threshold voltage distribution of two adjacent memory cells on two adjacent word lines in the first embodiment.

[0019] Figure 13 This is a graph showing the change in threshold voltage distribution caused by data storage degradation in the first embodiment.

[0020] Figure 14 This is a diagram showing the instruction sequence of the MLC write operation (first write operation) in the first embodiment.

[0021] Figure 15 This is a diagram showing the instruction sequence of the QLC write operation (second write operation) in the first embodiment.

[0022] Figure 16 This is a diagram showing the instruction sequence of the QLC write operation (second write operation) in the first embodiment, and the storage status of the data in the seven latch circuits that accompany the execution of the instruction sequence.

[0023] Figure 17This is a diagram showing the data stored in a latch circuit according to the first embodiment.

[0024] Figure 18 This is a graph used to illustrate the relationship between the threshold voltage distribution of the test operation in the first embodiment and the data of the six latch circuits.

[0025] Figure 19 This is a graph showing the change in the test voltage level during the test operation in state S15 of the first embodiment.

[0026] Figure 20 This is a diagram illustrating an example of data in the case where a latch circuit is used in the first embodiment.

[0027] Figure 21 This is a diagram showing the changes in data from the five latch circuits ADL to EDL in the internal data readout process of the first embodiment using one latch circuit.

[0028] Figure 22 This is a graph used to illustrate the changes in the threshold voltage distribution of the four levels caused by data storage degradation after the completion of the MLC write operation (first write operation) in the second embodiment.

[0029] Figure 23 This is a graph showing the change in the readout voltage of the select word line in the Vth tracking read of the second embodiment.

[0030] Figure 24 This is a diagram illustrating the valley location exploration process of Vth tracking read in the second embodiment.

[0031] Figure 25 This is a diagram showing the relationship between the write operation cycle and the verification operation in the second embodiment.

[0032] Figure 26 This is a graph showing the change in the threshold voltage distribution for each cycle in the second embodiment.

[0033] Figure 27 This is a graph showing the change in readout voltage during the test operation of loops 15 and 16 in the second embodiment.

[0034] Figure 28 This is a graph showing the change in the threshold voltage distribution for each cycle corresponding to the data storage degradation in the second embodiment.

[0035] Figure 29 This is a graph showing the change in the threshold voltage distribution for each cycle of the pre-assumed data storage degradation and the condition that the test operation starts cycling, as described in the second embodiment.

[0036] Figure 30This is a diagram showing the instruction sequence of the QLC write operation (second write operation) in the second embodiment.

[0037] Figure 31 This is a diagram showing the relationship between the loop that performs the write operation and the state of the object performing the check operation in the second embodiment.

[0038] Figure 32 This is a flowchart of the QLC write operation (second write operation) in the second embodiment.

[0039] Figure 33 This is a graph showing the relationship between the cycle and the inspection operation, which is the result of adjusting the inspection operation of each state based on the deviation of the readout voltage of each level read using Vth tracking in the second embodiment. Detailed Implementation

[0040] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0041] (First Embodiment)

[0042] (The structure of a memory system)

[0043] Figure 1 This is a block diagram illustrating an example configuration of a memory system according to an embodiment of the present invention. The memory system of this embodiment includes a memory controller 1 and a non-volatile memory 2, which is a semiconductor memory device. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a mobile terminal.

[0044] Non-volatile memory 2 is a memory that stores data non-volatilely, and includes, for example, NAND memory (NAND flash memory). Non-volatile memory 2 is, for example, a NAND memory having a memory cell (hereinafter also referred to as a memory cell) capable of storing 4 bits, that is, a 4-bit / cell (QLC: Quad Level Cell) NAND memory.

[0045] Memory controller 1 controls the writing of data to non-volatile memory 2 according to write requests from the host. Additionally, memory controller 1 controls the reading of data from non-volatile memory 2 according to read requests from the host. Between memory controller 1 and non-volatile memory 2, the following signals are used: transceiver enable signal / CE, ready / busy signal / RB, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protection signal / WP, data strobe signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0046] For example, the non-volatile memory 2 and the memory controller 1 are formed as semiconductor chips (hereinafter also simply referred to as "chips").

[0047] The Chip Enable signal / CE is used to enable non-volatile memory 2. The Ready / Busy signal / RB indicates whether non-volatile memory 2 is in a ready state (accepting commands from external sources) or a busy state (not accepting commands from external sources). The Instruction Latch Enable signal CLE indicates that signals DQ<7:0> represent instructions. The Address Latch Enable signal ALE indicates that signals DQ<7:0> represent addresses. The Write Enable signal / WE is used to fetch received signals into non-volatile memory 2, and is asserted by memory controller 1 each time it receives instructions, addresses, and data. Non-volatile memory 2 is indicated by fetching signals DQ<7:0> during the period when signal / WE is at a "L" (Low) level.

[0048] The read enable signals RE and / RE are used by memory controller 1 to read data from non-volatile memory 2. For example, they are used to control the operation of non-volatile memory 2 when output signals DQ<7:0> are displayed. The write protect signal / WP is used to instruct non-volatile memory 2 to disable data writing and erasure. Signals DQ<7:0> are the entities of data transmitted and received between non-volatile memory 2 and memory controller 1, including instructions, addresses, and data. The data strobe signals DQS and / DQS are used to control the input and output timing of signals DQ<7:0>.

[0049] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Checking and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are connected to each other via an internal bus 16.

[0050] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2 and responses from the processor 12 to the host.

[0051] The memory interface 15 controls, based on instructions from the processor 12, the processes of writing user data to the non-volatile memory 2 and reading it from the non-volatile memory 2.

[0052] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When processor 12 receives a request from the host via host interface 13, it performs control according to the request. For example, according to a request from the host, processor 12 instructs memory interface 15 to write user data and parity information to non-volatile memory 2. Additionally, according to a request from the host, processor 12 instructs memory interface 15 to read user data and parity information from non-volatile memory 2.

[0053] Processor 12 determines the storage area (memory region) on non-volatile memory 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for data written in units of pages (page data). In this specification, one page of user data stored in non-volatile memory 2 is defined as cell data. Cell data is generally encoded and stored as codewords in non-volatile memory 2. In this embodiment, encoding is not necessary. Although memory controller 1 may also store cell data in non-volatile memory 2 without encoding, in... Figure 1 In this example, the encoding configuration is shown. When the memory controller 1 does not perform encoding, the page data and the cell data are identical. Alternatively, a single codeword can be generated based on one cell of data, or a single codeword can be generated based on segmented data of segmented cell data. Furthermore, a single codeword can also be generated using multiple cell data sets.

[0054] Processor 12 determines the memory region of non-volatile memory 2 as the destination for each unit of data. A physical address is allocated within the memory region of non-volatile memory 2. Processor 12 uses the physical address to manage the memory region as the destination for writing unit data. Processor 12 instructs memory interface 15 to write user data to non-volatile memory 2 by specifying the determined memory region (physical address). Processor 12 manages the mapping between logical addresses (host-managed logical addresses) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address, assigns the physical address, and instructs memory interface 15 to read the user data.

[0055] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0056] RAM11 temporarily stores user data received from the host until it is stored in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 until it is sent to the host. RAM11 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0057] exist Figure 1 The diagram shows an example configuration where the memory controller 1 includes both an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0058] Upon receiving a write request from the host, the memory system operates as follows: Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface 15. Memory interface 15 writes the input codeword to non-volatile memory 2.

[0059] Upon receiving a read request from the host, the memory system operates as follows: The memory interface 15 inputs the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in RAM 11. The processor 12 then sends the data stored in RAM 11 to the host via the host interface 13.

[0060] (The structure of non-volatile memory)

[0061] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. The non-volatile memory 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequence generator 25, a voltage generation circuit 26, a row decoder 27, a sense amplifier 28, an input / output pad group 29, a logic control pad group 30, and a power input terminal group 31.

[0062] The memory cell array 21 contains multiple non-volatile memory cells (not shown) associated with word lines and bit lines. Each memory cell corresponds to a row and a column. The memory cell array 21 has multiple block BLKs. The memory cell array 21 contains multiple memory cells. As described later, each memory cell can store n (n is an integer of 2 or more) bits of data per memory cell.

[0063] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS between itself and the memory controller 1. The input / output circuit 22 transfers the instruction and address contained in the signal DQ<7:0> to the register 24. Additionally, the input / output circuit 22 transmits and receives write data and read data between itself and the sense amplifier 28.

[0064] The logic control circuit 23 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP from the memory controller 1. Additionally, the logic control circuit 23 transmits the ready-to-work signal / RB to the memory controller 1 and notifies the external system of the status of the non-volatile memory 2.

[0065] Register 24 stores instructions, addresses, and status. More specifically, register 24 contains instruction register 24A, address register 24B, and status register 24C, which store instructions, addresses, and status respectively.

[0066] The sequence generator 25 is a control circuit that controls the operation of the entire non-volatile memory 2 based on the instructions held in the instruction register 24A.

[0067] The voltage generation circuit 26 generates the voltage required for data writing, reading, and erasing based on the instructions from the sequence generator 25.

[0068] The line decoder 27 receives the block address and line address contained in the address from the address register 24B, selects the corresponding block based on the block address, and selects the corresponding word line based on the line address.

[0069] When reading data, the sense amplifier 28 senses the data read from the memory cell to the bit line and transmits the sensed read data to the input / output circuit 22. When writing data, the sense amplifier 28 transmits the write data written via the bit line to the memory cell. More specifically, the sense amplifier 28 includes a group of sense amplifier cells 28A and a data register 28B. When reading data, the read data read through the group of sense amplifier cells 28A is stored in the data register 28B. Furthermore, when writing data, the write data stored in the data register 28B is transmitted to the group of sense amplifier cells 28A, and write data is written from the group of sense amplifier cells 28A to the memory cell via the bit line.

[0070] The input / output pad group 29 has multiple terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS because it transmits and receives signals containing data between itself and the memory controller 1.

[0071] The logic control pad group 30, because it transmits and receives various signals with the memory controller 1, has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP.

[0072] The power input terminal group 31 provides various operating power supplies to the non-volatile memory 2 from the outside, and therefore has multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc, as the operating power supply, is generally an externally supplied circuit power supply voltage, and is input at, for example, approximately 3.3V. The power supply voltage VccQ is input at, for example, 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, and is input at, for example, 12V. When writing or erasing data to the memory cell array 21, a higher voltage of approximately 20V is required. In this case, compared to the power supply voltage Vcc, which is boosted to approximately 3.3V by the voltage generation circuit 26, the power supply voltage Vpp, boosted to approximately 12V, can generate the desired voltage at a higher speed and with lower power consumption. On the other hand, in environments where the non-volatile memory 2 cannot be supplied with high voltage, for example, the power supply voltage Vpp may not be required. Even without the power supply voltage Vpp, the non-volatile memory 2 can still perform various operations if the power supply voltage Vcc is supplied. That is, the power supply voltage Vcc is the standard power supply provided to the non-volatile memory 2, and the power supply voltage Vpp is an additional / arbitrarily supplied power supply depending on, for example, the usage environment.

[0073] (The structure of a NAND memory cell array)

[0074] Figure 3 This is a diagram illustrating an example of the structure of a block of a 3D memory cell array 21. Figure 3 This represents one block BLK among the multiple blocks constituting the 3D memory cell array 21. The other blocks of the memory cell array 21 also have the same characteristics. Figure 3 The same structure applies. Furthermore, this embodiment can also be applied to 2D memory cell arrays.

[0075] As shown in the figure, block BLK contains, for example, four string cells (SU0 to SU3). Each string cell SU contains multiple NAND strings NS. Each NAND string NS contains eight memory cells MT (MT0 to MT7) and select transistors ST1 and ST2. While the number of memory cells MT contained in the NAND string NS is eight, it is not limited to eight; for example, it could be 32, 48, 64, or 96. Although select transistors ST1 and ST2 are represented as a single transistor in the electrical circuit, their construction can be the same as that of the memory cell transistors. Furthermore, for example, to improve cutoff characteristics, multiple select transistors can be used as select transistors ST1 and ST2. Additionally, dummy cell transistors can be placed between the memory cells MT and the select transistors ST1 and ST2.

[0076] Multiple memory cells MT are connected in series between select transistors ST1 and ST2. Memory cell MT7 is connected to select transistor ST1 at one end of the multiple memory cells MT, and memory cell MT0 is connected to select transistor ST2 at the other end of the multiple memory cells MT.

[0077] The gates of the selection transistors ST1 of each of the serial cells SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3. On the other hand, the gates of the selection transistors ST2 are shared by multiple serial cells SU within the same BLK and connected to the same selection gate line SGS. In addition, the gates of memory cells MT0 to MT7 within the same BLK are shared by word lines WL0 to WL7. That is, word lines WL0 to WL7 and selection gate line SGS are shared by multiple serial cells SU0 to SU3 within the same BLK, while the selection gate line SGD is independent in each of the serial cells SU0 to SU3, even within the same BLK.

[0078] The gates of memory cells MT0 to MT7, which constitute the NAND string NS, are connected to word lines WL0 to WL7, respectively. The gates of memory cells MTi, which are in the same row within block BLK, are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS may be simply referred to as "string".

[0079] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell MT is connected to the bit line via the select transistor ST or other memory cell MT contained in the NAND string NS. As described above, the data of the memory cells MT within the same BLK is erased simultaneously. On the other hand, data is read and written in memory cell group MG units (or page units). In this specification, a group of memory cells MT connected to one word line WLi and belonging to one string unit SU is defined as a memory cell group MG. In this embodiment, the non-volatile memory 2 is a QLC (Quad-Level Cell) NAND memory capable of holding 4 bits (16 values) of data. Therefore, one memory cell group MG can hold 4 pages of data. The 4 bits held by each memory cell MT correspond to the 4 pages.

[0080] Figure 4 This is a cross-sectional view of a portion of a 3D constructed NAND memory cell array. (Example) Figure 4 As shown, multiple NAND strings NS are formed on the p-well region. That is, on the p-well region, multiple wiring layers 333 that function as select gate line SGS, multiple wiring layers 332 that function as word line WLi, and multiple wiring layers 331 that function as select gate line SGD are stacked.

[0081] Furthermore, a memory via 334 is formed, penetrating the wiring layers 333, 332, and 331 to reach the p-type well region. On the side of the memory via 334, a block insulating film 335, a charge storage film (charge holding region) 336, and a gate insulating film 337 are sequentially formed, and a conductive pillar 338 is further embedded within the memory via 334. The conductive pillar 338 comprises, for example, polysilicon and functions as a channel forming region when the memory via MT and select transistors ST1 and ST2 within the NAND string NS are activated. That is, wiring layer 331, conductive pillar 338, and the films 335-337 between them function as select transistor ST1; wiring layer 332, conductive pillar 338, and the films 335-337 between them function as memory cell MT; and wiring layer 333, each conductive pillar 338, and the films 335-337 between them function as select transistor ST2.

[0082] In each NAND string NS, a select transistor ST2, multiple memory cells MT, and a select transistor ST1 are sequentially formed on the p-type well region. Above the conductor post 338, a wiring layer is formed to function as the bit line BL. At the upper end of the conductor post 338, a contact plug 339 is formed to connect the conductor post 338 and the bit line BL.

[0083] Furthermore, an n+ -type impurity diffusion layer and a p+ -type impurity diffusion layer are formed in the surface of the p-type well region. A contact plug 340 is formed on the n+ -type impurity diffusion layer, and a wiring layer that functions as a source line SL is formed on the contact plug 340.

[0084] The above Figure 4 illustrated configuration is arranged in plural in the depth direction of the drawing sheet of Figure 4 , and one string unit SU is formed by a collection of a plurality of NAND strings arranged in a column in the depth direction.

[0085] (Threshold Voltage Distribution)

[0086] Figure 5 is a diagram showing the threshold voltage distribution of a memory cell (memory cell transistor). Figure 5 shows an example of the threshold voltage distribution of the 4-bit per cell non-volatile memory 2. In the non-volatile memory 2, the threshold voltage of a memory cell MT is set according to each data value of the multi-value data (4 bits in this case) stored in the memory cell MT. That is, each memory cell MT can store n bits of data (n is an integer of 2 or more), and the threshold voltage corresponding to each data value is set in each memory cell MT. Since the injection amount of charge into the charge storage film (charge retention region) is probabilistic, as shown in Figure 5 , the threshold voltage of each memory cell MT also has a statistical distribution.

[0087] As will be described later, 4 bits correspond to data of a Lower Level page, a Middle Level page, an Upper Level page, and a Top Level page.

[0088] In addition, in the present embodiment, data writing is performed in two stages. A sequence generator 25 can execute a first write operation (an MLC write operation described later) of writing p (p < n) bits of data out of n bits to each memory cell, and a second write operation (a QLC write operation described later) of writing n bits of data by additionally writing (n-p) bits of data to each memory cell after the first write operation. In the second write operation (QLC write operation), the sequence generator 25 executes a program operation for writing n bits of data, and a verify operation for verifying the n bits of data written by the program operation.

[0089] In the present embodiment, 2 bits of data are written to the lower page and the middle page in the first write operation, and 4 bits of data are written by additionally writing 2 bits of data of the upper page and the top page in the second write operation. Figure 5This represents the threshold voltage distribution of memory cells MT after data is written to the parent and top-level pages. As described later, in the first write operation, data corresponding to any one of the four levels Er, A, B, and C corresponding to the four threshold voltage distributions is written to each memory cell MT. That is, in the first write operation, data corresponding to any one of the four levels Er, A, B, and C corresponding to the four threshold voltage distributions corresponding to 2 bits of data is written to each memory cell MT. Using the second write operation, data corresponding to any one of the 16 states Er, S1, ..., S15 corresponding to the 16 threshold voltage distributions corresponding to 4 bits of data is written to each memory cell MT.

[0090] Figure 5 The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. The threshold voltage distribution is represented by 16 mountain-shaped regions: DEr, DS1, DS2, DS3, ..., DS13, DS14, and DS15. The width of the threshold voltage in each region corresponds to the width of the target region. Figure 5 In the example, by setting the threshold voltage of the memory cell MT in any of the 16 target regions, the memory cell MT can store data (4 bits) that can obtain 16 values.

[0091] In this embodiment, the threshold voltage Vth is... Figure 5 The target region with a threshold voltage below Vr1 is called state Er; the target region with a threshold voltage greater than Vr1 but less than Vr2 is called state S1; the target region with a threshold voltage greater than Vr2 but less than Vr3 is called state S2; and the target region with a threshold voltage greater than Vr3 but less than Vr4 is called state S3. The same applies below. Figure 5 As shown, the voltage settings are S4 to S15.

[0092] In other words, the state represents any target region corresponding to the data value stored in each memory cell MT. In the case of 4-bit 16-value pairs, the target region is divided into 16 states: Er, S1 to S15. Furthermore, the threshold voltage distributions corresponding to each state Er, S1, S2, S3, ..., S13, S14, S15 are respectively called distributions DEr, DS1, DS2, DS3, ..., DS13, DS14, DS15. Voltages Vr1 to Vr15 serve as reference voltages that define the boundaries of each target region. In addition, during the verification operation, voltages Vr1 to Vr15 are applied to the word line WL as verification voltages, and the current flowing in the bit line BL is sensed by the sensing amplifier unit SAU. When the memory cell MT to be determined is disconnected, it is determined that the threshold voltage corresponding to the state has been reached.

[0093] (Sensing amplifier)

[0094] Next, the operation of the sensing amplifier 28 for reading and testing will be explained.

[0095] Figure 6 This is a circuit diagram illustrating an example of the specific configuration of a sense amplifier unit included in a sense amplifier unit group 28A and a latch circuit XDL included in its corresponding data register 28B. The sense amplifier 28 includes a sense amplifier unit group 28A and a data register 28B. The sense amplifier unit group 28A includes multiple sense amplifier units SAU, each associated with bit lines BL0 to BL(m-1). Furthermore, the data register 28B includes multiple latch circuits XDL, each corresponding to one of the multiple sense amplifier units SAU. Figure 6 The diagram shows the detailed circuit configuration of a sense amplifier unit SAU connected to a bit line BL and a latch circuit XDL.

[0096] like Figure 6 As shown, the sense amplifier unit SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, FDL, and XDL are connected in a manner that allows them to receive data from each other. The latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and FDL are connected via a bus LBUS. The bus LBUS and the latch circuit XDL are connected via transistor 54 and a bus DBUS. The latch circuits SDL, ADL, BDL, CDL, DDL, EDL, FDL, and XDL temporarily hold read data, write data, and various other data, which will be described later. The latch circuit XDL is connected to the input / output circuit 22 and is used to input and output data between the sense amplifier unit SAU and the sequence generator 25. A control signal SW is input to the gate of transistor 54. The control signal SW controls the connection and disconnection of the bus LBUS and the bus XBUS.

[0097] The latch circuits ADL and BDL store lower-level page data and intermediate-level page data, respectively. The latch circuits CDL and DDL store upper-level page data and top-level page data, respectively. As described later, the latch circuits EDL and FDL store information related to the write data (threshold voltage) of the adjacent memory cell MT.

[0098] The latch circuits ADL, BDL, CDL, and DDL store 4 bits of data written to the memory. The latch circuits EDL and FDL store information related to the threshold voltages of the two adjacent memory cells MT, which will be described later. If a memory cell on the select word line WLn is designated as memory cell MT1, then information regarding the threshold voltages of the adjacent memory cell MT2 (adjacent to memory cell MT1) on the adjacent word line WL(n+1) and the adjacent memory cell MT3 (adjacent to memory cell MT1) on the adjacent word line WL(n-1) (also adjacent to memory cell MT1) (here, information indicating whether it is at the Er level) is stored in the latch circuits EDL and FDL respectively. For example, if the latch circuit EDL stores the data "1", it indicates that the threshold voltage of the adjacent memory cell MT2 is at the "Er" level.

[0099] The latch circuit SDL includes, for example, inverters 50 and 51, and n-channel MOS (Metal Oxide Semiconductor) transistors 52 and 53. The input node of inverter 50 and the output node of inverter 51 are connected to node LAT. The input node of inverter 51 and the output node of inverter 50 are connected to node INV. Inverters 50 and 51 hold the data in nodes INV and LAT. Write data from sequence generator 25 is supplied to node LAT. The data held in node INV is the inverted version of the data held in node LAT.

[0100] One end of the drain / source path of transistor 52 is connected to node INV, and the other end is connected to the bus LBUS. Similarly, one end of the drain / source path of transistor 53 is connected to node INV, and the other end is connected to the bus LBUS. A control signal STL is input to the gate of transistor 53, and a control signal STI is input to the gate of transistor 52.

[0101] Furthermore, since the circuit configurations of each latch circuit (ADL, BDL, CDL, DDL, EDL, and XDL) are the same as those of the latch circuit (SDL), their descriptions are omitted. Additionally, the various control signals supplied to the sense amplifier unit (SAU) are provided by the sequence generator (25).

[0102] The sensing amplifier section SA includes, for example, a p-channel MOS transistor 40, n-channel MOS transistors 41-48, and a capacitor 49.

[0103] During the readout operation, the sensing amplifier section SA senses the data read from the corresponding bit line BL and determines whether the read data is "0" or "1". In addition, during the programming operation, the sensing amplifier section SA sets the corresponding bit line BL to the voltage value corresponding to the written data "0" or "1".

[0104] In the sensing amplifier section SA, transistors 40 to 44 are related to program operation. The source / drain paths of transistor 40 and transistor 41 are connected in series between the power supply line supplying the internal power supply voltage (VDD) and node COM. Additionally, the drain / source path of transistor 44 is connected between node COM and node SRC supplying the ground voltage (Vss). Furthermore, the drain / source paths of transistor 42 and transistor 43 are connected in series between node COM and bit line BL.

[0105] The gates of transistors 40 and 44 are connected to node INV. Therefore, when node LAT corresponds to a "0" data level and is low (hereinafter also referred to as "L"), INV is maintained at a high level (hereinafter also referred to as "H"), transistor 40 is off and transistor 44 is on. Conversely, when node LAT corresponds to a "1" data level and is "H", node INV is maintained at "L", transistor 40 is on and transistor 44 is off.

[0106] During program execution, the control signals HLL and XXL supplied to the gates of transistors 45 and 46 are "L", and transistors 45 and 46 are turned off. The control signal supplied to transistor 41 is "H", and transistor 41 is turned on. In addition, transistors 42 and 43 are usually turned on during program execution via control signals BLC and BLS.

[0107] Therefore, if the data "0" is held at node LAT, then transistor 40 is off and transistor 44 is on, supplying the bit line voltage Vbl_L (e.g., 0V) from node SRC to bit line BL. Conversely, if the data "1" is held at node LAT, then transistor 40 is on and transistor 44 is off, supplying the bit line voltage Vbl_H (e.g., 2.5V) to bit line BL according to the control signals BLC and BLS given to transistors 42 and 43.

[0108] All transistors 40-48 and capacitor 49 in the sensing amplifier section SA are related to the test operation. The drain / source paths of transistors 45 and 46 are connected in series between the drain of transistor 40 and node COM. Additionally, the drain / source paths of transistors 48 and 47 are connected in series between the bus LBUS and the reference voltage point. The source of transistor 45 and the drain of transistor 46 are connected to the sensing node SEN, which is connected to the gate of transistor 47. Control signals HLL, XXL, the voltage of sensing node SEN, or control signal STB are applied to the gates of transistors 45-48, respectively. The clock CLK is applied to sensing node SEN via capacitor 49.

[0109] Figure 7It is a graph showing the voltage changes of each wire during the write operation. Figure 7 This indicates the voltage changes of each trace in the program. The program operates according to the program voltage and bit line voltage applied to the word lines and bit lines. (Not applicable to word lines...) Figure 7 The block BLK to which voltage is applied (selected WL, non-selected WL) is the non-selected block BLK that is not the object to be written. Figure 7 (Next paragraph). Additionally, because the bit line voltage is applied to the memory cell MT by turning on the select transistor ST1 connected to the bit line BL, the string cells SU in the write target block BLK (select block BLK) where the select gate line SGD is not applied are non-select SUs that are not write targets. Figure 7 (Middle section). Additionally, for the non-selected SU of the selected block BLK (... Figure 7 (Middle section), or before applying the program voltage Vpgm, the select gate line SGD can be set to, for example, 5V to turn on the select transistor ST1.

[0110] The string unit SU (selection SU) of the write object for the block BLK (selection block BLK) of the write object. Figure 7 (Above section), before applying the program voltage Vpgm, such as Figure 7 As shown on the left side of the upper section, for selecting SU, the select gate line SGD is set to, for example, 5V, turning on the select transistor ST1. However, during program operation, the select gate line SGS is, for example, 0V. Therefore, the select transistor ST2 is turned off. On the other hand, in Figure 7 As shown on the right side of the upper section, when the program voltage Vpgm is applied, the select gate line SGD is set to, for example, 2.5V. Therefore, the on / off state of the select transistor ST1 is determined by the bit line voltage connected to the bit line BL of the select transistor ST1.

[0111] As described above, the sense amplifier 28 transmits data to each bit line BL. A ground voltage Vss, for example 0V, is applied as the bit line voltage Vbl_L to the bit line BL assigned "0" data. A write-inhibit voltage Vinhibit (e.g., 2.5V) is applied as the bit line voltage Vbl_H to the bit line BL assigned "1" data. Therefore, when the program voltage Vpgm is applied, the select transistor ST1 connected to the bit line BL assigned "0" data is turned on, and the select transistor ST1 connected to the bit line BL assigned "1" data is turned off. The memory cell MT connected to the turned-off select transistor ST1 becomes write-inhibit.

[0112] The memory cell MT connected to the select transistor ST1, which is in the on state, injects electrons into the charge storage film according to the voltage applied to the word line WL. Although the memory cell MT connected to the word line WL, which is given a voltage Vpass as its word line voltage, is in the on state regardless of the threshold voltage, it does not inject electrons into the charge storage film. On the other hand, the memory cell MT connected to the word line WL, which is given a program voltage Vpgm as its word line voltage, injects electrons into the charge storage film according to the program voltage Vpgm.

[0113] In other words, the row decoder 27 selects any word line WL in the selection block BLK, applies a voltage Vpgm to the selected word line, and applies a voltage Vpass to the other non-selected word lines WL. The voltage Vpgm is a high voltage used to inject electrons into the charge storage film through the tunneling phenomenon, and Vpgm > Vpass. While controlling the voltage of the word line WL through the row decoder 27, the sensing amplifier 28 supplies data to each word line BL, thereby performing the write operation of the memory cell array 21 to each memory cell MT.

[0114] Figure 8 This is a diagram showing the voltage changes of each wiring during the test operation. The row decoder 27 selects the block BLK and string unit SU that have completed the program operation, and applies, for example, 5V to the select gate line SGS of the selected block BLK and the select gate line SGD of the selected string unit SU. As a result, in the NAND string contained in the selected string unit SU, select transistors ST1 and ST2 are turned on.

[0115] On the other hand, a voltage Vss is applied to the select gate line SGS of the non-selected block BLK and the select gate line SGD of the non-selected string unit SU of the selected block BLK, causing the select transistors ST1 and / or ST2 to be in the off state. Thus, in the NAND string contained in the non-selected string unit SU, at least select transistor ST1 is in the off state. Furthermore, in the NAND string contained in the non-selected block BLK, both select transistors ST1 and ST2 are in the off state.

[0116] Additionally, the row decoder 27 selects any word line WL in the selection block BLK, applies a voltage Vcgrv to the selected word line WL, and applies a voltage Vread to the other non-selected gate lines WL. For example, in the case of performing a program operation to set the threshold voltage of the memory cell MT to level A, voltage AV is used as voltage Vcgrv in the verification operation. Similarly, in the case of performing a program operation to set the threshold voltage of the memory cell MT to level B, voltage BV is used as voltage Vcgrv in the verification operation. Voltage Vread is the voltage that turns on the memory cells MT connected to the non-selected word lines WL regardless of their threshold voltage, and is Vread>Vcgrv(GV). In the case of MLC write operation, GV is the verification voltage VrC corresponding to level C, and in the case of QLC write operation, it is the verification voltage Vr15 corresponding to state S15.

[0117] Additionally, for example, in the intermediate page data verification action during the first write operation, such as Figure 8 As shown by the dashed line, the voltage Vcgrv has two voltage levels, level A and level C.

[0118] Furthermore, the sensing amplifier 28 charges each bit line BL to a voltage Vbl. The voltage Vbl is greater than the source line SL voltage Vsl, i.e., Vbl > Vsl. Therefore, in the NAND string contained in the selected string cell SU, current flows (or does not flow) from the bit line BL side to the source line SL side according to the threshold voltage of the memory cell MT connected to the select word line WL. This allows verification that the threshold voltage has risen to the desired level.

[0119] As described above, the write operation is performed by repeatedly looping through program and verification operations. In the program operation, a program voltage Vpgm is applied to the select word line WL. In the subsequent verification operation, corresponding to the verification threshold voltage level, at least one of the verification voltages VrA to C corresponding to levels A to C is applied in the case of an MLC write operation, and at least one of the verification voltages Vr1 to Vr15 corresponding to states S1 to S15 is applied in the case of a QLC write operation. Furthermore, sometimes in each loop, the verification operation is performed multiple times after the program operation. Conversely, sometimes in each loop, the verification operation is not performed after the program operation. That is, the write operation comprises multiple loops, each loop containing at least a program operation. Additionally, each loop may contain one or more verification operations. In each loop, the verification operation is performed after the program operation.

[0120] In the first loop, the program voltage Vpgm is set to the lowest possible value. As the loop progresses in the second, third, and subsequent loops, the program voltage Vpgm is gradually increased to a higher value. Additionally, the states for the verification operation in each loop are pre-defined. As described later, in each target state, the verification operation begins looping. The verification operation for each state is performed only within specific loops. Using this verification operation, once the threshold voltage reaches the memory cell MT in the set target region, writing is disabled.

[0121] (action)

[0122] Data is written using a multi-stage (two-stage in this embodiment) write method, which involves splitting the write sequence into multiple executions. In the two-stage write method, in the first execution, half of the n1 (n1=4 in this embodiment) pages (two pages in this embodiment) are written, and in the second execution, the remaining half of the pages (two pages in this embodiment) are written.

[0123] Figure 9 This is a graph showing the distribution of the threshold voltage Vth in the two-stage write mode. Figure 9 The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells.

[0124] like Figure 9 As shown, in the first write operation, the memory cell MT is used to store 2-bit data in an MLC (Multiple Level Cell). This first write operation is also called the MLC write operation. In the first write operation (MLC write operation), any one of the four data values ​​(level Er, A, B, C) is written to each memory cell MT. In the second write operation, the memory cell MT is used to store 4-bit data in a QLC. This second write operation is also called the QLC write operation. In the second write operation (QLC write operation), any one of the 16 data values ​​(states S0 to S15) in each cell is written to each memory cell MT.

[0125] In an MLC write operation, data is written to the lower-level and middle-level pages within a 4-page range. That is, in the first write operation, any one of the four values ​​(Er, A, B, C) is written to the memory cells MT within the memory cell group MG corresponding to a select gate line SGD in the select word line WL. Figure 9In this context, "M" represents the read voltage for intermediate page data, and "L" represents the read voltage for lower-level page data. This means that data written to lower-level and intermediate pages is written in a way that allows it to be read even before a QLC write operation is performed.

[0126] like Figure 9 As shown, the QLC write operation further divides the four-value level written by the MLC write operation into four levels, thereby writing 16-value data into each memory cell MT.

[0127] There is a case where the sequence generator 25 writes, for example, four pages of data at a time to each memory cell MT contained in the memory cell group MG. In this case, for example, the latch circuits ADL, BDL, CDL, and DDL store lower-level, middle-level, upper-level, and top-level page data, respectively. The sequence generator 25 uses the data stored in the four latch circuits ADL, BDL, CDL, and DDL to write four pages of data to each memory cell group MG.

[0128] In the two-stage write method, the sequence generator 25 performs a QLC write operation after executing an MLC write operation. More specifically, after performing the MLC write operation, the sequence generator 25 allocates time to perform a QLC write operation. In this case, during the QLC write operation, the sequence generator 25 reads lower-level page data and intermediate-level page data from each memory cell MT that is the target of the QLC write operation. The sequence generator 25 uses the read lower-level page data and intermediate-level page data, along with the upper-level page data and top-level page data received from the memory controller 1, to perform the QLC write operation. This reduces the amount of data transferred from the memory controller 1 to the non-volatile memory 2.

[0129] Figure 10 This is a diagram showing the sequence of write actions in a two-stage write method. Figure 10 It only represents a portion of the multiple word lines WL, from WL0 to WL2, and the string unit represents the five cases from SU0 to SU4. Figure 10 The numbers within the brackets "[" and "]" indicate the order of the writing actions.

[0130] In the two-stage write mode, writing to two adjacent word lines (WL) is performed alternately. For example... Figure 10 As shown, after the MLC write operation of string units SU0 to SU4 to word line WL0 is executed in sequence ([1] to [5]), the MLC write operation of string unit SU0 to word line WL1 is performed ([6]).

[0131] After the MLC write operation of the serial unit SU0 to the word line WL1 ([6]), the QLC write operation of the serial unit SU0 to the word line WL0 is performed ([7]). After the QLC write operation of the serial unit SU0 to the word line WL0, the process returns to the serial unit SU1 and performs the MLC write operation of the serial unit SU1 to the word line WL1 ([8]).

[0132] Then, similarly, Figure 10 As shown, the MLC write operation and QLC write operation on word line WL0 and word line WL1 are executed alternately ([9]~

[15] ).

[0133] After the QLC write operation of serial unit SU4 to word line WL0 (

[15] ), the MLC write operation of serial unit SU0 to word line WL2 is performed (

[16] ). After the MLC write operation of serial unit SU0 to word line WL2 (

[16] ), the QLC write operation of serial unit SU0 to word line WL1 is performed (

[17] ).

[0134] Then, in the same manner as the MLC write operation and QLC write operation for word line WL0 and word line WL1, the MLC write operation and QLC write operation for word line WL1 and word line WL2 are executed alternately (

[17] ~).

[0135] As described above, after all memory cells MT on word lines WL(n-1) of all serial units SU0 to SU4 have performed QLC write operations (

[15] ), an MLC write operation is performed on one memory cell MT on word line WL(n+1) of serial unit SU0 (

[16] ). Furthermore, after performing an MLC write operation on the memory cell MT, the process returns to word line WLn of serial unit SU0 and performs a QLC write operation (

[17] ).

[0136] In the two-stage write method, after performing the MLC write operation, a QLC write operation is performed after a certain period of time. Here, due to the passage of time, data preservation deteriorates (the threshold voltage of the memory cell MT changes over time due to the change in electrons held by the memory cell MT). For example, even if data in state S15 is written to a memory cell MT through the QLC write operation, and the threshold voltage of the adjacent memory cell MT is a low threshold voltage such as Er, the threshold voltage distribution of the memory cell MT in state S15 is affected by the adjacent memory cell MT of the adjacent word line, and deviates in the direction of the lower threshold voltage.

[0137] Figure 11 and Figure 12 This is a diagram showing an example of the threshold voltage distribution of two adjacent memory cells MT on two adjacent word lines WLn and WL(n+1). Figure 11The lower segment represents the threshold voltage distribution for the memory cell MT performing a QLC write operation on the word line WLn level C.

[0138] For example, when the threshold voltage distribution of a memory cell MT1 of the selected word line WLn becomes level C through the MLC write operation, the threshold voltage of the memory cell MT (hereinafter also referred to as MT1) at level C becomes any one of states S12 to S15 through the QLC write operation.

[0139] Figure 11 The upper segment represents the threshold voltage distribution of the adjacent memory cell MT (that is, the memory cell of the adjacent word line WL(n+1) (hereinafter also referred to as MT2)) of memory cell MT1, which becomes level C when the QLC write operation is performed. The threshold voltage distribution of memory cell MT2 becomes any one of states S12 to S15 after the subsequent QLC write operation.

[0140] Figure 12 The upper section represents the threshold voltage distribution when the threshold voltage level of memory cell MT2 becomes level Er through the MLC write operation, and a QLC write operation is performed. The threshold voltage level of memory cell MT2 becomes any one of states S0 to S3 through the subsequent QLC write operation.

[0141] exist Figure 11 and Figure 12 In any of these cases, the threshold voltage of memory cell MT1 after a QLC write operation is also affected by the charge of the adjacent memory cell MT2, resulting in data retention degradation. However, in Figure 11 In this case, because the difference between the threshold voltage of memory cell MT1 and the threshold voltage of the adjacent memory cell MT2 is small, the charge stored in memory cell MT1 is less likely to leak to memory cell MT2. On the other hand, in Figure 12 In this case, because the threshold voltage difference between memory cell MT1 and the adjacent memory cell MT2 is large, the charge stored in memory cell MT1 is prone to leak into memory cell MT2. Especially Figure 12In this case, because memory cell MT1 has the highest threshold voltage (level C) and the adjacent memory cell MT2 has the lowest threshold voltage (level Er), the charge stored in memory cell MT1 is particularly prone to leaking to memory cell MT2. Therefore, the threshold voltage distribution of memory cell MT1 at level C is prone to change after a QLC write operation, that is, it is prone to deviating towards the lower voltage side. The deviation of the threshold voltage distribution of each memory cell MT1 on word line WLn varies depending on the level (or state) of the threshold voltage of the adjacent memory cell MT2 on the adjacent word line WL(n+1).

[0142] Figure 11 and Figure 12 Although the charge of memory cell MT2 representing the adjacent word line WL(n+1) affects the threshold voltage of memory cell MT1 selecting word line WLn, the charge of memory cell MT3 representing the adjacent word line WL(n-1) also affects the threshold voltage of memory cell MT1.

[0143] Figure 13 This is a graph showing the change in threshold voltage distribution caused by data storage degradation. Figure 13 In the diagram, solid lines represent the threshold voltage distribution immediately after a QLC write operation, while dashed lines or dotted lines represent the threshold voltage distribution that deviates due to data storage degradation.

[0144] exist Figure 11 In this case, because the threshold voltages of the two adjacent memory cells MT1 and MT2 are both high, the amount of charge leakage from memory cell MT1 to the adjacent memory cell MT2 due to data retention degradation is small. In this case, as shown by the dashed line, the deviation in the threshold voltage distribution of memory cell MT1 caused by data retention degradation is small.

[0145] However, in Figure 12 In this case, because the threshold voltage of memory cell MT1 is higher and the threshold voltage of memory cell MT2 is lower, the amount of charge leakage from memory cell MT1 to the adjacent memory cell MT2 due to data retention degradation is greater. Therefore, in Figure 13 As shown by the dotted line, the deviation dTH of the threshold voltage distribution of memory cell MT1 caused by data storage degradation is relatively large.

[0146] The deviation dTH of the threshold voltage distribution of memory cell MT1 caused by data retention degradation varies depending on the charge of the adjacent memory cells MT2 and MT3 of each memory cell MT on the select word line WLn.

[0147] For example, when the threshold voltage distribution of adjacent memory cell MT2 is at level A, the deviation of the threshold voltage distribution in memory cell MT1, where data storage is degraded, is less than... Figure 13 The deviation dTH is shown. Furthermore, when memory cell MT2 is at the threshold voltage level B, the deviation of the threshold voltage distribution in memory cell MT1, where data storage has deteriorated, is further less than... Figure 13 The deviation dTH is shown.

[0148] In addition, as mentioned above, the threshold voltage of memory cell MT1 is affected not only by the level (or state) of the threshold voltage of the adjacent memory cell MT2 of the adjacent word line WL(n+1), but also by the level (or state) of the threshold voltage of the adjacent memory cell MT3 of the adjacent word line WL(n-1).

[0149] Therefore, in this embodiment, the verification voltage level for the QLC write operation of memory cell MT1 is adjusted based on the threshold voltages of the two adjacent memory cells MT2 and MT3.

[0150] Furthermore, since the amount of charge leakage in memory cell MT1 varies depending on the difference between the data (target state) of memory cell MT1 and the data of each adjacent memory cell MT2, MT3, it is preferable to adjust the test voltage level of the QLC write operation based on the difference.

[0151] However, since the charge leakage of memory cell MT1 is the greatest when the difference between the threshold voltage of memory cell MT1 and the threshold voltage of each adjacent memory cell MT2 and MT3 is the greatest, the test voltage level of QLC write operation can be adjusted only when the difference between the data read from memory cells MT2 and MT3 and the data written to memory cell MT1 (target state) is the greatest.

[0152] Therefore, in this embodiment described below, the test voltage level is adjusted only when the difference between the data in adjacent memory cells MT2 and MT3 and the written data (target state) in memory cell MT1 is the greatest. In other words, for example, in Figure 13 In this case, adjust the verification voltage level for the QLC write operation of memory cell MT1.

[0153] The check voltage level is adjusted when the sequence generator 25 performs a QLC write operation. Figure 13 In this context, the test voltage level is set so that the threshold voltage distribution of memory cell MT1 is the higher threshold voltage distribution shown by the two-dot dashed line.

[0154] Next, the sequence of write operations of sequence generator 25 will be described. Figure 14This diagram illustrates the instruction sequence for an MLC write operation. During an MLC write operation, memory controller 1 outputs the MLC write instruction, address, and data to non-volatile memory 2. The MLC write instruction is the instruction that instructs the execution of the MLC write.

[0155] Sequence generator 25 receives an MLC write command. Furthermore, after receiving the MLC write command, sequence generator 25 receives the address and write data. After receiving the command, address, and data, sequence generator 25 performs the MLC write operation. The received data is stored in two latch circuits, ADL and BDL, via latch circuit XDL. Sequence generator 25 performs the MLC write operation based on the lower-level page data and intermediate-level page data stored in latch circuits ADL and BDL.

[0156] Figure 15 This diagram illustrates the instruction sequence for a QLC write operation. During a QLC write operation, memory controller 1 outputs a QLC write instruction, address, and data to non-volatile memory 2. The QLC write instruction is the instruction that instructs the execution of a QLC write.

[0157] First, the sequence generator 25 receives the QLC write command. After receiving the QLC write command, the sequence generator 25 receives the address and data. After receiving the data, the sequence generator 25 reads the data from each memory cell MT of the memory cell group MG corresponding to the adjacent word line WL(n+1) and each memory cell MT of the memory cell group MG corresponding to the adjacent word line WL(n-1). The process of reading data from each memory cell MT of the memory cell group MG corresponding to the adjacent word line WL(n+1) and each memory cell MT of the memory cell group MG corresponding to the adjacent word line WL(n-1) is also called the adjacent cell readout process (NDR).

[0158] Hereinafter, the data written via the MLC write action will also be referred to as MLC write data. In the adjacent cell read process (NDR), the MLC write data of the adjacent word line WL(n-1) and the MLC write data of the adjacent word line WL(n+1) are read.

[0159] Next, the sequence generator 25 reads the MLC write data from each memory cell MT of the memory cell group MG corresponding to the selection word line WLn. The process of reading the MLC write data from each memory cell MT of the memory cell group MG corresponding to the selection word line WLn is also called the Write Target Cell Read Process SDR. In the Write Target Cell Read Process SDR, the reading of the lower-level page and the reading of the intermediate-level page written to the selection word line WLn via the MLC write action are performed.

[0160] As described above, if the sequence generator 25 receives a QLC write instruction during a QLC write operation, it will execute the adjacent cell readout process NDR, which reads the data of multiple memory cells MT on adjacent word lines WL(n+1) and WL(n-1), and the write target cell readout process SDR, which reads the MLC write data of each memory cell MT on the selected word line WLn.

[0161] Hereinafter, the process that includes the adjacent cell readout process (NDR) and the write target cell readout process (SDR) will be referred to as the internal data readout process (IDL1).

[0162] Furthermore, the sequence generator 25 performs a QLC write operation. During the QLC write operation, a program operation and a verification operation are performed. The program operation includes applying a program voltage to the select word line WL and applying a verification voltage. The QLC write operation is performed based on the data of the lower and middle level pages, and the data of the upper and top level pages. The data of the lower and middle level pages is obtained through the write object unit read processing SDR and stored in the data latch circuits ADL and BDL. The data of the upper and top level pages is sent from the memory controller 1 and stored in the data latch circuits CDL and DDL.

[0163] The sequence generator 25 adjusts the test voltage level of the QLC write operation based on the difference between the data (i.e. the level of the threshold voltage distribution) of multiple memory cells (hereinafter also referred to as adjacent memory cells) MT of adjacent word lines WL(n+1) and WL(n-1) and the data (i.e. the level of the threshold voltage distribution) of multiple memory cells (hereinafter also referred to as write target memory cells) MT of word line WLn.

[0164] The QLC write operation will be explained in more detail.

[0165] Figure 16 It is a diagram showing the instruction sequence of the QLC write operation and the storage status of the data in the seven latch circuits XDL to FDL that accompany the execution of the instruction sequence.

[0166] When the ready-to-work signal / RB is high, the sequence generator 25 receives instruction c1 specifying the parent page data, write instruction c2, address data (Add(WLn)), parent page data (Data_U), and instruction c3. The instructions and addresses sent from the memory controller 1 are stored in instruction register 24A and address register 24B, respectively. The parent page data (Data_U) is transferred to the latch circuit XDL and stored.

[0167] like Figure 16As shown, sequence generator 25 sets the ready-busy signal / RB to a low level and, based on the instruction stored in instruction register 24A, transfers the upper-level page data (Data_U) stored in latch circuit XDL to latch circuit CDL. After the transfer, the ready-busy signal / RB goes high.

[0168] Next, when the ready-to-work signal / RB is high, the sequence generator 25 receives the instruction c4 specifying the top-level page data, the write instruction c2, the address data (Add(WLn)), the top-level page data (Data_T), and the instruction c5. The instructions and addresses sent from the memory controller 1 are stored in the instruction register 24A and the address register 24B, respectively. The top-level page data (Data_T) is transferred to the latch circuit XDL and stored.

[0169] like Figure 16 As shown, the sequence generator 25 sets the ready-busy signal / RB low and, based on the instruction stored in the instruction register 24A, transfers the top-level page data (Data_T) stored in the latch circuit XDL to the latch circuit DDL.

[0170] Next, sequence generator 25 performs internal data readout processing IDL1.

[0171] In the adjacent cell readout process (NDR), the MLC write data of multiple memory cells MT of two adjacent word lines WL(n+1) and WL(n-1) is read out.

[0172] like Figure 16 As shown, data is read from adjacent word lines WL(n+1) (WL(n+1)read). Based on the result of the data read, the sequence generator 25 stores the information related to the written data (threshold voltage) of the adjacent memory cell MT2 in the latch circuit EDL.

[0173] Figure 17 This is a diagram representing the data stored in the latch circuit EDL. For example... Figure 17 As shown, when the read data (threshold voltage) is at levels A, B, or C, the sequence generator 25 stores "0" in the latch circuit EDL. Conversely, when the read data (threshold voltage) is at level Er, the sequence generator 25 stores "1" in the latch circuit EDL.

[0174] Next, the MLC write data of multiple memory cells MT on adjacent word lines WL(n-1) is read out.

[0175] Next, as Figure 16As shown, data is read from adjacent word lines WL(n-1) (WL(n-1)read). Based on the result of the data read, the sequence generator 25 stores information related to the written data (threshold voltage) of the adjacent memory cell MT2 in the latch circuit FDL.

[0176] Next, the adjacent cell readout process (NDR) executes the write target cell readout process (SDR). In the write target cell readout process (SDR), the MLC write data of multiple memory cells MT along the word line WLn is read. The sequence generator 25 stores the results of the data readout in latch circuits ADL and BDL. Lower-level page data is stored in the chip circuit ADL, and intermediate-level page data is stored in the latch circuit BDL.

[0177] The sequence generator 25 adjusts the test voltage level based on the data stored in the latch circuits ADL to FDL, and performs a write operation on the word line WLn (the memory cell group MG selected by the combination of word line WLn and select gate line SGD).

[0178] As described above, in this embodiment, the check voltage level is adjusted for the memory cell MT that writes data at level C via the MLC write operation in the select word line WLn. Therefore, the check voltage level is adjusted during the check operation after the program operation to the memory cell MT in the target states S12 to S15.

[0179] Figure 18 It is a graph used to illustrate the relationship between the threshold voltage distribution and the data of the latch circuits ADL to FDL for testing the action. Figure 18 The horizontal axis of the included distribution map represents the threshold voltage, and the vertical axis represents the number of memory cells MT corresponding to the threshold voltage of the memory cell group MG. Figure 19 This is a graph showing the change in the test voltage level when the test operation in state S15 is performed. Figure 19 The horizontal axis represents time, and the vertical axis represents the test voltage level (or readout voltage VCG).

[0180] Figure 18 SS1 represents the change in data in latch circuits ADL to FDL when the MLC write data of two adjacent memory cells MT2 and MT3 on adjacent word lines WL(n+1) and WL(n-1) are both at level Er (Example 1). Latch circuits EDL and FDL store "1". Latch circuits ADL to DDL store "0" as the data corresponding to state S15.

[0181] Figure 18SS2 represents the change in data in latch circuits ADL to FDL when the MLC write data of adjacent memory cell MT2 of adjacent word line WL(n+1) is any one of level A, B, or C, and the MLC write data of adjacent memory cell MT3 of adjacent word line WL(n-1) is level Er (Example 2). In latch circuit EDL, "0" is stored; in latch circuit FDL, "1" is stored. In latch circuits ADL to DDL, "0" is stored respectively as the data corresponding to state S15.

[0182] Figure 18 SS3 represents the change in data in latch circuits ADL to FDL when the MLC write data of adjacent memory cell MT2 of adjacent word line WL(n+1) is at level Er, and the MLC write data of adjacent memory cell MT3 of adjacent word line WL(n-1) is at any one of levels A, B, or C (Example 3). In latch circuit EDL, "1" is stored; in latch circuit FDL, "0" is stored. In latch circuits ADL to DDL, "0" is stored respectively as the data corresponding to state S15.

[0183] Figure 18 SS4 represents the change in data in latch circuits ADL to FDL when the MLC write data of two adjacent memory cells MT2 and MT3 on adjacent word lines WL(n+1) and WL(n-1) is at any of the levels A, B, and C (Example 4). Both latch circuits EDL and FDL store "0". Latch circuits ADL to DDL store "0" as the data corresponding to state S15.

[0184] In Example 1, the amount of charge leakage to the adjacent memory cell MT is the greatest. In Example 4, the amount of charge leakage to the adjacent memory cell MT is the least. In Examples 2 and 3, the amount of charge leakage to the adjacent memory cell MT is no more than in Example 1 and no less than in Example 4.

[0185] Therefore, the test voltage level of each memory cell MT1 is set to any one of the three stages, and the data writing operation is performed.

[0186] The sequence generator 25 performs a verification operation on each memory cell MT1 of the selected word line WLn based on the MLC write data of two adjacent memory cells MT2 and MT3 of adjacent word lines WL(n+1) and WL(n-1), the MLC write data of the memory cell MT1 of the target to be written, and the target status data.

[0187] In each memory cell MT1, if the target state is not any of S12 to S15, then no adjustment of the test voltage level is performed.

[0188] Furthermore, in each memory cell MT1, even if the target state is any of S12 to S15, if the data written to the MLC of the two memory cells MT2 and MT3 is not at the Er level (when it is any of the levels A, B, and C), no adjustment of the test voltage level is performed. In other words, in the case of Example 4, no adjustment of the test voltage level is performed.

[0189] However, in each memory cell MT1, when the target state is any one of S12 to S15, and the MLC write data of one of the two memory cells MT2 and MT3 is at the Er level, the test voltage level is adjusted. That is, in the cases of Examples 2 and 3, the test voltage level is adjusted.

[0190] Furthermore, in each memory cell MT1, even if the target state is any of S12 to S15, and the MLC write data of the two memory cells MT2 and MT3 is at the Er level, the check voltage level is adjusted. That is to say, in the case of Example 1, the check voltage level is also adjusted.

[0191] For the verification actions of each state from S12 to S15, the sequence generator 25 sets multiple verification voltage levels. A verification voltage level is set for each memory cell MT.

[0192] Corresponding to Examples 1-4, such as Figure 19 As shown, the test voltage level is set to multiple levels. Figure 19 This refers to an example where, during the check operation in state S15, multiple check voltage levels Vr15_L1, Vr15_L2, and Vr15_L3 are used instead of the standard single check voltage Vr15. For example, check voltage Vr15_L2 is higher than check voltage Vr15_L1 by a specific offset, and check voltage Vr15_L3 is higher than check voltage Vr15_L2 by a specific offset. In other words, the sequence generator 25 applies multiple check voltage levels in stages during the check operation corresponding to a certain state included in the QLC write operation, replacing the standard single check voltage. The choice of which of the multiple check voltage levels to apply depends on the data written to the two adjacent memory cells MT2 and MT3.

[0193] Apply the test voltage Vr15_L1 to memory cell MT in Example 4. Apply the test voltage Vr15_L2 to memory cell MT in Examples 2 and 3. Apply the test voltage Vr15_L3 to memory cell MT in Example 1.

[0194] exist Figure 18 and Figure 19Although the example shown is of using multiple levels of test voltage in the test operation of state S15, multiple levels of test voltage can also be used in the test operations of states S12, S13, and S14. In the test operations of states S12, S13, and S14, a three-stage test voltage is used, similar to the test operation of state S15. Furthermore, the offset of the test voltage can also be different in each state.

[0195] Therefore, in the verification operation of the state S15 of the selected word line WLn, the verification voltage Vr15_L1 is applied to the memory cell MT of Example 4, the verification voltage Vr15_L2 is applied to the memory cells MT of Examples 2 and 3, and the verification voltage Vr15_L3 is applied to the memory cell MT of Example 1.

[0196] As described above, the sequence generator 25 reads the data written to two memory cells MT2 and MT3 adjacent to memory cell MT1, and sets the check voltage level of multiple check actions for memory cell MT1 used in QLC write actions based on the read data and the data written to memory cell MT1 through the MLC write action.

[0197] Furthermore, the sequence generator 25 changes multiple check voltage levels when both memory cells MT2 and MT3 are at level Er, and when only one memory cell is at level Er. In other words, the sequence generator 25 sets multiple check voltage levels based on the data written to the two memory cells MT2 and MT3.

[0198] Furthermore, if the test operation passes with any one of the test voltages Vr15_L1, Vr15_L2, or Vr15_L3, the data in the latch circuits ADL to DDL corresponding to the memory cell MT is rewritten from all "0"s to all "1"s (representing state S0). That is, the data in the latch circuits ADL to DDL is maintained as all "0"s until the memory cell MT reaches the threshold voltage distribution for state S15. However, if the test operation passes with any one of the test voltages Vr15_L1, Vr15_L2, or Vr15_L3, the data in the latch circuits ADL to DDL corresponding to the memory cell MT is updated from all "0"s (representing state S15) to all "1"s (representing state S0), and the memory cell MT is excluded from the program operation in subsequent loops (set to a write-prohibited state). Furthermore, the data in the latch circuits EDL and FDL are not changed.

[0199] Specifically, in Figure 19In the example, for the memory cell MT corresponding to Example 4, if the test operation passes with the test voltage Vr15_L1, then the data latching operation LO1 of latch circuits ADL to DDL is executed, updating all the data in latch circuits ADL to DDL to "1". For the memory cell MT corresponding to Example 2 or Example 3, if the test operation passes with the test voltage Vr15_L2, then the data latching operation LO2 of latch circuits ADL to DDL is executed, updating all the data in latch circuits ADL to DDL to "1". Furthermore, for the memory cell MT corresponding to Example 1, if the test operation passes with the test voltage Vr15_L3, then the data latching operation LO3 of latch circuits ADL to DDL is executed, updating all the data "0" in latch circuits ADL to DDL to "1".

[0200] Furthermore, in the example described, although latch circuits EDL and FDL corresponding to adjacent word lines WL(n+1) and WL(n-1) are used, only one latch circuit EDL can be used. That is, as long as there is at least one latch circuit that stores the data of two adjacent memory cells of adjacent word lines WL(n+1) and WL(n-1), it is sufficient.

[0201] Figure 20 This is a diagram illustrating an example of data using a single latch circuit, EDL. Figure 20 This indicates that the data-related information of two adjacent memory cells MT2 and MT3 is stored in the data of a latch circuit EDL.

[0202] like Figure 20 As shown, when the data in two adjacent memory cells MT2 and MT3 of word lines WL(n+1) and WL(n-1) is both Er, the sequence generator 25 stores "1" in the latch circuit EDL. When the data in one of the two memory cells MT2 and MT3 is Er, the sequence generator 25 stores "0" in the latch circuit EDL. When the data in both adjacent memory cells MT2 and MT3 is any one of A, B, and C, the sequence generator 25 stores "0" in the latch circuit EDL. In other words, Figure 20 It is a graph showing the reading results of two adjacent memory cells MT2 and MT3 and their corresponding data stored in the latch circuit EDL.

[0203] Figure 21 This is a diagram showing the changes in data read from the latch circuits ADL to EDL when using one latch circuit (EDL). For example... Figure 21 As shown, the MLC write data of multiple memory cells MT2 of adjacent word lines WL(n+1) is read out (WL(n+1)read), and the result of reading out the data is stored in the latch circuit EDL.

[0204] Next, although the MLC write data of multiple memory cells MT3 of adjacent word lines WL(n-1) is read, the sequence generator 25 follows... Figure 20 The diagram shows that data based on the read results of two adjacent memory cells MT2 and MT3 is stored in the latch circuit EDL. Furthermore, the sequence generator 25 performs MLC write data reading (WLn read) of multiple memory cells MT1 on the selected word line WLn, and stores the results of the data reading in the latch circuits ADL and BDL. Simultaneously, the sequence generator 25 adjusts the check voltage level based on the data stored in the latch circuits ADL to EDL, and performs a write operation on the word line WLn.

[0205] Therefore, even using a single latch circuit (EDL), the same effect as described in the embodiment can be achieved.

[0206] As mentioned above, the test voltage level of memory cell MT1 (the memory cell in Example 1) which is assumed to have the most charge leakage to adjacent memory cells MT2 and MT3 is set to a higher level. In addition, the test voltage level of memory cell MT1 (the memory cells in Examples 2 and 3) which is assumed to have a significant amount of charge leakage to adjacent memory cells MT2 and MT3 is also set to a slightly higher level.

[0207] As a result, immediately after the QLC write operation, memory cell MT1, which is adjacent to memory cells MT2 and MT3 at level Er, has a higher threshold voltage distribution. Therefore, even if the threshold voltage distribution of memory cell MT1 shifts to a lower level, the threshold voltage distribution of multiple memory cells MT in the same state within the same word line WL is roughly the same.

[0208] Because the threshold voltage distribution of each memory cell MT1 on the selected word line WLn is affected by the threshold voltage distribution of the corresponding adjacent memory cells MT2 and MT3 on adjacent word lines WL(n+1) and WL(n-1), there is a possibility that the threshold voltage distribution of each memory cell MT1 on the selected word line WLn may be significantly uneven. If additional read voltage level correction processing, such as reading adjacent word lines, is performed in order to read data under uneven threshold voltage distribution conditions, then reading data will take longer.

[0209] In contrast, according to this embodiment, because the occurrence rate of such correction processing is reduced, the time required to read data can be reduced.

[0210] Next, variations of the described implementation will be explained.

[0211] (Variation Example 1)

[0212] In the described embodiment, each sense amplifier unit (SAU) stores data indicating whether the data of adjacent memory units MT2 and MT3 is at level Er in latch circuits EDL and FDL. However, as mentioned above, the amount of charge leakage varies depending on the difference between the data of memory unit MT1 and the data of each adjacent memory unit MT2, MT3. Therefore, each sense amplifier unit (SAU) may also have more latch circuits capable of storing information representing the data (level Er, A, B, C) of adjacent memory units MT2, MT3, and more finely setting multiple test voltage levels based on the difference between the MLC write data (or target state) of memory unit MT1 and the data of adjacent memory units MT2, MT3.

[0213] For example, the test voltage levels can be different when adjacent memory cell MT2 is at level Er and when it is at level A.

[0214] In other words, the sequence generator 25 sets the test voltage level more precisely based on the difference between the data held by the adjacent memory cells MT2 and MT3 and the MLC write data (or target state) of the memory cell MT1.

[0215] Based on this configuration, the test voltage level can be changed more precisely and in stages, and the time required to read data can be suppressed from deteriorating due to data storage degradation.

[0216] (Variation Example 2)

[0217] Alternatively, the test voltage level for the QLC write operation of memory cell MT1 can be adjusted by considering only one of the two adjacent memory cells MT2 and MT3.

[0218] In the described embodiment, when performing a QLC write operation on memory cell MT1 of selected word line WLn, the check voltage level for the QLC write operation of word line WLn is adjusted based on the difference between the two MLC write data of memory cells MT2 and MT3 and the MLC write data (or target state) of memory cell MT1. However, the check voltage level for the QLC write operation of word line WLn can also be adjusted based on the difference between the MLC write data of at least one of the two memory cells MT2 and MT3 of adjacent word lines WL(n+1) and WL(n-1) and the MLC write data (or target state) of memory cell MT1. For example, the check voltage level for the QLC write operation of word line WLn can also be adjusted based on the difference between the MLC write data of memory cell MT2 of adjacent word line WL(n+1) and the MLC write data (or target state) of memory cell MT1.

[0219] Using this embodiment 2, the same effect as the first embodiment can also be obtained.

[0220] (Second Implementation)

[0221] In the first embodiment, during the second write operation (QLC write operation), assuming that charge leakage is caused by future data storage degradation, the test voltage level is pre-adjusted in such a way that the threshold voltage distribution becomes higher if the assumed leakage amount is large.

[0222] However, when a second write operation (QLC write operation) is performed immediately after the first write operation (MLC write operation), no data retention degradation occurs. On the other hand, if a second write operation is performed after a certain period of time following the first write operation, then data retention degradation occurs.

[0223] Therefore, in the second embodiment, during the second write operation, the MLC write data (the data written in the first write operation) is read out, and the deviation of the threshold voltage distribution is detected, which determines the degree of data preservation degradation. Furthermore, based on the deviation, the inspection operation for each state is adjusted and the cycle begins.

[0224] This embodiment, like the first embodiment, uses a multi-segment write method as an example, illustrating that each memory cell group (MG) can hold 4 bits of data, and... Figure 9 The same two-stage write method applies.

[0225] Since the configuration of the memory system in this embodiment is the same as that in the memory system of the first embodiment, the configuration elements that are the same as those in the memory system of the first embodiment are omitted in the configuration elements of the memory system in this embodiment, and the different configuration elements are described in detail.

[0226] First, the changes in the threshold voltage distribution that cause data storage degradation are explained. Figure 22 This is a graph used to illustrate the changes in the threshold voltage distribution of the four levels caused by data retention degradation after performing an MLC write operation.

[0227] Figure 22 The upper section represents the threshold voltage distribution of the four levels Er, A, B, and C immediately after an MLC write operation. "M" represents the read voltage for the intermediate page data, and "L" represents the read voltage for the lower page data. After an MLC write operation, the lower page data can be read using the read voltage L, and the intermediate page data can be read using the read voltage M. The read voltages M and L are preset settings, for example, held by the sequence generator 25. Hereinafter, the reading of data from the lower and intermediate pages will also be referred to as MLC readout.

[0228] Figure 22 The lower section represents the threshold voltage distribution of the four levels Er, A, B, and C after time has elapsed since the MLC write operation was performed. The threshold voltage distribution of the three levels A, B, and C changes due to data retention degradation, and the read voltages M and L applied to the select word line decrease. Figure 22 The lower segment indicates that the read voltage L of level B only decreases by the deviation amount dv.

[0229] The deviation dv is detected by Vth tracking reads, which will be described later. Similarly, the deviation of the threshold voltage distribution of levels A and C is also calculated using Vth tracking reads.

[0230] If the threshold voltage distributions of levels A, B, and C change due to data storage degradation, and MLC data is read using preset read voltages M and L for QLC write operations, there is a possibility that the read data will be read as different data. In this case, a read error occurs. As a result, the reliability of MLC reads during QLC write operations decreases.

[0231] Additionally, it is generally assumed that the check operation is omitted if the threshold voltage has not reached the target state during a QLC write operation. By omitting the check operation, the write time TPROG is shortened. Therefore, the check operation start loop is pre-set to correspond to the multiple loops included in the write operation.

[0232] However, if the threshold voltage distribution shifts to a lower voltage side after an MLC write operation due to data retention degradation, then when the verification operation for the target state begins, the threshold voltage distribution of each memory cell MT will not be close to the target state. Therefore, the write time TPROG unnecessarily increases due to the execution of useless verification operations.

[0233] Therefore, in this embodiment, Vth tracking read is first performed during the MLC read operation of the QLC write operation. The Vth tracking read explores the optimal value of the read voltage for MLC read, and the corrected read voltage obtained through the exploration is used to perform MLC read. Because the QLC write operation is performed using the MLC data read through the MLC read, read errors in MLC read are prevented.

[0234] Figure 23 This is a graph showing the change in read voltage of the select word line WLn, which is tracked by Vth. Figure 24 This is a graph representing the valley location exploration process of Vth tracking and reading.

[0235] like Figure 23As shown, the MLC read operation during a QLC write consists of two read operations: an exploratory read and a best-value read. Hereinafter, the MLC read operation during a QLC write will also be referred to as the Internal Data Read Processing (IDL2). Figure 23 This indicates the optimal values ​​of the readout voltages AR and CR when reading data from intermediate pages.

[0236] Exploratory read is used to trace and read the voltage (Vth) to find the optimal readout voltage. For example... Figure 23 As shown, the exploration reads include the exploration read SR1 with the read voltage AR and the exploration read SR2 with the read voltage CR. Additionally, the optimal value reads include the optimal value read OR1 with the read voltage AR and the optimal value read OR2 with the read voltage CR. Figure 24 This is a graph illustrating the optimal Vth tracking reading of the readout voltage between the two threshold voltage distributions of level Er and level A. The illustration of the optimal Vth tracking reading between level A and level B, and between level B and level C, is omitted.

[0237] like Figure 24 As shown, in Vth tracking readout, multiple readouts are performed to calculate the optimal readout voltage (i.e., the valley position) between level Er and level A. Multiple readouts are performed by varying the readout voltage within a specific range. The specific range and number of readouts for Vth tracking readout are preset based on the deviation of the data storage degradation assumption made from the level-to-level assumptions.

[0238] For example, the valley location can be determined by the ratio of the number of memory cells MT that were connected in each of the multiple reads to the number of memory cells MT that were disconnected.

[0239] In addition, Figure 24 In the middle, although Vth tracking reads are used to explore the valley position of levels Er and A in order to explore the optimal read voltage for intermediate pages, Vth tracking reads are performed for the three optimal read voltages for lower and intermediate pages.

[0240] Figure 24 This represents nine reads performed within a specific range, based on nine distinct read voltages v1 to v9. During the exploratory read, the optimal read voltage is calculated and valley positions are determined based on the read data. Valley positions are then determined for each word line WL.

[0241] As will be described later, the starting position of the inspection cycle is adjusted based on which of the multiple ranges r1, r2, r3, r4, and r5 determined by the Vth tracking read falls within, as specified by the read voltages v1 to v9. In other words, the timing of starting the inspection cycle is adjusted.

[0242] Because the optimal read voltage for each page is calculated before performing MLC readout, readout errors during MLC readout can be prevented.

[0243] In addition, for each target state, a specific inspection action is set to begin the loop.

[0244] Figure 25 This is a diagram showing the relationship between the write operation loop and the check operation. Figure 25 This indicates a loop range from 1 to 36. Preset execution is as follows: Figure 25 The relationship between the state and cycle of the inspection action shown is based on the preset settings for performing the inspection action.

[0245] The data writing process includes both programming and verification actions. Figure 25 This represents a loop that performs checks corresponding to each state. In each state S1 to S15, the program action is executed starting from the first loop. In each state S1 to S15, the program action continues until the maximum loop containing the circle symbol is reached.

[0246] Figure 25 The arrows in the diagram indicate the start of the loop for the inspection action of each target state. Figure 25 The circular notation indicates a loop where verification actions can be performed. For example, the verification action for the data in state S5 proceeds from loop 7 to loop 16. Loop 7 is the start loop for the verification action of S5, and loop 16 is the end loop for the verification action of S5. In other words, since it is assumed that the threshold voltage has not reached the vicinity of the target state (S5) using the program actions of loops 1 to 6 for the data in state S5, the verification actions up to loop 6 are omitted. In this way, by omitting useless verification actions, the write time TPROG is shortened.

[0247] In this embodiment, the verification action of each state is changed and looped according to which of the multiple ranges r1, r2, r3, r4, and r5 the valley position determined by the Vth tracking read falls into.

[0248] In this embodiment, for example, the sequence generator 25 maintains an offset dL corresponding to the valley position determined by Vth tracking, and sets the check action start loop corresponding to the offset dL based on a pre-set chart. Furthermore, the offset for the check action start loop is changed according to the valley position deviation dv. Here, the offset is changed such that the offset (i.e., the number of addition loops) when the valley position is in the range r1 is 2dL, the offset when the valley position is in the range r2 is dL, the offset when the valley position is in the range r3 is 0, the offset when the valley position is in the range r4 is (-dL), and the offset when the valley position is in the range r5 is (-2dL). Thus, for example, when the offset dL is set to "1", even if the check action start loop for a certain state is set to 10 when the valley position is in the range r1, only a delay of 2 loops is made, and the check action start loop for that state is changed to 12. In addition, when the valley position is within the range of r4, even if the check action start loop for a certain state is set to 10, it will only be moved forward by 1 loop, and the check action start loop for that state will be changed to 9.

[0249] In other words, the sequence generator 25 explores the valley positions between the threshold voltage distribution corresponding to the data written via the MLC write operation, and changes the start loop of the verification operation based on the voltage at the explored valley positions. Here, the sequence generator 25 changes the start loop of the verification operation based on the difference between the voltage at the valley positions and the readout voltage preset for reading the MLC data.

[0250] Figure 26 It is a graph showing the change in the threshold voltage distribution for each cycle. Figure 26 This indicates the change in threshold voltage distribution and the start time of the verification action when the program is executed in such a way that the threshold voltage distribution of level B becomes the threshold voltage distribution of state S10.

[0251] For example Figure 9 As shown, the charge distributed by the threshold voltage of level B is written through the QLC, becoming any one of states S6, S7, S10, and S11. The magnitude of the program voltage Vpgm applied in the program action is related to the rise in the threshold voltage of the memory cell MT. Therefore, for a certain state Sn, the timing of starting the inspection action is determined by the corresponding loop. That is, in each state Sn, the inspection action start loop N(Sn) is set. For example, in the case of state S10, if data retention degradation is not assumed, then as... Figure 25 As shown, the loop N(S10) for starting the inspection action at the moment when the inspection action begins in state S10 is 16. If we do not assume data storage degradation, then as... Figure 26As shown, before the 15th cycle, it is useless to perform the verify operation for state S10. By performing the verify operation for state S10 starting from a predetermined cycle N(Sn), useless verify operations can be suppressed, and a desired threshold voltage distribution for state S10 can be obtained.

[0252] In Figure 25 , the verify operation start cycle N(S10) at which the verify operation for state S10 starts is 16. That is, before the 15th cycle (when the loop count Lc represents the current cycle, if Lc is less than N(S10)), the verify operation for state S10 is not performed. In Figure 26 , d1 represents a threshold voltage distribution at level B, and d2 represents a threshold voltage distribution before the 15th cycle.

[0253] The threshold voltage distribution of state S10 is generated from the threshold voltage distribution of level B. The threshold voltage distribution of each memory cell MT changes in such a way that as the cycle progresses (as the loop count Lc increases), the threshold voltage gradually increases.

[0254] Figure 27 is a diagram showing changes in the read voltage applied to a selected word line during a verify operation in the 15th cycle (Lc=15) and the 16th cycle (Lc=16). According to Figure 25 the graph, in the 15th cycle (Lc=15), verify operations for states S5 to S9 are performed. Similarly, in the 16th cycle (Lc=16), verify operations for states S5 to S10 are performed.

[0255] For example, in Figure 26 , when the threshold voltage distribution of state S10 shown as d4 is generated from the threshold voltage distribution of level B shown as d1, the threshold voltage distribution d2 generated by program operations before the 15th cycle (Lc < N(S10)) does not reach the verify voltage Vr10 shown by the dotted line (the verify voltage used for state S10). On the other hand, the threshold voltage distribution d3 generated by the program operation of the 16th cycle (Lc = N(S10)) reaches the vicinity of the verify voltage Vr10 shown by the dotted line. Therefore, assuming that the threshold voltage distribution changes as shown in Figure 26 , the verify operation for state S10 is not needed before the 15th cycle, and the verify operation for state S10 is performed after the 15th cycle, whereby useless verify operations can be omitted, and the desired distribution d4 can be obtained as the threshold voltage distribution of state S10.

[0256] That is, if the loop count Lc representing the current cycle reaches N(Sn) (in Figure 26In the example, N(S10) = 16), then the check action begins in the state Sn. If we assume an ideal state, then in the loop before the check action begins looping N(Sn), as follows... Figure 26 The test voltage (Vr10 shown by the dashed line) for the point d2 indicates that the target state has not been reached. Figure 26 As shown in d3, this represents the state of the test voltage, which is close to the target state, during a portion of the test operation in cycle N(Sn). This is achieved by... Figure 26 The state shown in d3 begins the inspection action, and useless inspection actions can be omitted, and as... Figure 26 As shown in d4, a narrower distribution is generated as the threshold voltage distribution for each state.

[0257] However, there are cases where the threshold voltage distribution (e.g., level B) shifts to a lower voltage side after an MLC write operation is performed.

[0258] Figure 28 This is a graph showing the change in threshold voltage distribution for each cycle caused by data retention degradation after the MLC write operation ends. (Example) Figure 28 As shown, when the threshold voltage distribution of level B changes from the position shown by the dashed line to the position shown by the solid line, for example, the threshold voltage distribution d3 generated by the program actions before loop 15 does not reach the test voltage (Vr10) corresponding to the target state (S10), until the threshold voltage distribution da obtained by the program actions of loop 16+M reaches near the test voltage (Vr10) corresponding to the target state (S10). In this case, the test action performed before loop 16+M is useless, and the time of the entire write operation only increases by the time t1 of the Mth test action.

[0259] In other words, if the threshold voltage distribution of MLC data shifts to a lower voltage side, and the test action is executed repeatedly starting from the test action that assumes data storage degradation without any assumptions, then useless test actions will occur.

[0260] On the other hand, if we simply assume that the threshold voltage distribution shifts to the lower voltage side and set the test action to start loop N(Sn), then overprogramming may occur if the impact of data preservation degradation is small.

[0261] Figure 29This is a graph illustrating the change in the threshold voltage distribution in each cycle under the simple assumption that the threshold voltage distribution shifts towards a lower voltage side and that the test action start loop N(Sn) is set to a larger value. For example, consider an example where the test action start loop N(S10) is not 16, but is set to a larger value of 17, as opposed to state S10 without assuming data retention degradation. Here, it is assumed that the shift of the threshold voltage distribution towards a lower voltage side due to data retention degradation is less than assumed, such as... Figure 29 As shown, the threshold voltage distribution d2 generated by the program action of loop 16 (the original check action starts loop N (S10)) approaches the check voltage (Vr10). Furthermore, a portion of the threshold voltage distribution d3 generated by the program action of loop 17 (the check action is set to a larger value starts loop N (S10)) exceeds the check voltage (Vr10). Each memory cell MT becomes the target of the program action even if the threshold voltage exceeds the check voltage, if it was not set to a write-prohibited state by the check action before the program action. As a result, concerns arise that... Figure 29 As shown in d4, a wide distribution is generated as the threshold voltage distribution for each state. It is assumed that if the threshold voltage distribution reaches the test voltage of a higher state (or, if the number of memory cells MT in the memory cell group MG that reach the test voltage of a higher state increases, and the ECC circuit 14 of the memory controller 1 cannot perform error correction), it becomes overprogramming.

[0262] Therefore, in this embodiment, the check operation for each state Sn is adjusted and loop N(Sn) is started based on the deviation dv of the threshold voltage distribution after the MLC write operation is performed.

[0263] Specifically, during the QLC write operation, the threshold voltage distribution of the data written via MLC is tracked (Vth) to detect the optimal read voltage. The difference between the detected optimal read voltage and the initially assumed read voltage is then calculated. Figure 22 The deviation amount (dv) is used to change the start cycle of the inspection action for the required state. For example, based on the deviation amount (dv) of the threshold voltage distribution of level B, the start cycle of the inspection action for states S6, S7, S10, and S11 is set to only a specific amount, and the start of the inspection action is delayed. That is, when the valley position is lower than the read voltage preset for reading the MLC written data, the sequence generator 25 changes the start cycle of the inspection action by delaying the start of the inspection action.

[0264] As mentioned above, because MLC readout is performed based on the optimal readout voltage at the valley position between levels, the reliability of reading MLC write data during QLC write operations is improved. Furthermore, because the check operation for each state Sn is changed according to the deviation dv from the normal readout voltage, the loop N(Sn) can be cyclically changed, thus eliminating unnecessary check operations and reducing the write time TPROG.

[0265] Figure 30 This is a diagram representing the instruction sequence for a QLC write operation.

[0266] When performing a QLC write operation, the sequence generator 25 receives the QLC write command.

[0267] In addition, the sequence generator 25 receives the address and data associated with the received QLC write command.

[0268] After receiving the data, the sequence generator 25 performs the valley position exploration process VS on the select word line WLn. That is, it calculates the optimal readout voltage for the MLC data.

[0269] Next, the sequence generator 25 uses the optimal read voltage to perform the read process (also known as the write target cell read process SDR1) for the MLC write data of each memory cell MT on the select word line WLn. In the write target cell read process SDR1, two reads are also performed: the read of the lower-level page and the read of the intermediate-level page.

[0270] As described above, if the sequence generator 25 receives a QLC write command during a QLC write operation, it executes valley location exploration processing (VS) to explore valley locations and data readout processing (SDR1) to read the data written via MLC write. In the write object cell readout processing (SDR1), the data written via MLC write operation is read out based on the explored valley locations.

[0271] Furthermore, the sequence generator 25 performs a QLC write operation. During the QLC write operation, the verification operation of each state is adjusted and loop N(Sn) is started based on the deviation dv of the read voltage of each level.

[0272] Specifically, sequence generator 25 causes at least a portion of the inspection actions in states S1 to S15 to begin cyclic delay, so as to avoid performing the useless inspection actions or reduce the number of useless inspection actions.

[0273] Figure 31This is a diagram illustrating the relationship between the write operation cycle and the state that becomes the object of the verification operation in this embodiment. If the verification operation start cycle is set to only a specific amount, then the verification operation for the state that becomes the object is omitted from the cycle starting from the preset verification operation start to the cycle starting from the newly set verification operation start. Figure 31 In the diagram, the dotted circular mark indicates an omitted inspection action.

[0274] Figure 32 This is a flowchart of a QLC write operation. Lc represents the loop count value corresponding to the loop being executed. For example, in the first loop, Lc is 1. Furthermore, in this flowchart, the loop count value Lc is set to 0 before the QLC write operation is performed.

[0275] Sequence generator 25 increments the loop count value Lc by 1 and applies a specific program pulse to the select word line WL (step S101). Hereinafter, "step" is also referred to as "s". For example, "step 101" is also referred to as "s101".

[0276] The sequence generator 25 determines whether the program for each state Sn, which is the object of the inspection action in the loop, has ended (s102). n is any one of 1 to 15. For example, in loop 1, state S1 is the object of the inspection action; in loop 3, states S1 and S2 are the objects of the inspection action; and in loop 20, states S8, S9, S10, S11, and S12 are the objects of the inspection action.

[0277] When the program related to each state Sn, which is the object of the test action in the loop, ends (s102: YES), the sequence generator 25 determines whether the program of state S15 has ended (i.e., n=15?) (s103).

[0278] When the program reaches state S15 (s103; Yes), sequence generator 25 terminates. Figure 32 The processing.

[0279] If the program has not ended by state S15 (s103; No), sequence generator 25 increments n by 1 (s108) and then executes the processing of s102.

[0280] If the program related to each state Sn, which is the object of the inspection action in the loop, has not ended (s102: No), the sequence generator 25 determines whether the loop count value Lc (the loop being executed) is above the start loop N(Sn) of the inspection action for each state Sn (s105). That is, in the loop, it is determined whether the inspection action for state Sn needs to be executed.

[0281] If the loop count value Lc (the loop in progress) is not the start loop N(Sn) of the check action for each state Sn (s105: No), the sequence generator 25 increments the loop count value Lc by 1 (s104). After s104, the sequence generator 25 outputs a specific program pulse to the selection word line WL to execute the program action of the next loop (s101).

[0282] When the loop count value Lc (the loop in progress) is above the loop N(Sn) of the check action start for state Sn (s105: Yes), the sequence generator 25 performs the check action on the state Sn (s106).

[0283] After s106, sequence generator 25 determines whether the check action of state S15 has been executed (i.e., n=15?) (s107).

[0284] While the verification action in state S15 has been executed (s107: Yes), sequence generator 25 executes s104. At this time, n is initialized in S104.

[0285] If the check action in state S15 has not been performed (s107: no), sequence generator 25 increments n by 1 (s108), and then performs the processing of s102.

[0286] Figure 33 This is a graph showing the relationship between the cycle and the test action, which is the result of adjusting the test action cycle N(Sn) based on the deviation dv of the read voltage of each level read using Vth tracking.

[0287] exist Figure 33 In the diagram, the state where shading is applied indicates the start loop N(Sn) of the change check action. For example, the start loop N(S4) of the check action in state S4 omits only the offset 2dL. That is, the check action of state S4 is not executed in loops 5 and 6. Similarly, the start loop N(S10) of the check action in state S10 omits only the offset dL. In addition, the start loops N(S12) to N(S15) of the check actions in states S12 to S15 omits only the offset dL.

[0288] As described above, according to this embodiment, since it is possible to suppress the execution of useless testing actions, it is possible to avoid adverse effects on the threshold voltage distribution and reduce the time required to write data.

[0289] In particular, because the information of the valley position detected by the Vth trace of the MLC data is obtained before the QLC write operation, and the start loop of the verification operation is determined, the verification operation can be performed in the most useful and optimal number of times.

[0290] Furthermore, in each of the embodiments described, while the non-volatile memory 2 is a NAND memory capable of storing 4 bits of QLC per memory cell, the non-volatile memory 2 can also be a 2-bit / cell, 3-bit / cell, or 5-bit / cell NAND memory. Additionally, it can be written in a manner that involves writing multiple values ​​of data through three or more write operations. For example, in the case of a 3-bit / cell NAND memory, it can be written in the first write operation with 1 bit of data and in the second write operation with the remaining 2 bits of data. For example, in the case of a 5-bit / cell NAND memory, it can be written in the first write operation with 2 bits of data and in the second write operation with the remaining 3 bits of data, or it can be written in the first write operation with 3 bits of data and in the second write operation with the remaining 2 bits of data. Furthermore, for example, in the case of a 5-bit / cell NAND memory, it can be written in the first write operation with 1 bit of data, in the second write operation with the other 2 bits of data, and in the third write operation with the remaining 2 bits of data.

[0291] While several embodiments of the present invention have been described, these embodiments are illustrative by way of example and are not intended to limit the scope of the invention. The novel embodiments may be implemented in various other ways, with various omissions, substitutions, and modifications made without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0292] [Explanation of Symbols]

[0293] 1: Memory controller

[0294] 2: Non-volatile memory

[0295] 12: Processor

[0296] 13: Host Interface

[0297] 14: ECC circuit

[0298] 15: Memory Interface

[0299] 16: Internal Bus

[0300] 21: Memory Cell Array

[0301] 22: Input / output circuit

[0302] 23: Logic control circuit

[0303] 24: Registers

[0304] 25: Sequence Generator

[0305] 26: Voltage generation circuit

[0306] 27: Line decoder

[0307] 28: Sensing Amplifier

[0308] 29: Input / output pad group

[0309] 30: Logic control pad group

[0310] 31: Power input terminal group

[0311] 40-48: Transistors

[0312] 49: Capacitor

[0313] 50, 51: Inverters

[0314] 52, 53: Transistors

[0315] 331, 332, 333: Wiring layer

[0316] 334: Memory Hole

[0317] 335: Block insulating film

[0318] 336: Charge storage membrane

[0319] 337: Gate insulating film

[0320] 338: Conductor column

[0321] 339, 340: Contact plugs.

Claims

1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells each capable of storing n-bit data, n being an integer of 2 or greater; and a control circuit capable of executing a first write operation of writing p-bit data, p<n, among the n bits into each memory cell, and a second write operation of writing the n-bit data into each said memory cell after said first write operation, wherein in said second write operation, said control circuit executes a program operation of writing the n-bit data and a verify operation of verifying the n-bit data written by said program operation; and said control circuit reads at least one first data stored in at least one second memory cell adjacent to a first memory cell, and sets a plurality of verify voltage levels for said verify operation of said first memory cell used in said second write operation based on the read said first data and second data written into said first memory cell through said first write operation.

2. The semiconductor memory device according to claim 1, wherein said control circuit sets said plurality of verify voltage levels according to said first data.

3. The semiconductor memory device according to claim 2, wherein in said second write operation, said control circuit sets said plurality of verify voltage levels to be stepwise increased according to said first data.

4. The semiconductor memory device according to claim 1, wherein if said control circuit receives a write instruction for the n-bit data in said second write operation, it executes a first read processing of reading said first data and a second read processing of reading said second data.

5. The semiconductor memory device according to claim 1, comprising at least one first latch circuit for storing said at least one first data.

6. The semiconductor memory device according to claim 5, wherein said at least one first latch circuit comprises two said first latch circuits for use with two memory cells adjacent to said first memory cell.

7. The semiconductor memory device according to claim 5, comprising a second latch circuit that stores said second data.

8. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells each capable of storing n-bit data, n being an integer of 2 or greater; and a control circuit capable of executing a first write operation of writing p-bit data, p<n, among the n bits into each memory cell, and a second write operation of writing the n-bit data into each said memory cell after said first write operation, wherein in said second write operation, said control circuit executes a program operation of writing the n-bit data and a verify operation of verifying the n-bit data written by said program operation; and said control circuit searches for a valley position between two threshold voltage distributions corresponding to data written through said first write operation, and changes a verify operation start cycle used for said verify operation based on a voltage at the searched said valley position.

9. The semiconductor memory device of claim 8, wherein the control circuit changes the start-cycle of the inspection operation based on the difference between the voltage at the valley position and a readout voltage preset for reading the data.

10. The semiconductor memory device of claim 9, wherein the control circuit, when the valley position is lower than the preset readout voltage for reading the data, changes the start cycle of the verification operation by delaying the start of the verification operation.

11. The semiconductor memory device of claim 9, wherein if the control circuit receives a write instruction for the n-bit data during the second write operation, it performs valley location exploration processing to explore the valley location and data readout processing to read the p-bit data written through the first write operation.

12. The semiconductor memory device of claim 11, wherein the data readout processing is based on the discovered valley location, and the p-bit data written by the first write operation is read out.

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