Semiconductor system and method for detecting wiring defects

Abstract

Embodiments provide a semiconductor system and a method of detecting a wiring defect, by which a cause of a defect in a signal can be easily and accurately detected without separating a package of the semiconductor system. A semiconductor system includes a first semiconductor chip, a second semiconductor chip stacked above the first semiconductor chip, a controller configured to control the first and second semiconductor chips, a first wiring connected between the controller and each of the first and second semiconductor chips through which a first signal is to be transmitted from the controller to each of the first and second semiconductor chips, a second wiring connected between the controller and the first semiconductor chip through which a current of the first signal flowing through the first wiring to the first semiconductor chip is to be returned to the controller, and a third wiring connected between the controller and the second semiconductor chip through which a current of the first signal flowing through the first wiring to the second semiconductor chip is to be returned to the controller.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-144898, filed September 6, 2021, and U.S. Patent Application No. 17 / 679857, filed February 24, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to semiconductor systems and methods for detecting wiring defects. Background Technology

[0004] Stacking technology, in which semiconductor chips are stacked, interconnected, and packaged using bonding wires, has become widely used. In cases where defects are detected in signals transmitted from a controller via bonding wires, there is a need to easily and accurately detect these defects without disassembling the package. Summary of the Invention

[0005] The embodiment provides a semiconductor system and a wiring defect detection method. The method enables easy and accurate detection of the cause of defects in signals without disassembling the semiconductor system package.

[0006] Generally, according to one embodiment, a semiconductor system includes: a first semiconductor chip; a second semiconductor chip stacked on top of the first semiconductor chip; a controller configured to control the first and second semiconductor chips; a first wiring connection connected between the controller and each of the first and second semiconductor chips, through which a first signal is to be transmitted from the controller to each of the first and second semiconductor chips; a second wiring connection connected between the controller and the first semiconductor chip, through which current flowing through the first wiring to the first semiconductor chip of the first signal is to be returned to the controller; and a third wiring connection connected between the controller and the second semiconductor chip, through which current flowing through the first wiring to the second semiconductor chip of the first signal is to be returned to the controller. Attached Figure Description

[0007] Figure 1 This is a schematic plan view illustrating the main components of a semiconductor system according to the first embodiment.

[0008] Figure 2 This is a schematic plan view illustrating the main components of a semiconductor system according to the second embodiment.

[0009] Figure 3This is a block diagram illustrating the outline of a memory system, which is a specific example of a semiconductor system according to the first and second embodiments.

[0010] Figure 4 This is a circuit diagram illustrating an example of a NAND flash memory cell array with a three-dimensional structure. Detailed Implementation

[0011] In the following description, embodiments of the semiconductor system and wiring defect detection method will be illustrated with reference to the accompanying drawings. While the description will focus on the main components of the semiconductor system, the semiconductor system may have components or functions not described herein. The description herein is not intended to exclude components or functions not described herein.

[0012] (First Embodiment)

[0013] Figure 1 This is a schematic plan view illustrating the main components of the semiconductor system 1 according to the first embodiment. Figure 1 The semiconductor system 1 has multiple stacked semiconductor chips 2 and a controller 3 that controls the multiple semiconductor chips 2.

[0014] Each of the plurality of semiconductor chips 2 is an unpackaged bare chip. Semiconductor chip 2 can be of any type. For example, semiconductor chip 2 can be a flash memory chip.

[0015] Each of the multiple stacked semiconductor chips 2 has multiple pads P1 and P2. Figure 1 In this context, it is assumed that multiple semiconductor chips 2 have the same function, and the position, size, and number of pads P1 and P2 disposed on each semiconductor chip 2 are common to all semiconductor chips 2. Each semiconductor chip 2 transmits signals to / receives signals from the controller 3 via pads P1 and P2 and bonding lines W1 and W2. As described later, each semiconductor chip 2 includes two types of pads P1 and P2. Regarding the number of pads, each semiconductor chip 2 has one pad P1 and one or more pads P2. Figure 1 This indicates that each semiconductor chip 2 has multiple instances of pads P2.

[0016] Each semiconductor chip 2 has multiple pads P2, including pads for receiving signals from the controller 3, pads for transmitting signals to the controller 3, pads for bidirectional transmission of signals to / from the controller 3, and pads for supplying power. Additionally, a pad P1, individually disposed on each semiconductor chip 2, is a pad for detecting defects, as described later.

[0017] like Figure 1The description states that multiple semiconductor chips 2 are stacked on a support substrate (not shown) and slightly shifted simultaneously. This shifting is to facilitate the connection of bonding lines W1 and W2 to pads P1 and P2 on each semiconductor chip 2. When bonding lines W1 and W2 are connected to pads P1 and P2 on each of the multiple semiconductor chips 2, as the number of stacked semiconductor chips 2 increases, it becomes difficult to ensure sufficient space for arranging bonding lines W1 and W2. Therefore, in some embodiments, pads of the same type on the multiple stacked semiconductor chips 2 are bonded to each other in the stacking direction using through-silicon vias (TSVs), bumps, Cu-Cu connections, or the like, and bonding lines W1 are connected to the pads of any semiconductor chip 2 to transmit signals to / receive signals from the controller 3. Therefore, without increasing the number of bonding lines W1, signals can be transmitted / received between the controller 3 and the multiple semiconductor chips 2. Thus, the number of stacked semiconductor chips 2 can be increased as needed.

[0018] exist Figure 1 In this configuration, corresponding pads P1 (or P2) of multiple stacked semiconductor chips 2 are electrically connected to each other via wires. However, the diagonal lines are schematic and are actually implemented using, for example, vias, Cu-Cu connections, wiring patterns, and combinations thereof.

[0019] Although Figure 1 This indicates an instance where each semiconductor chip 2 contains three pads P2. However, the number of pads P2, the arrangement of pads P1 and P2, and the type of signals transmitted / received through pads P2 are arbitrary. For example, when semiconductor chip 2 is a flash memory chip, all pads, except for those related to power, essentially transmit signals to / receive signals from controller 3. Typical pads in a flash memory chip include pads for the chip enable signal CEn, pads for the write enable signal WEn, pads for the read enable signal REn, pads for the address latch enable signal ALE, pads for the command latch enable signal CLE, and others. The chip enable signal CEn is used to enable the flash memory chip. The write enable signal WEn is used to specify the timing for writing data to the flash memory chip. The read enable signal REn is used to specify the timing for reading data from the flash memory chip. The address latch enable signal ALE is used to indicate that signal DQ is an address. The command latch enable signal CLE is used to indicate that signal DQ is a command.

[0020] As described above, the number and type of pads P2 disposed on each of the multiple stacked semiconductor chips 2 are arbitrary, and the pads P2 on any of the multiple semiconductor chips 2 and the controller 3 are connected to each other via bonding wires W1. For example, multiple pads P2 disposed on the uppermost semiconductor chip 2 can be connected to the controller 3 respectively via bonding wires W1. Additionally, as... Figure 1 The text explains that, since multiple semiconductor chips 2 are stacked and simultaneously shifted, the semiconductor chip 2 connected to the pad P2 by the bonding line W1 may not necessarily be the semiconductor chip placed on the top layer.

[0021] In the description herein, the bonding line W1 used for transmitting signals between each of the plurality of semiconductor chips 2 and the controller 3 will be referred to as the first bonding line W1, and the bonding line W2 used for connecting the controller 3 to each of the semiconductor chips 2 to detect defects in the first bonding line W1 will be referred to as the second bonding line W2. The number of first bonding lines W1 is equal to the number of various types of pads P2 disposed on each of the plurality of stacked semiconductor chips 2. The number of second bonding lines W2 is equal to the number of stacked semiconductor chips 2.

[0022] Furthermore, in the description herein, a pad P1 connected to each of the plurality of second wirings W2 on the semiconductor chip 2 may be referred to as the first pad P1, and a pad P2 electrically connected to the first wiring W1 may be referred to as the second pad P2. While the second pad P2 is a conventional pad disposed on the semiconductor chip 2, the first pad P1 is a non-conventional pad provided for defect detection. The first pad P1 is provided for each semiconductor chip 2 and connected to the corresponding second wiring W2. One or more second pads P2 are disposed on each semiconductor chip 2, and the first wiring W1 is connected to the second pad P2 of any of the semiconductor chips 2.

[0023] As described above, for the minimum configuration, in addition to the plurality of semiconductor chips 2 and controller 3 described above, the semiconductor system 1 according to this embodiment includes at least one first wiring W1 and a plurality of second wirings W2. The first wiring W1 is a wiring (connection wire) for transmitting signals between the controller 3 and the plurality of semiconductor chips 2. The plurality of second wirings W2 are wirings (connection wires) for connecting the controller 3 and the first pads P1 of the plurality of semiconductor chips 2 to each other, and when defect detection is performed, the current flowing through the first wiring W1 to the controller 3 is returned.

[0024] The controller 3 includes a switch SW that selects one of a plurality of second wirings W2. Based on the current flowing through the second wiring W2 selected by the switch SW, the controller 3 detects a defect in the first wiring W1 connected to the second wiring W2. More precisely, a defect in the first wiring W1 refers to a defect in the signal path from the end of the first wiring W1 at the controller 3 side to the second pad P2 of each semiconductor chip 2. Typical examples of defects are short circuits or disconnections.

[0025] As described later, in this embodiment, when the controller 3 sends a signal to the second pad P2 of each semiconductor chip 2 via the first wiring W1, the current corresponding to the signal returns from the first pad P1 to the controller 3 via the second wiring W2. When each semiconductor chip 2 has multiple second pads P2, the controller 3 can select any second pad P2 based on the input signal to the controller 3 or the address signal used to select any first wiring W1 after the first mode, which will be described later, is selected, and can detect defects in the first wiring W1 connected to the selected second pad P2.

[0026] Because a second wiring W2 is provided separately for each semiconductor chip 2, the controller 3 can identify the semiconductor chip 2 with a signal path in which a defect occurs from the current returned through the second wiring W2.

[0027] The controller 3 can control multiple stacked semiconductor chips 2 by switching between a first mode and a second mode. The first mode is used to detect defects in the first wiring W1 used for signal transmission. When the first mode is selected, the controller 3 detects the current returning through multiple second wirings W2 and detects whether a defect has occurred in the signal path of the multiple corresponding semiconductor chips 2 based on the detected current. More specifically, in the first mode, the controller 3 detects the current flowing from the first wiring W1 to the corresponding second wiring W2 via the first pad P1 corresponding to any second pad P2.

[0028] When the second mode is selected, the signal path from the first terminal W1 to the plurality of second terminals W2 is interrupted. Therefore, the controller 3 transmits signals to / from each semiconductor chip 2 via the first terminal W1 to enable each semiconductor chip 2 to perform normal operation.

[0029] As described above, one end of each first wire W1 is connected to the controller 3, and the other end is connected to the second pad P2 of any of the semiconductor chips 2. The plurality of second pads P2 disposed on each of the plurality of semiconductor chips 2 are electrically connected to each other. During defect detection, the current flowing from the first wire W1 to each of the plurality of second pads P2 flows through the corresponding first pad P1 to the corresponding second wire W2.

[0030] like Figure 1The description states that each of the plurality of semiconductor chips 2 has a rectifier circuit 4 disposed between a first pad P1 and a second pad P2. When the voltage level of the first terminal W1 is less than a predetermined threshold, the rectifier circuit 4 cuts off the signal path in which current flows from the second pad P2 to the first pad P1, and when the voltage level of the first terminal W1 is equal to or higher than the threshold, the rectifier circuit 4 allows current to flow from the second pad P2 to the first pad P1 in the signal path. The predetermined threshold is, for example, a voltage higher than the power supply voltage of the semiconductor chip 2. Therefore, when the controller 3 sets the voltage level of the first terminal W1 to be less than the predetermined threshold (the second mode described above), current does not flow from the first terminal W1 to the first pad P1 through the second pad P2, and therefore, it does not flow in the second terminal W2, so that the controller 3 does not need to monitor the current in the second terminal W2. Meanwhile, in the first mode, the controller 3 intentionally sets the voltage level of the first terminal W1 to be equal to or higher than the predetermined threshold, so that current flows from the first terminal W1 to the second terminal W2 through the second pad P2 and the first pad P1.

[0031] As described above, in the first mode, the voltage level of the first terminal W1 needs to be set to a predetermined threshold or higher. Therefore, for example, a boost circuit (not shown) may be provided inside the controller 3 to supply the voltage obtained by boosting the power voltage of the controller 3 using the boost circuit to the first terminal W1 during the first mode. Alternatively, the voltage for the first mode may be pre-input into the controller 3, and the input voltage for the first mode may be supplied to the first terminal W1 during the first mode.

[0032] By providing the rectifier circuit 4 in this way, current can flow from the first terminal W1 to the second terminal W2 only when the controller 3 increases the voltage level of the first terminal W1. Therefore, by monitoring the current in the second terminal W2, the controller 3 can perform defect detection on the first terminal W1, whose voltage level has been increased.

[0033] The rectifier circuit 4 has a plurality of first diodes D1 connected in series, aligning their rectification direction. The anodes of the first diodes D1 are connected to a second pad P2 at one end of the plurality of first diodes D1 connected to the first pad P1. The cathodes of the first diodes D1 are connected to a first pad P1 at the other end of the plurality of first diodes D1 connected to the first pad P1. Because the forward voltage of a normal diode is about 0.6V, the number of diodes connected in series is set to, for example, 4 when the power voltage of the semiconductor chip 2 is, for example, about 1.8V. Therefore, the predetermined threshold is set to about 2.4V, and when the voltage level of the first terminal W1 is 2.4V or more, current is allowed to flow through diode D1 from the first terminal W1 to the second terminal W2.

[0034] An example in which current flows from the first terminal W1 to the second terminal W2 through the rectifier circuit 4 has been described. However, depending on the type of defect, the defect may not be correctly detected by simply monitoring the current in the second terminal W2, but rather by allowing the current to flow back from the second terminal W2 to the first terminal W1 through the rectifier circuit 4. Therefore, when the voltage level of the plurality of second terminals W2 is less than a predetermined threshold, the rectifier circuit 4 cuts off the signal path in which current flows from the plurality of first pads P1 to the corresponding second pad P2. When the voltage level of at least one of the plurality of second terminals W2 is equal to or higher than the threshold, the rectifier circuit 4 allows current to flow in the signal path from at least one of the plurality of first pads P1 to the corresponding second pad P2. In this case, the rectifier circuit 4 has a plurality of second diodes D2 connected in series in the opposite direction to the plurality of first diodes D1. The cathodes of the second diodes D2 are connected to the second pad P2 at one end of the plurality of second diodes D2 connected to the second diodes D2. The anodes of the second diodes D2 are connected to the first pad P1 at the other end of the plurality of second diodes D2 connected to the second diodes D2.

[0035] like Figure 1 The description states that each semiconductor chip 2 has multiple types of second pads P2 for transmitting signals relative to the controller 3. In this case, multiple first terminals W1 are arranged between the controller 3 and the multiple semiconductor chips 2 to be electrically connected to the multiple types of second pads P2. During defect detection, the controller 3 detects the current flowing from each first terminal W1 to the corresponding second terminal W2 through the corresponding second pad P2 and the corresponding first pad P1. A rectifier circuit 4 is individually connected to each of the multiple first terminals W1. When the voltage level of the second terminal W2 is less than a predetermined threshold, each rectifier circuit 4 cuts off the signal path in which current flows from the corresponding second pad P2 to the first pad P1. When the voltage level of the second terminal W2 is equal to or higher than the threshold, each rectifier circuit 4 allows current to flow from the corresponding second pad P2 to the corresponding first pad P1 in the signal path. Furthermore, when the voltage level of the multiple second terminals W2 is less than the predetermined threshold, each rectifier circuit 4 cuts off the signal path in which current flows from each of the multiple first pads P1 to the corresponding second pad P2. When the voltage level of at least one of the plurality of second terminals W2 is equal to or higher than a threshold, each rectifier circuit 4 may allow current to flow in the signal path from at least one of the plurality of first pads P1 to the corresponding second pad P2.

[0036] Stacking technology, in which semiconductor chips are stacked, interconnected, and packaged together via bonding wires, has become widely used. In cases where a large number of semiconductor chips are stacked, the number of wires in the package becomes excessive when bonding wires are connected to the pads of each stacked semiconductor chip. Therefore, for the same type of signal, the pads of multiple semiconductor chips can be interconnected in the stacking direction, and the bonding wires can be connected only to the pads of representative semiconductor chips, thereby reducing the number of wires. In this case, when a defect is detected in the signal transmitted from the controller to the bonding wires, it is difficult to identify the location of the defect from outside the package.

[0037] For the minimum configuration, Figure 1 The semiconductor system 1 described herein may include a controller 3 and two semiconductor chips 2. In the following description, the two semiconductor chips 2 will be referred to as a first semiconductor chip 2a and a second semiconductor chip 2b. For example, each of the first semiconductor chip 2a and the second semiconductor chip 2b has a first pad P1 and two second pads P2. In the following description herein, the two second pads P2 in the first semiconductor chip 2a will be referred to as third pads P2a and fifth pads P2c, and the two second pads P2 in the second semiconductor chip 2b will be referred to as fourth pads P2b and sixth pads P2d.

[0038] As described above, the controller 3 and each semiconductor chip 2 perform signal transmission via the first wiring W1. In the following description, the first wiring W1 used to transmit a first signal between the controller 3 and the third pad P2a in the first semiconductor chip 2a / the fourth pad P2b in the second semiconductor chip 2b will be referred to as the first wiring W1a, and the first wiring W1 used to transmit a second signal different from the first signal between the controller 3 and the fifth pad P2c in the first semiconductor chip 2a / the sixth pad P2d in the second semiconductor chip 2b will be referred to as the fourth wiring W1b.

[0039] As described above, Figure 1 Each semiconductor chip 2 in the semiconductor system 1 described herein has a first pad P1 and a second wiring W2. In the following text, the first pad P1 in the first semiconductor chip 2a will be referred to as the first pad P1a, and the second wiring W2 connected to the first pad P1a will be referred to as the second wiring W2a. Furthermore, the first pad P1 in the second semiconductor chip 2b will be referred to as the second pad P1b, and the second wiring W2 connected to the second pad P1b will be referred to as the third wiring W2b.

[0040] As described above, Figure 1Each semiconductor chip 2 in the semiconductor system described herein has a rectifier circuit 4. In the following text, the rectifier circuit 4 disposed between the first pad P1a and the third pad P2a in the first semiconductor chip 2a will be referred to as the first rectifier circuit 4a, and the rectifier circuit 4 disposed between the second pad P1b and the fourth pad P2b in the second semiconductor chip 2b will be referred to as the second rectifier circuit 4b. Furthermore, the rectifier circuit 4 disposed between the first pad P1a and the fifth pad P2c in the first semiconductor chip 2a will be referred to as the third rectifier circuit 4c, and the rectifier circuit 4 disposed between the second pad P1b and the sixth pad P2d in the second semiconductor chip 2b will be referred to as the fourth rectifier circuit 4d.

[0041] As described above, Figure 1 The rectifier circuit 4 has multiple diodes D1 and multiple diodes D2, which are oriented differently from each other. In the following text, the multiple diodes D1 in the first rectifier circuit 4a will be referred to as multiple first diodes D1a, and the multiple diodes D1 in the second rectifier circuit 4b will be referred to as multiple second diodes D1b. Furthermore, in the following text, the multiple diodes D2 in the first rectifier circuit 4a will be referred to as multiple third diodes D2a, and the multiple diodes D2 in the second rectifier circuit 4b will be referred to as multiple fourth diodes D2b.

[0042] As described above, the first semiconductor chip 2a includes a first pad P1a, a third pad P2a, a fifth pad P2c, a first rectifier circuit 4a having multiple first diodes D1a and multiple third diodes D2a, and a third rectifier circuit 4c having the same configuration as the first rectifier circuit 4a. The second semiconductor chip 2b includes a second pad P1b, a fourth pad P2b, a sixth pad P2d, a second rectifier circuit 4b having multiple second diodes D1b and multiple fourth diodes D2b, and a fourth rectifier circuit 4d having the same configuration as the second rectifier circuit 4b. The controller 3 transmits a first signal to the first semiconductor chip 2a and the second semiconductor chip 2b via a first connection W1a. The first semiconductor chip 2a returns the current flowing in the first connection W1a to the controller 3 via a second connection W2a. The second semiconductor chip 2b returns the current flowing in the first connection W1a to the controller 3 via a third connection W2b. Furthermore, the controller 3 transmits a second signal to the first semiconductor chip 2a and the second semiconductor chip 2b via a fourth connection W1b. The first semiconductor chip 2a returns the current flowing in the fourth terminal W1b to the controller 3 via the second terminal W2a. The second semiconductor chip 2b returns the current flowing in the fourth terminal W1b to the controller 3 via the third terminal W2b.

[0043] In the semiconductor system 1 according to the first embodiment, in order to detect defects in the first wiring W1 used for transmitting signals between a plurality of stacked semiconductor chips 2 and a controller 3, a second wiring W2 is provided for connecting the first pad P1 of each semiconductor chip and the controller 3 to each other. Then, the current corresponding to the signal sent from the controller 3 to the first wiring W1 returns from each second wiring W2 to the controller 3. Therefore, defects such as short circuits or disconnections in the signal path from the end of the first wiring W1 at the controller 3 side to the second pad P2 of each semiconductor chip 2 can be detected individually for each semiconductor chip 2. Therefore, according to this embodiment, the location of a defect in the wiring path between the plurality of stacked semiconductor chips 2 and the controller 3 can be easily and accurately identified.

[0044] Furthermore, in this embodiment, since multiple rectifier circuits 4 are disposed between the first terminal W1 and the multiple second terminals W2, current flows from the first terminal W1 to the second terminal W2 only when the controller 3 supplies a signal with a voltage level equal to or higher than a predetermined threshold to the first terminal W1. Therefore, by simply switching the voltage level of the first terminal W1 without providing a switching circuit for switching operating modes, switching can be implemented between a first mode for detecting defects in the first terminal W1 and a second mode for normal operation of the multiple semiconductor chips 2.

[0045] (Second Embodiment)

[0046] In the second embodiment, a switching circuit 5 is provided instead of... Figure 1 4. Rectifier circuit. Figure 2 This is a schematic plan view illustrating the main components of the semiconductor system 1a according to the second embodiment. Similar to... Figure 1 , Figure 2 The semiconductor system 1a has multiple stacked semiconductor chips 2 and a controller 3.

[0047] like Figure 2 The description states that each of the plurality of semiconductor chips 2 has a plurality of switching circuits 5, which switch whether various types of second pads P2 and first pads P1 are electrically connected to each other. The controller 3 selects one of the plurality of switching circuits 5 to make the corresponding second pads P2 and first pads P1 electrically connected to each other, thereby detecting the current flowing through the first pad P1.

[0048] Multiple switching circuits 5 switch between each other based on a switch control signal SC from the controller 3, indicating whether the corresponding second pad P2 and first pad P1 are electrically connected. Between the controller 3 and the multiple semiconductor chips 2, multiple first wirings W1 and multiple second wirings W2 are arranged as in the semiconductor system 1 of the first embodiment, and a third wiring W3 for the switch control signal SC is also provided. Since the switch control signal SC can perform switching control on all switching circuits 5, only one third wiring W3 is required. By switching the logic of the switch control signal SC, the controller 3 can switch between each other regarding whether the corresponding second pad P2 and first pad P1 are electrically connected. More specifically, the controller 3 can set the switch control signal SC to, for example, a high level, such that through each switching circuit 5, the corresponding second pad P2 and first pad P1 are electrically connected. In this case, the current corresponding to the signal connected to the first wiring W1 of the second pad P2 flows through the second pad P2 and the first pad P1 to the corresponding second wiring W2.

[0049] Since the controller 3 can individually control the voltage applied to the plurality of first terminals W1, defects such as disconnections or the like in each first terminal W1 can be detected individually. In the first embodiment, a signal having a voltage level equal to or higher than a predetermined threshold is supplied to the plurality of first terminals W1 in a first mode. However, in this embodiment, there is no difference in the voltage levels of the signals supplied to the plurality of first terminals W1 during the first and second modes. Therefore, control at the controller 3 side is facilitated.

[0050] The specific circuit configuration of the multiple switching circuits 5 is not limited to any specific configuration. Figure 2 An example has an NMOS transistor Q1 and a PMOS transistor Q2 connected in parallel between a first pad P1 and a second pad P2 and an inverter 6. A switch control signal SC is input to the inverter 6, and the output of the inverter 6 is input to the gate of the PMOS transistor Q2. A switch control signal SC is input to the gate of the NMOS transistor Q1.

[0051] For the minimum configuration, Figure 2 The semiconductor system 1a described herein may include a controller 3 and two semiconductor chips 2. In the following text, the two semiconductor chips 2 will be referred to as the first semiconductor chip 2a' and the second semiconductor chip 2b'. The following text will focus on... Figure 1 The differences between the first semiconductor chip 2a and the second semiconductor chip 2b are described.

[0052] The first semiconductor chip 2a' has a first switching circuit 5a and a second switching circuit 5b, rather than Figure 1The first semiconductor chip 2a contains a first rectifier circuit 4a and a third rectifier circuit 4c. Furthermore, the second semiconductor chip 2b' has a third switch circuit 5c and a fourth switch circuit 5d, instead of... Figure 1 The first semiconductor chip 2b contains a second rectifier circuit 4b and a fourth rectifier circuit 4d. A first switching circuit 5a switches whether the first pad P1a and the third pad P2a are electrically connected to each other. A second switching circuit 5b switches whether the first pad P1a and the fifth pad P2c are electrically connected to each other. A third switching circuit 5c switches whether the second pad P1b and the fourth pad P2b are electrically connected to each other. A fourth switching circuit 5d switches whether the second pad P1b and the sixth pad P2d are electrically connected to each other. The controller 3 puts the first switching circuit 5a into a conducting state to make the third pad P2a and the first pad P1a electrically connected to each other, thereby detecting the current flowing through the first pad P1a. The controller 3 puts the second switching circuit 5b into a conducting state to make the fifth pad P2c and the first pad P1a electrically connected to each other, thereby detecting the current flowing through the first pad P1a. Controller 3 activates the third switching circuit 5c to make the fourth pad P2b and the second pad P1b electrically connected to each other, thereby detecting the current flowing through the second pad P1b. Controller 3 also activates the fourth switching circuit 5d to make the sixth pad P2d and the second pad P1b electrically connected to each other, thereby detecting the current flowing through the second pad P1b.

[0053] As described above, in the second embodiment, a plurality of switching circuits 5 are disposed between a plurality of second pads P2 and first pads P1 electrically connected to a plurality of first wirings W1 arranged for signal transmission between the controller 3 and a plurality of semiconductor chips 2. The controller 3 selects one of the plurality of switching circuits 5 by means of a switch control signal SC and causes the current from the corresponding first wiring W1 to return to the second wiring W2 through the selected switching circuit 5.

[0054] In the second embodiment, since the switching circuit 5 switches whether the first pad P1 and the second pad P2 are electrically connected to each other, the voltage level of the multiple first wirings W1 does not need to rise to a higher level than the voltage level in the second mode during the first mode, so that the internal configuration and control of the controller 3 may not become complicated.

[0055] In addition, Figure 2 In this configuration, switching control for all switching circuits 5 is performed based on a common switching control signal SC output from the controller 3. However, individual switching control signals SC can be formed for each switching circuit 5. In this case, a number of third wirings W3, equal to the number of switching circuits 5, are arranged between the controller 3 and the plurality of semiconductor chips 2, and through each third wiring W3, a corresponding switching control signal SC is supplied to each semiconductor chip 2.

[0056] NAND flash memory chips can be used as multiple stacked semiconductor chips 2 in semiconductor systems 1 and 1a according to the first and second embodiments described above.

[0057] Figure 3 This is a block diagram illustrating the outline of a memory system 10, which is a specific instance of a semiconductor system 1 or 1a according to a first or second embodiment. Figure 3 The memory system 10 includes a NAND flash memory 100, a controller 200, and a host device 300. The NAND flash memory 100 is a stacked body in which multiple NAND flash memory chips are stacked.

[0058] Each of the plurality of flash memory chips comprising the NAND flash memory 100 has a memory cell array 110. Each memory cell in the memory cell array 110 stores data in a non-volatile manner. All the plurality of flash memory chips have the same internal configuration. Furthermore, each flash memory chip has a controller interface (I / F) circuitry 170. Figure 1 and 2 The description states that multiple second pads P2, rectifier circuit 4 or switching circuit 5, and first pad P1 are disposed in controller I / F circuit 170. Second wiring W2 and first pad P1 are provided for each flash memory chip. Furthermore, controller I / F circuit 170 can provide... Figure 2 The third pad P3, and the third wiring W3 can be provided for connection to the third pad P3.

[0059] The controller 200 transmits various signals to the NAND flash memory 100 and receives various signals from the NAND flash memory 100. Furthermore, the controller 200 is connected to the host device 300 via the host bus 12.

[0060] The controller 200 and the NAND flash memory 100 are interconnected via multiple first wires W1 and multiple second wires W2 for transmitting / receiving various signals. As described above, the multiple first wires W1 transmit / receive chip enable signal CEn, write enable signal WEn, read enable signal REn, address latch enable signal ALE, command latch enable signal CLE, and others.

[0061] The controller 200 controls the NAND flash memory 100 and accesses the NAND flash memory 100 in response to a command received from the host device 300. The host device 300 is, for example, an electronic device, such as a personal computer or the like.

[0062] The controller 200 includes a host interface (I / F) circuit 210, an internal memory (random access memory (RAM)) 220, a processor (central processing unit (CPU)) 230, a buffer memory 240, a NAND interface (I / F) circuit 250, and an error checking and correction (ECC) circuit 260.

[0063] The host I / F circuit 210 is connected to the host device 300 via the host bus 12 and transmits commands and data received from the host device 300 to each of the CPU 230 and the buffer memory 240. In addition, in response to a command from the CPU 230, the host I / F circuit 210 transmits data from the buffer memory 240 to the host device 300.

[0064] The CPU 230 controls the operation of the entire controller 200. For example, when a write command is received from the host device 300, the CPU 230 issues a write command to the NAND I / F circuitry 250 in response. The same applies to read and erase commands. Furthermore, the CPU 230 performs various processes for managing the NAND flash memory 100, such as wear leveling or similar procedures. Additionally, the operation of the controller 200 described below can be implemented by the CPU executing firmware or by hardware.

[0065] NAND I / F circuit 250 transmits various signals to and receives various signals from controller I / F circuit 170 in NAND flash memory 100 to perform communication with NAND flash memory 100. Furthermore, based on commands received from CPU 230, NAND I / F circuit 250 transmits and receives various signals from NAND flash memory 100. Buffer memory 240 temporarily stores data written or read.

[0066] RAM 220 is a semiconductor memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), or the like, and serves as the working area of ​​CPU 230. RAM 220 stores firmware, various management tables, and other information used to manage NAND flash memory 100.

[0067] The ECC circuit 260 performs error detection and error correction processes on the data to be stored in the NAND flash memory 100. Specifically, for data writing, the ECC circuit 260 generates an error correction code (ECC) and assigns the generated ECC to the data being written. For data reading, the ECC circuit 260 determines whether errors exist in the read data, and when errors are determined to exist, the ECC circuit 260 performs an error correction process on the read data using the ECC.

[0068] The configuration of the NAND flash memory 100 will be described next. As described above, in addition to the controller I / F circuit 170, the NAND flash memory 100 also includes a memory cell array 110, a row decoder 120, a driver circuit 130, a column control circuit 140, a register set 150, and a sequencer 160.

[0069] The memory cell array 110 has multiple blocks BLK containing multiple non-volatile memory cells associated with rows and columns. Figure 3 For example, four blocks BLK0 to BLK3 are described. Next, the memory cell array 110 stores the data transmitted from the controller 200.

[0070] The line decoder 120 selects one of blocks BLK0 to BLK3, and further selects the line direction within the selected block BLK. The driver circuit 130 supplies voltage to the selected block BLK via the line decoder 120.

[0071] During data reading, column control circuit 140 senses the data read from memory cell array 110 and performs necessary arithmetic operations. Then, column control circuit 140 outputs the data to controller 200. During data writing, column control circuit 140 transmits the write data received from controller 200 to memory cell array 110.

[0072] Register set 150 includes an address register, a command register, and others. The address register stores the address received from controller 200. The command register stores the command received from controller 200.

[0073] The sequencer 160 controls the operation of the entire NAND flash memory 100 based on various types of information stored in the register set 150.

[0074] like Figure 1 Or as explained in section 2, Figure 3 The NAND flash memory 100 is configured with multiple stacked flash memory chips. By increasing the number of stacked layers, the memory capacity of the NAND flash memory 100 can be increased.

[0075] Figure 4 This is a circuit diagram illustrating an example of a NAND flash memory cell array 110 with a three-dimensional structure. Figure 4 This represents the circuit configuration of one of the blocks BLK in a NAND flash memory cell array 110 having a three-dimensional structure. The other blocks of the NAND flash memory cell array 110 have the same circuit configuration as... Figure 4 The same circuit configuration as described in the document.

[0076] like Figure 4 The description states that a block BLK has, for example, four finger sections FNG (FNG0 to FNG3). Furthermore, each finger section FNG contains multiple NAND strings NS. Each NAND string NS has, for example, eight cascaded memory cell transistors MT (MT0 to MT7), and select transistors ST1 and ST2. In the description herein, each finger section FNG may be referred to as a string cell SU.

[0077] Furthermore, the number of memory cell transistors MT in the NAND string NS is not limited to 8. The memory cell transistors MT are arranged such that their current paths are connected in series between select transistors ST1 and ST2. The current path of memory cell transistor MT7 is connected to one end of the current path of select transistor ST1 at one end of the series connection, and the current path of memory cell transistor MT0 is connected to one end of the current path of select transistor ST2 at the other end of the series connection.

[0078] The gates of the select transistor ST1 in the corresponding finger FNG0 to FNG3 are all connected to the select gate lines SGD0 to SGD3. Meanwhile, the gate of the select transistor ST2 is connected to the same select gate line SGS across multiple finger FNGs. Furthermore, the control gates of the memory cell transistors MT0 to MT7 in the same BLK are all coupled to word lines WL0 to WL7. That is, although word lines WL0 to WL7 and the select gate line SGS are connected across multiple finger FNG0 to FNG3 in the same BLK, even within the same BLK, the select gate line SGD is used independently for each finger FNG0 to FNG3.

[0079] Word lines WL0 to WL7 are respectively connected to the control gate electrodes of the memory cell transistors MT0 to MT7 that make up the NAND string NS, and the i-th memory cell transistor MTi (i = 0 to 7) in the corresponding NAND string NS within the same finger FNG is connected by the same word line WLi (i = 0 to 7). That is, the control gate electrodes of the memory cell transistors MTi in the same row of block BLK are connected to the same word line WLi.

[0080] Each NAND string NS is connected to a word line WLi and also to a bit line. Each memory cell in each NAND string NS can be identified by recognizing the word line WLi, the address of the select gate lines SGD0 to SGD3, and the address of the bit line. As described above, the data in the memory cells (memory cell transistors MT) within the same BLK is erased together. Simultaneously, data reads and writes are performed within the cells of the physical sector MG. A physical sector MG contains multiple memory cells connected to a word line WLi and belonging to a finger section FNG.

[0081] The controller 200 performs writing (programming) in all the units of the NAND string NS connected to a word line WLi within a finger section FNG. Therefore, the unit of the amount of data that the controller 200 performs programming is 4 bits x the number of bit lines.

[0082] During read and program operations, a word line WLi and a select gate line SGD are selected based on the physical address, and a physical sector MG is selected. In the description herein, writing data to a memory cell when necessary is referred to as programming.

[0083] like Figure 3 and 4 As explained, the controller 200 and the NAND flash memory 100 transmit / receive multiple signals. Therefore, the number of bonding lines between the controller 200 and the NAND flash memory 100 increases. Furthermore, as each flash memory chip in the NAND flash memory 100 is miniaturized, the number of stacked flash memory chips also tends to increase. Therefore, when defects such as disconnections, short circuits, or the like occur in the bonding lines from the controller 200, identifying the location of the defect becomes significantly difficult.

[0084] In the memory system 10 according to this embodiment, the current corresponding to each signal transmitted to / received from the plurality of first wires W1 is returned to the controller 200 from the first pad P1 in each flash memory chip via the second wire W2, as in the semiconductor systems 1 and 1a according to the first and second embodiments, so that the controller 200 can easily and accurately identify whether a defect has occurred in the individual first wires W1.

[0085] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in various other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0086] Symbol Explanation

[0087] 1, 1a: Semiconductor System

[0088] 2: Semiconductor chips

[0089] 3: Controller

[0090] 4: Rectifier circuit

[0091] 5: Switching circuit

[0092] 6: Inverter

[0093] 10: Memory System

[0094] 12: Host Bus

[0095] 100: NAND flash memory

[0096] 110: Memory Cell Array

[0097] 120: Line Decoder

[0098] 130: Driver circuit

[0099] 140: Column control circuit

[0100] 150: Register Set

[0101] 160: Sequencer

[0102] 170: Controller I / F circuit

[0103] 200: Controller

[0104] 210: Host Interface (I / F) Circuit

[0105] 220: Internal Memory (Random Access Memory (RAM))

[0106] 230: Processor (Central Processing Unit (CPU))

[0107] 240: Buffer memory

[0108] 250: NAND Interface (I / F) Circuit

[0109] 260: Error checking and correction (ECC) circuit

[0110] 300: Main unit.

Claims

1. A semiconductor system comprising: First semiconductor chip; A second semiconductor chip is stacked on top of the first semiconductor chip; A controller configured to control the first and second semiconductor chips; A first wiring connection is provided between the controller and each of the first and second semiconductor chips, and a first signal is to be transmitted from the controller to each of the first and second semiconductor chips via this connection. A second wiring connection is provided between the controller and the first semiconductor chip, and the current flowing through the first wiring connection to the first semiconductor chip for the first signal is to return to the controller via this connection; and The third wiring connects the controller and the second semiconductor chip, and the current flowing through the first wiring from the first wiring to the second semiconductor chip will return to the controller via this wiring; and The controller is configured to set the voltage level supplied to the first wiring connection to be higher in the defect detection mode of operating the first and second semiconductor chips than in the normal mode of operating the first and second semiconductor chips. During the normal mode, the signal path from the first wiring to the second or third wiring is interrupted. The first semiconductor chip includes a first pad connected to one end of the second wiring, and the second semiconductor chip includes a second pad connected to one end of the third wiring. During the defect detection mode, the controller detects the current flowing from the first terminal to the second terminal through the first pad, and detects the current flowing from the first terminal to the third terminal through the second pad. The first semiconductor chip includes a third pad that is electrically connected to the first wiring, and the second semiconductor chip includes a fourth pad that is electrically connected to the first wiring. During the defect detection mode, the controller detects the current flowing from the first terminal to the second terminal through the third pad and the first pad, and also detects the current flowing from the first terminal to the third terminal through the fourth pad and the second pad. One end of the first wire is connected to the controller, and the opposite end of the first wire is connected to the third or fourth pad, and the third and fourth pads are electrically connected to each other. The current flowing from the first terminal to the third pad of the first semiconductor chip flows through the first pad to the second terminal, and the current flowing from the first terminal to the fourth pad of the second semiconductor chip flows through the second pad to the third terminal. The semiconductor system further includes: A fourth connection is made between the controller and each of the first and second semiconductor chips, and a second signal, different from the first signal, is to be transmitted from the controller to each of the first and second semiconductor chips via this connection, wherein... The first semiconductor chip includes a fifth pad connected to the fourth wiring, and the second semiconductor chip includes a sixth pad connected to the fourth wiring. The controller detects the current of the second signal flowing from the fourth terminal to the second terminal through the fifth pad and the first pad, and flowing from the fourth terminal to the third terminal through the sixth pad and the second pad.

2. The semiconductor system of claim 1, wherein the controller is configured to detect a defect in the first wiring based on the current flowing through the second or third wiring.

3. The semiconductor system according to claim 1, wherein The first semiconductor chip includes a first rectifier circuit between the first pad and the third pad. The first rectifier circuit cuts off current flow from the third pad to the first pad when the voltage level at the first connection is less than a predetermined threshold, and allows current flow from the third pad to the first pad when the voltage level at the first connection is equal to or higher than the threshold. The second semiconductor chip includes a second rectifier circuit between the second pad and the fourth pad, the second rectifier circuit cutting off current flow from the fourth pad to the second pad when the voltage level of the first connection is less than a predetermined threshold, and allowing current flow from the fourth pad to the second pad when the voltage level of the first connection is equal to or higher than the threshold.

4. The semiconductor system according to claim 3, wherein The first semiconductor chip includes a third rectifier circuit between the first pad and the fifth pad. This third rectifier circuit cuts off current flow from the fifth pad to the first pad when the voltage level at the fourth connection is less than a predetermined threshold, and allows current flow from the fifth pad to the first pad when the voltage level at the fourth connection is equal to or higher than the threshold. The second semiconductor chip includes a fourth rectifier circuit between the second pad and the sixth pad, the fourth rectifier circuit cutting off current flow from the sixth pad to the second pad when the voltage level at the fourth connection is less than a predetermined threshold, and allowing current flow from the sixth pad to the second pad when the voltage level at the fourth connection is equal to or higher than the threshold.

5. The semiconductor system according to claim 3, wherein The first rectifier circuit includes a plurality of first diodes connected in series, having a rectification direction aligned in the same direction. The anode of the first diode is connected to the third pad at one end of the plurality of first diodes, and The cathode of the first diode is connected to the first pad at the opposite ends of the plurality of first diodes.

6. The semiconductor system according to claim 5, wherein The first rectifier circuit includes a plurality of third diodes having a rectification direction aligned in a direction opposite to that of the plurality of first diodes connected in series. The cathode of the third diode is connected to the third pad at one end of the plurality of third diodes, and The anode of the third diode is connected to the first pad at the opposite ends of the plurality of third diodes.

7. The semiconductor system according to claim 3, wherein The second rectifier circuit includes a plurality of second diodes connected in series, having a rectification direction aligned in the same direction. The anode of the second diode is connected to the fourth pad at one end of the plurality of second diodes, and The cathode of the second diode is connected to the second pad at the opposite ends of the plurality of second diodes.

8. The semiconductor system of claim 7, wherein The second rectifier circuit includes a plurality of fourth diodes having a rectification direction aligned in a direction opposite to that of the plurality of second diodes connected in series. The cathode of the fourth diode is connected to the fourth pad at one end of the plurality of fourth diodes, and The anode of the fourth diode is connected to the second pad at the opposite ends of the plurality of fourth diodes.

9. The semiconductor system according to claim 3, wherein The first rectifier circuit cuts off the current flow from the first pad to the third pad when the voltage level of the second connection is less than a predetermined threshold, and allows the current flow from the first pad to the third pad when the voltage level of the second connection is equal to or higher than the threshold.

10. The semiconductor system of claim 3, wherein The second rectifier circuit cuts off the current flow from the second pad to the fourth pad when the voltage level of the third connection is less than a predetermined threshold, and allows the current flow from the second pad to the fourth pad when the voltage level of the third connection is equal to or higher than the threshold.

11. The semiconductor system of claim 1, wherein The first semiconductor chip includes: a first switching circuit configured to switch whether the first pad and the third pad are electrically connected to each other; and a second switching circuit configured to switch whether the first pad and the fifth pad are electrically connected to each other. The second semiconductor chip also includes: a third switching circuit configured to switch whether the second pad and the fourth pad are electrically connected to each other; and a fourth switching circuit configured to switch whether the second pad and the sixth pad are electrically connected to each other. The controller causes the first switching circuit to be in a conducting state to electrically conduct the third pad and the first pad and detect the current flowing in the first pad, causes the second switching circuit to be in the conducting state to electrically conduct the fifth pad and the first pad and detect the current flowing in the first pad, causes the third switching circuit to be in the conducting state to electrically conduct the fourth pad and the second pad and detect the current flowing in the second pad, and causes the fourth switching circuit to be in the conducting state to electrically conduct the sixth pad and the second pad and detect the current flowing in the second pad.

12. The semiconductor system of claim 1, wherein the first and second semiconductor chips are flash memory chips.

13. A wiring defect detection method, which uses the wiring defect detection method of the semiconductor system according to claim 1, the method comprising: A defect in the first wiring is detected by returning the current of the first signal flowing in the first wiring to the controller through the second wiring and the third wiring.

14. The wiring defect detection method according to claim 13, further comprising: A second signal, different from the first signal, is transmitted from the controller to the first semiconductor chip and the second semiconductor chip via a fourth connection; and A defect in the fourth wiring is detected by returning the current of the second signal flowing in the fourth wiring to the controller through the second wiring and the third wiring.

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