Multilayer electronic component

Abstract

The laminated electronic component of the present application includes: a plurality of dielectric layers, and a plurality of electrode layers alternately laminated with the plurality of dielectric layers. The skewness of the distribution of the thickness of the dielectric layer at any number of portions of the plurality of dielectric layers is 0.2 or more.

Description

Technical Field

[0001] One aspect of this disclosure relates to stacked electronic components. Background Technology

[0002] Japanese Patent Application Publication No. 2016-160133 discloses a multilayer ceramic capacitor as one type of multilayer electronic component. The multilayer ceramic capacitor described in Patent Document 1 is constructed by alternately stacking dielectric layers and internal electrode layers. Summary of the Invention

[0003] The technical problem that the invention aims to solve

[0004] In such stacked electronic components, efforts are made to improve reliability and extend high-temperature load life. Furthermore, efforts are also made to suppress crack formation.

[0005] Therefore, one aspect of the present invention is to provide a laminated electronic component that can improve high-temperature load life and suppress crack formation.

[0006] Technical means for solving technical problems

[0007] One aspect of the present disclosure is a stacked electronic component comprising: a plurality of dielectric layers and a plurality of electrode layers alternately stacked with the plurality of dielectric layers, wherein the skewness of the thickness distribution of the dielectric layers at any plurality of locations of the plurality of dielectric layers is 0.2 or more.

[0008] In this laminated electronic component, the thickness distribution of the dielectric layers at any of several locations within the multiple dielectric layers has a skewness of 0.2 or more. This results in a thickness distribution biased towards the left (thinner side), with a smaller thickness deviation on the thinner side. Consequently, thinner portions of the dielectric layers can be reduced, improving high-temperature load life. Furthermore, by having a skewness of 0.2 or more, the skirt on the right side (thicker side) of the thickness distribution becomes longer, allowing the dielectric layer to include thicker portions. As a result, the contact area between the dielectric layer and the electrode layer can be increased, ensuring bonding strength and suppressing crack initiation. Therefore, according to this laminated electronic component, high-temperature load life can be improved, and crack initiation can be suppressed.

[0009] Alternatively, the skewness of the distribution can be less than 0.6. In this case, it is possible to suppress the increase in the deviation of the electrostatic capacitance formed by the dielectric layer due to excessive skewness.

[0010] Alternatively, the kurtosis of the distribution can be 3.2 or higher. In this case, the skirt portion of the thickness distribution can be thicker, and the dielectric layer can include a larger portion of the thicker part. As a result, crack initiation can be further suppressed.

[0011] Alternatively, the kurtosis of the distribution can be below 5.0. In this case, it is possible to suppress the increase in the deviation of the electrostatic capacitance formed by the dielectric layer due to excessive kurtosis.

[0012] Alternatively, the average thickness of the multiple dielectric layers can be 0.4 μm or less. As mentioned above, when the dielectric layers are thin, the high electric field strength acting on them tends to decrease the high-temperature load life. Furthermore, since the proportion of electrode layers in the stacked electronic component is relatively increased, cracks are more likely to form. Therefore, according to this stacked electronic component, even under such conditions, the high-temperature load life can be improved, and crack formation can be suppressed.

[0013] The effects of the invention

[0014] According to one aspect of the present invention, it is possible to provide a laminated electronic component that can improve high-temperature load life and suppress crack formation. Attached Figure Description

[0015] Figure 1 This is a cross-sectional view of the stacked electronic components in the implementation method.

[0016] Figure 2 It is a graph used to illustrate skewness.

[0017] Figure 3 It is a graph used to illustrate kurtosis.

[0018] Figure 4 This is a graph illustrating an example of the thickness distribution of the dielectric layer of a stacked electronic component according to an embodiment. Detailed Implementation

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same or equivalent elements will be referred to by the same reference numerals, and repeated descriptions will be omitted.

[0020] [Structure of stacked electronic components]

[0021] exist Figure 1The image shows a laminated electronic component 1 as a laminated ceramic capacitor. The laminated electronic component 1 includes a body 2. The body 2 is formed, for example, in a generally cuboid shape. The body 2 has a pair of main surfaces 2a, a first side surface 2b, and a second side surface 2c. The pair of main surfaces 2a face each other in a first direction D1. The first side surface 2b and the second side surface 2c face each other in a second direction D2 perpendicular to the first direction D1. One main surface 2a constitutes a mounting surface. The laminated electronic component 1 is mounted on a mounting object (e.g., an electronic component or a substrate) by soldering, for example, onto one main surface 2a. The laminated electronic component 1 is, for example, an automotive laminated electronic component used in a car. In this case, a high high-temperature load life is desired for the laminated electronic component 1.

[0022] The substrate 2 has multiple dielectric layers 3 and multiple electrode layers 4. The multiple electrode layers 4 include a first electrode layer 10 and multiple second electrode layers 20. Each dielectric layer 3 is, for example, a sintered body of a ceramic green sheet (dielectric sheet) containing a dielectric material (such as BaTiO3, Ba(Ti,Zr)O3, (Ba,Ca)TiO3, CaZrO3, or (Ca,Sr)(Zr,Ti)O3 dielectric ceramic). In the actual substrate 2, adjacent dielectric layers 3 are integrated to the point that the boundaries between them are indistinguishable. The average thickness of the multiple dielectric layers 3 is, for example, 10 μm or less, and in this example, 0.4 μm or less. The substrate 2, for example, contains at least 10 or 20 or more dielectric layers 3.

[0023] Multiple dielectric layers 3 and multiple electrode layers 4 are alternately stacked along a first direction D1. In this example, multiple first electrode layers 10 and multiple second electrode layers 20 are alternately arranged opposite each other in the first direction D1, separated by dielectric layers 3. The first electrode layers 10 extend to the first side surface 2b of the substrate 2, and the second electrode layers 20 extend to the second side surface 2c of the substrate 2.

[0024] Electrode layer 4 is formed, for example, of a conductive material such as Ni, Cu, Ag, Pd, or alloys thereof. Electrode layer 4 is, for example, a sintered body comprising a conductive paste (conductive layer) containing the conductive material. Electrode layer 4 functions as an internal electrode disposed within the substrate 2. The first electrode layer 10 and the second electrode layer 20 have different polarities. In the stacked electronic component 1, an electrostatic capacitance is formed by the first electrode layer 10 and the second electrode layer 20 being opposite each other.

[0025] The stacked electronic component 1 further includes a pair of external electrodes 5 electrically connected to the mounted object. The pair of external electrodes 5 are formed on a first side surface 2b and a second side surface 2c of the substrate 2, respectively. One external electrode 5 is electrically connected to the first electrode layer 10 on the first side surface 2b, and the other external electrode 5 is electrically connected to the second electrode layer 20 on the second side surface 2c.

[0026] [Manufacturing method for stacked electronic components]

[0027] In manufacturing the laminated electronic component 1, firstly, multiple dielectric sheets are prepared (preparation step). The dielectric sheets are ceramic components that become dielectric layers 3 after firing. Next, multiple dielectric sheets and multiple conductive layers are alternately laminated (lamination step). The conductive layers are layers that become electrode layers 4 after firing, and are, for example, conductive paste.

[0028] Next, the laminate obtained through the lamination process is pressurized along the first direction D1 (pressurization process). Through this pressurization process, adjacent layers are integrated to obtain a chip of a specified size. Alternatively, the laminate having multiple parts that will become chips after cutting can be pressurized in the pressurization process, and then multiple chips of a specified size can be obtained by cutting the laminate. Next, the chip is fired to obtain the substrate 2. Subsequently, through processes such as setting external electrodes 5 on the outer surface of the substrate 2, the laminated electronic component 1 is obtained.

[0029] [Skew and kurtosis of the dielectric layer thickness distribution]

[0030] In the stacked electronic component 1, the skewness of the thickness distribution of the dielectric layer 3 at any multiple locations of the plurality of dielectric layers 3 is 0.2 or more and 0.6 or less, and the kurtosis of this distribution is 3.2 or more and 5.0 or less. This point will be explained below.

[0031] Figure 2 It is a graph used to illustrate skewness, and Figure 3 This is a graph used to illustrate kurtosis (Reference: Cain, Meghan K., Zhiyong Zhang, and Ke-Hai Yuan, "Univariate and multivariates kewness and kurtosis for measuring nonnormality: Prevalence, influence and estimation." Behavior research methods 49.5 (2017), 1716-1735). The skewness A of the probability distribution followed by the random variable X is defined by equation (1), and the kurtosis B is defined by equation (2).

[0032]

[0033]

[0034] In equations (1) and (2), E(X) is the expected value of the random variable X, μ is the mean of the random variable X, and σ is the standard deviation of the random variable X. Skewness is an indicator of asymmetry, which is 0 when the probability distribution is normally distributed. Kurtosis is an indicator of sharpness, which is 3 when the probability distribution is normally distributed. That is, in this specification, kurtosis, unlike excess kurtosis which is 0 when the probability distribution is normally distributed, is defined as 3 when the probability distribution is normally distributed.

[0035] exist Figure 2 The diagram shows three probability distributions with skewnesses of 0.95, 0, and -0.3, respectively. Figure 2 As shown, when the skewness is positive, the distribution is skewed to the left (towards the smaller random variable), and the skirt on the right side of the distribution (towards the larger random variable) becomes longer. Therefore, the phenomenon corresponding to the right side of the distribution, where the random variable is large, is more likely to occur. On the other hand, when the skewness is negative, the distribution is skewed to the right, and the skirt on the left side of the distribution becomes longer. Therefore, the phenomenon corresponding to the left side of the distribution, where the random variable is small, is more likely to occur.

[0036] exist Figure 3 The diagram shows three probability distributions with kurtosis of 3, 0, and -1. In any of these distributions, the variance is 1. For example... Figure 3 As shown, when the kurtosis is greater than 3, the skirt of the distribution becomes thicker. That is, the phenomenon where the random variable is extremely large, corresponding to the two ends of the distribution, is more likely to occur.

[0037] As described above, in the stacked electronic component 1, the skewness of the distribution of the thickness of the dielectric layer 3 at any number of locations of the plurality of dielectric layers 3 is 0.2 or more and 0.6 or less, and the kurtosis of the distribution is 3.2 or more and 5.0 or less. This distribution is calculated, for example, as described below. For the stacked electronic component 1, an image of a cross-section along the stacking direction (first direction D1) is obtained. This image is obtained, for example, using a laser microscope. For the plurality of dielectric layers 3 included in the image, the thickness of the dielectric layer 3 is measured at any number of locations (e.g., 3000 locations). The locations for measuring the thickness of the dielectric layer 3 are, for example, randomly selected, but the thickness of the dielectric layer 3 can also be measured at multiple locations arranged at predetermined intervals. Based on the measured thickness, a probability distribution in which the thickness of the dielectric layer 3 is set as a random variable can be calculated.

[0038] Figure 4This is a graph showing an example of the thickness distribution of the dielectric layer 3 in the stacked electronic component 1. This distribution is calculated based on the thickness (μm) of the dielectric layer 3 measured at 3000 locations. In this example, the skewness of the distribution is 0.42, and the kurtosis is 3.29. The average thickness of the dielectric layer 3 is 0.38 μm, and the standard deviation is 0.05. Thus, in the stacked electronic component 1, the skewness of the thickness distribution of the dielectric layer 3 is 0.2 or more and 0.6 or less. Furthermore, the kurtosis of the distribution is 3.2 or more and 5.0 or less.

[0039] The method for adjusting skewness and kurtosis is explained. In general, in the preparation step of the manufacturing process described above, multiple dielectric sheets are prepared such that the skewness of the thickness distribution of the dielectric sheets at any multiple locations is 0.2 or more and 0.6 or less, and the kurtosis of this distribution is 3.2 or more and 5.0 or less. Therefore, in the laminate obtained through the lamination process, the skewness of the thickness distribution of the dielectric sheets is 0.2 or more and 0.6 or less, and the kurtosis of this distribution is 3.2 or more and 5.0 or less. Furthermore, in the finally obtained laminated electronic component 1, the skewness of the thickness distribution of the dielectric layer 3 is 0.2 or more and 0.6 or less, and the kurtosis of this distribution is 3.2 or more and 5.0 or less.

[0040] More specifically, in the preparation process, for example, by measuring the thickness of the dielectric sheets, dielectric sheets with a thickness less than a predetermined threshold are excluded, while dielectric sheets with a thickness greater than or equal to that threshold are not excluded (used), thereby preparing multiple dielectric sheets in such a way that the skewness of the dielectric sheet thickness distribution is 0.2 or greater. The thickness of the dielectric sheets is measured, for example, using X-rays. As a threshold, for example, the thickness of 100 dielectric sheets can be measured, and the value obtained by multiplying the average thickness of these dielectric sheets by a predetermined coefficient (e.g., 0.2). By not using dielectric sheets with a thickness less than the threshold as described above, the skewness can be controlled to be 0.2 or greater.

[0041] Furthermore, in the preparation process, for example, by using a dielectric sheet with a dispersant content less than a specified value, it is possible to prepare a dielectric sheet with a kurtosis of 3.2 or higher in the thickness distribution of the dielectric sheet. In this way, by reducing the dispersant content, it is possible to produce a dielectric sheet with a large thickness variation.

[0042] Alternatively, in the preparation process, a first dielectric sheet with an average thickness of 1 and a second dielectric sheet with an average thickness of 2 different from 1 can be prepared, such that the kurtosis of the dielectric sheet thickness distribution is 3.2 or higher. In this case, the first and second dielectric sheets are used as dielectric sheets and laminated in the lamination process. By mixing and laminating dielectric sheets of different thicknesses as described above, kurtosis can also be controlled. For example, by preparing a second dielectric sheet that is thicker than the first dielectric sheet (i.e., the second value is greater than the first value) in fewer quantities than the first dielectric sheet, and by mixing the second dielectric sheet in a laminate that is mostly composed of the first dielectric sheet, the kurtosis can be increased compared to the case where all dielectric sheets are composed of the first dielectric sheet.

[0043] [Functions and Effects]

[0044] In the stacked electronic component 1, the skewness of the thickness distribution of the dielectric layers 3 at any of several locations of the plurality of dielectric layers 3 is 0.2 or more. As a result, the thickness distribution is biased towards the left (thinner side), and the thickness deviation on the thinner side is reduced. Consequently, the thinner portions of the dielectric layers 3 can be reduced, and the high-temperature load life can be improved. That is, when the dielectric layers 3 include a larger portion thinner than a reference value, the high-temperature load life may decrease, but in the stacked electronic component 1, since the dielectric layers 3 include fewer thin portions, the high-temperature load life can be improved. As described above, the high-temperature load life is particularly important when the stacked electronic component 1 is used in automotive applications and in high-temperature environments. Furthermore, by having a skewness of 0.2 or more, the skirt on the right side (thicker side) of the thickness distribution becomes longer, allowing the dielectric layers 3 to include thicker portions. As a result, the contact area between the dielectric layers 3 and the electrode layers 4 can be increased, ensuring bonding strength and suppressing crack formation. Therefore, based on the stacked electronic component 1, the high-temperature load life can be improved and the generation of cracks can be suppressed.

[0045] That is, it is generally assumed that the thickness distribution of the dielectric layer in a multilayer ceramic capacitor is close to a normal distribution. In such a multilayer ceramic capacitor, for example, when only the thickness deviation of the dielectric layer 3 is reduced, although the thin portion can be reduced and the high-temperature load life can be improved, the bonding strength between the dielectric layer and the electrode layer is prone to decrease, making cracks more likely to occur. In contrast, in the multilayer electronic component 1, by making the skewness of the thickness distribution of the dielectric layer 3 0.2 or more, the thin portion of the dielectric layer 3 can be reduced, thereby improving the high-temperature load life, and the inclusion of the thick portion of the dielectric layer 3 ensures the bonding strength between the dielectric layer 3 and the electrode layer 4, suppressing crack formation. Thus, according to the multilayer electronic component 1, both the improvement of high-temperature load life and the suppression of crack formation can be achieved.

[0046] The skewness of the thickness distribution of dielectric layer 3 is less than 0.6. This prevents the increase in the deviation of the electrostatic capacitance formed by dielectric layer 3 due to excessive skewness.

[0047] The kurtosis of the thickness distribution of dielectric layer 3 is 3.2 or higher. This allows for a thicker skirt portion of the thickness distribution and enables dielectric layer 3 to include a larger proportion of thicker portions. As a result, crack initiation can be further suppressed. Specifically, by having a kurtosis of 3.2 or higher and a skewness of 0.2 or higher in the thickness distribution of dielectric layer 3, crack initiation can be suppressed by enabling dielectric layer 3 to include a larger proportion of thicker portions, and the decrease in high-temperature load life can be suppressed by preventing the increase of thinner portions.

[0048] The kurtosis of the thickness distribution of dielectric layer 3 is 5.0 or less. This suppresses the increase in the deviation of the electrostatic capacitance formed by dielectric layer 3 due to excessively large kurtosis.

[0049] The average thickness of the multiple dielectric layers 3 is 0.4 μm or less. As described above, when the dielectric layer 3 is thin, the high-temperature load life tends to decrease due to the high electric field strength acting on it. Furthermore, since the proportion of electrode layers 4 in the stacked electronic component 1 is relatively increased, cracks are more likely to form. In response, the stacked electronic component 1 can improve the high-temperature load life even under such conditions and suppress crack formation.

[0050] This disclosure is not limited to the embodiments described above. For example, the materials and shapes of each structure are not limited to those described above, and various materials and shapes can be used. The laminated electronic component 1 may also be a laminated piezoelectric actuator, a laminated rheostat, a laminated thermistor, or a laminated composite component, etc.

Claims

1. A stacked electronic component, wherein, have: Multiple dielectric layers; and Multiple electrode layers are alternately stacked with the plurality of dielectric layers. The skewness of the thickness distribution of the dielectric layers at any of the plurality of locations is greater than 0.2 and less than 0.

6. The kurtosis of the distribution is greater than 3.2 and less than 5.

0. The average thickness of the plurality of dielectric layers is less than 0.4 μm.

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