Methods of manufacturing semiconductor devices and patterning semiconductor structures

Abstract

This disclosure provides a method for manufacturing a semiconductor device, the method comprising the following steps: forming a semiconductor stack including a silicon-containing layer, an oxide deposited on a portion of the silicon-containing layer, an underlayer, and a photoresist layer; patterning the photoresist layer to form a first opening in the photoresist layer; etching the underlayer to extend the first opening into the underlayer, wherein the first opening exposes the top surface of the oxide; etching the oxide and the underlayer using a first etchant, wherein the etch rate ratio of the oxide to the underlayer is approximately 1:1; and etching the oxide and the silicon-containing layer using a second etchant to form a second opening below the first opening, wherein the etch rate of the oxide is higher than the etch rate of the silicon-containing layer. The method provided in this disclosure includes a two-step etching process, thereby completely removing the oxide in the underlayer before patterning the silicon-containing layer, thus allowing the formation of an opening conforming to a critical size in the silicon-containing layer when patterning the silicon-containing layer using the underlayer.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing semiconductor devices and patterned semiconductor structures. Background Technology

[0002] The semiconductor industry has experienced exponential growth. Technological advancements in materials and design have resulted in numerous generations of devices, each with smaller and more complex circuitry compared to its predecessor. Generally, miniaturization offers advantages through increased production efficiency and reduced associated costs. As semiconductor manufacturing processes require smaller process windows, the space needed between components in the device diminishes, becoming increasingly difficult to achieve. Therefore, it is necessary to develop lithography tools and patterning methods suitable for miniaturization processes to facilitate the formation of features with the desired critical dimension (CD). Further advancements can be expected as the advantages of lithography equipment and patterning become apparent in many areas. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, wherein the method includes forming a semiconductor stack including a silicon-containing layer, an oxide deposited on a portion of the silicon-containing layer, an underlayer covering the oxide and the silicon-containing layer, and a photoresist layer above the underlayer. The method also includes patterning the photoresist layer to form a first opening in the photoresist layer, and etching the underlayer to extend the first opening into the underlayer, wherein the first opening exposes a top surface of the oxide. The method also includes etching the oxide and the underlayer using a first etchant, wherein the ratio of a first etch rate of the oxide to a second etch rate of the underlayer is approximately 1:1. The method further includes etching the oxide and the silicon-containing layer using a second etchant different from the first etchant to form a second opening below the first opening, wherein a third etch rate of the oxide is higher than a fourth etch rate of the silicon-containing layer.

[0004] In some embodiments of this disclosure, the ratio of the third etch rate of the oxide to the fourth etch rate of the silicon-containing layer is approximately 3:1.

[0005] In some embodiments of this disclosure, after etching the substrate to extend the first opening, the width of the first opening in the substrate is greater than the maximum width of the oxide.

[0006] In some embodiments of this disclosure, after etching the oxide and silicon-containing layers, the width of a first opening in the substrate is greater than the width of a second opening in the substrate.

[0007] In some embodiments of this disclosure, after etching the underlayer to extend the first opening, the first height between the top surface of the oxide and the bottom surface of the first opening is 25% to 35% of the second height between the top surface of the oxide and the bottom surface of the oxide.

[0008] In some embodiments of this disclosure, the first etchant comprises a mixture of CHF3 and O2.

[0009] In some embodiments of this disclosure, the second etchant comprises a mixture of CHF3 and CH2F2.

[0010] In some embodiments of this disclosure, the semiconductor stack further includes a bottom anti-reflective coating disposed between the bottom layer and the photoresist layer, and etching the bottom layer to extend the first opening further includes etching the bottom anti-reflective coating.

[0011] In some embodiments of this disclosure, the method further includes extending a second opening through the silicon-containing layer to separate the semiconductor device into two parts.

[0012] In some embodiments of this disclosure, the method further includes extending a second opening through a silicon-containing layer and filling the second opening with an insulating material to form an insulator.

[0013] According to some embodiments of this disclosure, a method for patterning a semiconductor structure is provided. The method includes patterning a first photoresist layer to form a first opening in the first photoresist layer, and patterning a second photoresist layer under the first photoresist layer to extend the first opening into the second photoresist layer, wherein the top surface of an oxide layer in the second photoresist layer is higher than the bottom surface of the first opening. The method also includes etching the oxide and the second photoresist layer using a first etchant, wherein a first etch rate of the oxide is close to a second etch rate of the second photoresist layer. The method further includes etching the oxide and a silicon-containing layer under the oxide using a second etchant to form a second opening below the first opening, wherein a third etch rate of the oxide is higher than a fourth etch rate of the silicon-containing layer.

[0014] In some embodiments of this disclosure, after the second photoresist layer is patterned, the width of the bottom surface of the first opening is greater than the maximum width of the oxide.

[0015] In some embodiments of this disclosure, after etching the oxide and silicon-containing layer, the width of the bottom surface of the first opening is greater than the width of the second opening in the silicon-containing layer.

[0016] In some embodiments of this disclosure, after etching the oxide and the silicon-containing layer, the width of the second opening in the silicon-containing layer is close to the maximum width of the oxide.

[0017] In some embodiments of this disclosure, after etching the oxide and silicon-containing layer, the bottom surface of the first opening is higher than the interface between the second photoresist layer and the silicon-containing layer.

[0018] In some embodiments of this disclosure, after etching the oxide and silicon-containing layer, the depth of the first portion of the second opening in the second photoresist layer is greater than the depth of the second portion of the second opening in the silicon-containing layer.

[0019] In some embodiments of this disclosure, etching the oxide and silicon-containing layer further includes etching a second photoresist layer adjacent to the oxide to form a sidewall of the second opening perpendicular to the interface between the second photoresist layer and the silicon-containing layer.

[0020] In some embodiments of this disclosure, the ratio of the third etch rate of the oxide to the fourth etch rate of the silicon-containing layer is between 2.5:1 and 3.5:1.

[0021] In some embodiments of this disclosure, patterning the second photoresist layer includes etching the second photoresist layer using an oxygen-based etchant.

[0022] In some embodiments of this disclosure, the first etchant comprises a fluorine-containing gas and an oxygen-containing gas, and the second etchant comprises a fluorine-containing gas. Attached Figure Description

[0023] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0025] Figures 2A to 6 This is a cross-sectional view of a semiconductor device at an intermediate stage of the manufacturing process according to some embodiments of the present disclosure.

[0026] Figures 7A to 7B This is a cross-sectional view of a semiconductor device at an intermediate stage of the manufacturing process according to some other embodiments of this disclosure. Detailed Implementation

[0027] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, values, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0029] This disclosure provides a method for fabricating a semiconductor device by patterning a semiconductor structure. The method includes forming a semiconductor stack including at least one silicon-containing layer, an oxide deposited on the silicon-containing layer, and an underlayer covering the oxide and the silicon-containing layer. The oxide is then etched using a two-step etching process to completely remove the oxide in the underlayer. Specifically, the two-step process includes etching the oxide using a first etchant having low etch selectivity for both the oxide and the underlayer; and etching the oxide using a second etchant having high etch selectivity for the oxide relative to the silicon-containing layer. Therefore, the pattern in the underlayer can be well defined while over-etching of the silicon-containing layer can be avoided.

[0030] According to some embodiments of this disclosure Figure 1 A flowchart illustrating a method 100 for manufacturing a semiconductor device is provided. Figures 2A to 6 This is a cross-sectional view of a semiconductor device at an intermediate stage of manufacturing method 100. Method 100 can be used to pattern layers of the semiconductor device. The semiconductor device may include memory and / or other logic circuits, passive components, or active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0031] Specifically, method 100 includes the following steps. In step 110, a semiconductor stack is formed, wherein the semiconductor stack includes a silicon-containing layer, an oxide layer, an underlayer, and a photoresist layer. In step 120, the photoresist layer is patterned to form a first opening. In step 130, the underlayer is etched to extend the first opening. In step 140, the oxide layer and the underlayer are etched using a first etchant to extend the first opening. In step 150, the oxide layer and the silicon-containing layer are etched using a second etchant to form a second opening. After the above steps, the semiconductor stack is patterned to fabricate a semiconductor device. Further details are provided below. Figures 2A to 6 The method 100 for manufacturing a semiconductor device is described in detail below. It is worth noting that additional operations may be performed before, during, or after the operations described below, and these modifications are also within the scope of this disclosure.

[0032] In step 110, a semiconductor stack is formed, such as Figures 2A to 2C As shown in the diagram. The semiconductor stack includes one or more target layers to be patterned. More specifically, the semiconductor stack includes at least one silicon-containing layer, wherein the silicon-containing layer serves as the target layer to be patterned. By patterning the target layer, the target layer can be configured to have a plurality of features with openings. The pattern of the target layer can point to multiple semiconductor device features, such as interconnect wires, isolation structures, active regions, or the like.

[0033] refer to Figure 2A A silicon-containing layer 210 is formed on the substrate 200, and an oxide 220 is deposited on a portion of the silicon-containing layer 210. In some embodiments, the substrate 200 may include elemental semiconductors (e.g., germanium and / or germanium), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide and / or indium arsenide), alloy semiconductors (e.g., silicon germanium, gallium arsenide phosphide, aluminum gallium arsenide, aluminum indium arsenide, gallium indium arsenide and / or gallium indium phosphide), or combinations thereof. In some other embodiments, the substrate 200 may be a silicon-on-insulator (SOI) substrate. Multiple features (not shown) associated with a semiconductor device may be present in or above the substrate 200, such as gate structures, source / drain regions, isolation features, interconnect features, or the like.

[0034] In some embodiments, the silicon-containing layer 210 may comprise a silicon-based material having a silicon content greater than 50 atomic percent. For example, the silicon-containing layer 210 may be an amorphous silicon (a-Si) layer. In some other embodiments, the silicon-containing layer 210 may comprise other components, such as hydrogen, to provide hydrogenated amorphous silicon. In some embodiments, the silicon-containing layer 210 may be formed by a chemical vapor deposition (CVD) process, such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDPCVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), or other suitable methods. In some other embodiments, the silicon-containing layer 210 may be formed by physical vapor deposition (PVD), such as plasma-enhanced physical vapor deposition, sputtering, electron beam, thermal evaporation, or other suitable methods. In some other embodiments, the silicon-containing layer 210 can be formed by atomic layer deposition (ALD), such as plasma-enhanced atomic layer deposition.

[0035] In some embodiments, the oxide 220 may have a uniform width such that the sidewalls of the oxide 220 are perpendicular to the top surface of the silicon-containing layer 210. In some other embodiments, the width of the oxide 220 may vary along a direction perpendicular to the top surface of the silicon-containing layer 210. In other words, an angle of less than or greater than 90 degrees may exist between the sidewalls of the oxide 220 and the top surface of the silicon-containing layer 210. For example, as Figure 2A As shown, the cross-sectional view of oxide 220 illustrates a trapezoidal shape, wherein the width of the bottom surface of oxide 220 is greater than the width of the top surface of oxide 220. In some embodiments, oxide 220 may comprise a suitable dielectric material. For example, oxide 220 may comprise silicon oxide or carbon-doped silicon oxide. In some other embodiments, oxide 220 may comprise a dielectric material having a dielectric constant less than 3.9.

[0036] refer to Figure 2B A bottom layer 230 is formed on the oxide 220 and the silicon-containing layer 210. The bottom layer 230 covers the oxide 220 and the silicon-containing layer 210, allowing it to be used as a photoresist or mask in subsequent patterning processes. Therefore, the bottom layer 230 can also be called a second photoresist layer (relative to the subsequent patterning layer). Figure 2CThe first photoresist layer 250 is formed in the substrate. In some embodiments, the substrate 230 may include a patternable carbon-containing material, such as an organic polymer. For example, the substrate 230 may include polyimide. It is worth noting that the substrate 230 may include a suitable non-photosensitive patternable material. In some embodiments, the substrate 230 may include a material different from the oxide 220, such that the substrate 230 and the oxide 220 can be etched separately in different etching processes. For example, the oxide 220 may include silicon oxide and the substrate 230 may include polyimide. In some embodiments, the substrate 230 may be formed by chemical vapor deposition, physical vapor deposition, or other suitable methods. In some other embodiments, the substrate 230 may be formed by spin coating.

[0037] refer to Figure 2C A photoresist layer 250 is formed over the underlying layer 230 to form a semiconductor stack 20. The photoresist layer 250 may include a photosensitive material, such that the photoresist layer 250 on top of the semiconductor stack 20 can be patterned first. The pattern of the photoresist layer 250 can then be transferred to the underlying layer 230. Therefore, the photoresist layer 250 may also be referred to as a first photoresist layer. In some embodiments, the photoresist layer 250 may include a suitable photoresist material different from the underlying layer 230. For example, the photoresist layer 250 may include an epoxy resin while the underlying layer 230 is a carbon layer. In some embodiments, a bottom antireflective coating (BARC) 240 may be formed on the underlying layer 230 before forming the photoresist layer 250 in the semiconductor stack 20. The bottom antireflective coating 240 disposed between the underlying layer 230 and the photoresist layer 250 may include an organic material selected for the photolithography process to be performed in step 120. More specifically, the bottom antireflective coating 240 may provide suitable antireflective properties according to the radiation wavelength of the exposed photoresist layer 250. In some embodiments, the bottom anti-reflective coating 240 can be formed by spin coating.

[0038] like Figure 2C As shown, the silicon-containing layer 210 in the semiconductor stack 20 serves as the target layer for patterning. However, oxide 220 is deposited on a portion of the silicon-containing layer 210, and in subsequent processes, pattern openings will be formed on this portion of the silicon-containing layer 210. If the oxide 220 on the silicon-containing layer 210 and the underlying layer 230 above the oxide 220 are removed in a single step, the oxide 220 may not be completely removed. Therefore, residual oxide 220 may affect the patterning of the silicon-containing layer 210, leading to defects in the semiconductor device. For example, the residual oxide 220 may block the etchant used to etch the silicon-containing layer 210, causing the opening width in the silicon-containing layer 210 to not meet the expected critical dimensions. Therefore, the following steps of method 100 are provided to completely remove the oxide 220.

[0039] In step 120, the photoresist layer (or first photoresist layer) is patterned to form a first opening in the photoresist layer. (See reference) Figure 3 A first opening 300 is formed in the photoresist layer 250, exposing the bottom anti-reflective coating 240 beneath the photoresist layer 250. The first opening 300 is formed above the oxide 220, as... Figure 3 As shown in the diagram. More specifically, oxide 220 is located within the projection of the first opening 300 on the top surface of the silicon-containing layer 210. In some embodiments, the photoresist layer 250 can be patterned using a lithography process by exposing and developing specific portions of the photoresist layer 250.

[0040] In step 130, the underlying layer (or second photoresist layer) is patterned to extend the first opening into the underlying layer. (See reference...) Figure 4 The first opening 300 is extended into the substrate 230 by etching the substrate 230. Specifically, the first opening 300 extending into the substrate 230 exposes the top surface 220t of the oxide 220. In other words, after step 130, the top surface 220t of the oxide 220 in the substrate 230 is higher than the bottom surface 300b of the first opening 300. In some embodiments, after etching the substrate 230 to extend the first opening 300, the first height between the top surface 220t of the oxide 220 and the bottom surface 300b of the first opening 300 may be less than the second height between the top surface 220t and the bottom surface 220b of the oxide 220. For example, the first height between the top surface 220t and the bottom surface 300b may be 25% to 35% of the second height between the top surface 220t and the bottom surface 220b.

[0041] In some embodiments, after etching the substrate 230 to extend the first opening 300, the width W1 of the first opening 300 in the substrate 230 may be greater than the maximum width W2 of the oxide 220. For complete removal of the oxide 220 in subsequent processes, a first opening 300 with a width W1, where the width W1 is greater than the width W2, is preferred. For example, when the oxide 220 has… Figure 4As shown in the trapezoidal shape, the bottom surface 220b of oxide 220 can have a maximum width W2. After the first opening 300 extends into the underlying layer 230, the width W1 of the bottom surface 300b of the first opening 300 is greater than the maximum width W2 of oxide 220. In some embodiments, patterning the underlying layer 230 may include etching the underlying layer 230 by means of a dry etching process. For example, when the underlying layer 230 comprises a carbon-containing material, the underlying layer 230 may be etched using an oxygen-based etchant such as O2. In some embodiments where the semiconductor stack 20 includes a bottom anti-reflective coating 240 between the photoresist layer 250 and the underlying layer 230, patterning the underlying layer 230 to extend the first opening 300 may further include simultaneously etching the bottom anti-reflective coating 240.

[0042] In step 140, the oxide and the underlying layer are etched using a first etchant to extend the first opening. (Reference) Figure 5 The oxide 220 and the substrate 230 are etched using a first etchant, making the bottom surface 300b of the first opening 300 closer to the silicon-containing layer 210. Specifically, in the etching process using the first etchant, the first etching rate of the oxide 220 is close to the second etching rate of the substrate 230. In other words, the ratio of the first etching rate of the oxide 220 to the second etching rate of the substrate 230 is approximately 1:1. Therefore, when etching the oxide 220 and the substrate 230 simultaneously, the first opening 300 can be extended to have a uniform width. As shown in Figure 5A, since the etching rate of the oxide 220 is close to the etching rate of the substrate 230, after step 140, the top surface 220t of the oxide 220 can be higher than the bottom surface 300b of the first opening 300. In some embodiments, the first etching rate of the oxide 220 and the second etching rate of the substrate 230 can be between 140 nm / min and 150 nm / min. In some embodiments, the first etchant in the dry etching process of step 140 may include a suitable gas composition such that the first etchant has low etch selectivity for oxide 220 relative to the underlying layer 230. For example, the first etchant may include a mixture of a fluorine-containing gas and an oxygen-containing gas, such as a mixture of CHF3 and O2.

[0043] In step 150, the oxide and silicon-containing layer are etched using a second etchant to form a second opening. (Reference) Figure 6The oxide 220 and the silicon-containing layer 210 are etched using a second etchant, which is different from the first etchant. Therefore, a second opening 350 is formed below the first opening 300, wherein the second opening 350 includes a first portion in the underlying layer 230 and a second portion in the silicon-containing layer 210. Specifically, in the etching process using the second etchant, the third etch rate of the oxide 220 is higher than the fourth etch rate of the silicon-containing layer 210. Therefore, the oxide 220 can be completely removed while over-etching of the silicon-containing layer 210 is avoided.

[0044] In some embodiments, the ratio of the third etch rate of oxide 220 to the fourth etch rate of silicon-containing layer 210 can be between 2.5:1 and 3.5:1. For example, the ratio of the third etch rate of oxide 220 to the fourth etch rate of silicon-containing layer 210 can be about 2.5:1, 2.8:1, 3:1, 3.2:1, or 3.5:1. In some embodiments, the third etch rate of oxide 220 can be between 120 nm / min and 130 nm / min. In some embodiments, the fourth etch rate of silicon-containing layer 210 can be between 40 nm / min and 45 nm / min. In some embodiments, the second etchant of the dry etching process in step 150 can include a suitable gas composition such that the second etchant has high etch selectivity for oxide 220 relative to silicon-containing layer 210. For example, the second etchant can include a mixture of fluorine-containing gases, such as a mixture of CHF3 and CH2F2. In some embodiments, etching oxide 220 and silicon-containing layer 210 using the second etchant can further include etching the underlying layer 230 adjacent to the portion of oxide 220. For example, when oxide 220 has Figure 5 When the trapezoidal shape is shown, the second etchant can also etch the bottom layer 230 adjacent to the portion of oxide 220 to form the sidewall of the second opening 350 perpendicular to the interface 215, wherein the interface 215 is between the bottom layer 230 and the silicon-containing layer 210.

[0045] After removing oxide 220 and etching silicon-containing layer 210 in step 150, the structure of semiconductor stack 20 is patterned as follows: Figure 6 As shown in the diagram. In some embodiments, the width of the second opening 350 in the silicon-containing layer 210 may be close to the maximum width of the oxide 220. Reference Figure 4 and Figure 6 The oxide 220 is completely removed to form the second opening 350. Therefore, the width W4 of the bottom surface 350b of the second opening 350 can be the same as the width W2 of the bottom surface 220b of the oxide 220. In some embodiments, the width of the first opening 300 in the bottom layer 230 can be greater than the width of the second opening 350 in the bottom layer 230 or the silicon-containing layer 210. For example, due to... Figure 4The width W1 of the first opening 300 shown is greater than the width W2 of the oxide 220, and the width W3 of the bottom surface 300b of the first opening 300 can be greater than the width W4 of the bottom surface 350b of the second opening 350 in the silicon-containing layer 210. In some embodiments, the etching process using the second etchant can have high etching selectivity for the oxide 220 relative to the silicon-containing layer 210. Therefore, the depth of the first portion of the second opening 350 in the bottom layer 230 can be greater than the depth of the second portion of the second opening 350 in the silicon-containing layer 210. In some embodiments, the etching process using the second etchant can have high etching selectivity for the oxide 220 relative to the bottom layer 230. Therefore, the bottom surface 300b of the first opening 300 can be higher than the interface 215 between the bottom layer 230 and the silicon-containing layer 210.

[0046] According to some other embodiments of this disclosure, method 100 may optionally include step 160. In step 160, the second opening is extended through the silicon-containing layer. Figures 7A to 7B This is a cross-sectional view of a semiconductor device at an intermediate stage of manufacturing method 100. (Reference) Figure 7A The second opening 350 extends through the silicon-containing layer 210, exposing the substrate 200. This separates the semiconductor stack 20 into two parts that can be used to fabricate different components of a semiconductor device. In some embodiments, the photoresist layer 250 and the bottom anti-reflective coating 240 may be removed when the second opening 350 is extended in step 160. In some embodiments, after the second opening 350 is extended through the silicon-containing layer 210, a suitable material can be used to fill the second opening 350 to form an element between the two parts of the silicon-containing layer 210. For example, the second opening 350 extending through the silicon-containing layer 210 can be filled with an insulating material, such that an insulator 400 is formed between the two parts of the silicon-containing layer 210, as... Figure 7B As shown in the diagram. In some other embodiments, the second opening 350 extending through the silicon-containing layer 210 may be filled with a conductive material to form a conductive feature. In some embodiments, the underlying layer 230 may be removed before filling the second opening 350.

[0047] The method for manufacturing a semiconductor device disclosed herein provides a two-step etching process to pattern a target layer in a semiconductor structure. First, an oxide layer on the target layer is etched using a first etchant, wherein the etch rate of the oxide is close to the etch rate of the underlying layer on the oxide. Next, the oxide is etched using a second etchant, wherein the etch rate of the oxide is higher than the etch rate of the silicon-containing layer (as the target layer) beneath the oxide. Through this two-step etching process, the oxide layer on the silicon-containing layer can be completely removed before patterning the silicon-containing layer, thereby forming an opening of a desired width in the underlying layer. Therefore, the silicon-containing layer patterned using the underlying layer can meet the critical dimensions required for semiconductor device design.

[0048] While this disclosure has been outlined with reference to specific embodiments, other embodiments are also possible. Therefore, those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0049] [Symbol Explanation]

[0050] 20: Semiconductor stacking

[0051] 100: Method

[0052] 110, 120, 130, 140, 150, 160: Steps

[0053] 200:Substrate

[0054] 210: Silicon-containing layer

[0055] 215: Interface

[0056] 220: Oxides

[0057] 220b: Bottom surface

[0058] 220t: Top surface

[0059] 230: Bottom Layer

[0060] 240: Bottom anti-reflective coating

[0061] 250: Photoresist layer

[0062] 300: First Opening

[0063] 300b: Bottom surface

[0064] 350: Second opening

[0065] 350b: Bottom surface

[0066] 400: Insulator

[0067] W1, W2, W3, W4: Width.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Forming a semiconductor stack, the semiconductor stack comprising: Silicon-containing layer; Oxides are deposited on a portion of the silicon-containing layer; The bottom layer covers the oxide and the silicon-containing layer; as well as A photoresist layer is placed on top of this underlying layer; The photoresist layer is patterned to form a first opening in the photoresist layer; The substrate is etched to extend the first opening into the substrate, wherein the first opening exposes the top surface of the oxide. The oxide and the substrate are etched using a first etchant, wherein the ratio of the first etch rate of the oxide to the second etch rate of the substrate is 1:

1. as well as The oxide and the silicon-containing layer are etched using a second etchant different from the first etchant to form a second opening below the first opening, wherein the third etch rate of the oxide is higher than the fourth etch rate of the silicon-containing layer.

2. The method according to claim 1, characterized in that, The ratio of the third etch rate of the oxide to the fourth etch rate of the silicon-containing layer is 3:

1.

3. The method according to claim 1, characterized in that, After etching the substrate to extend the first opening, the width of the first opening in the substrate is greater than the maximum width of the oxide.

4. The method according to claim 1, characterized in that, After etching the oxide and the silicon-containing layer, the width of the first opening in the substrate is greater than the width of the second opening in the substrate.

5. The method according to claim 1, characterized in that, After etching the bottom layer to extend the first opening, the first height between the top surface of the oxide and the bottom surface of the first opening is 25% to 35% of the second height between the top surface and the bottom surface of the oxide.

6. The method according to claim 1, characterized in that, The first etchant consists of a mixture of CHF3 and O2.

7. The method according to claim 1, characterized in that, The second etchant comprises a mixture of CHF3 and CH2F2.

8. The method according to claim 1, characterized in that, The semiconductor stack further includes a bottom anti-reflective coating disposed between the bottom layer and the photoresist layer, and etching the bottom layer to extend the first opening further includes etching the bottom anti-reflective coating.

9. The method according to claim 1, characterized in that, Further includes: The second opening is extended through the silicon-containing layer to separate the semiconductor device into two parts.

10. The method according to claim 1, characterized in that, Further includes: Extend the second opening through the silicon-containing layer; as well as The second opening is filled with insulating material to form an insulator.

11. A method for patterning a semiconductor structure, characterized in that, include: The first photoresist layer is patterned to form a first opening in the first photoresist layer; The second photoresist layer under the first photoresist layer is patterned to extend the first opening into the second photoresist layer, wherein the top surface of the oxide in the second photoresist layer is higher than the bottom surface of the first opening. The oxide and the second photoresist layer are etched using a first etchant, wherein the first etch rate of the oxide is equal to the second etch rate of the second photoresist layer; as well as The oxide and the silicon-containing layer beneath it are etched using a second etchant to form a second opening below the first opening, wherein the third etch rate of the oxide is higher than the fourth etch rate of the silicon-containing layer.

12. The method according to claim 11, characterized in that, After the second photoresist layer is patterned, the width of the bottom surface of the first opening is greater than the maximum width of the oxide.

13. The method according to claim 11, characterized in that, After etching the oxide and the silicon-containing layer, the width of the bottom surface of the first opening is greater than the width of the second opening in the silicon-containing layer.

14. The method according to claim 11, characterized in that, After etching the oxide and the silicon-containing layer, the width of the second opening in the silicon-containing layer is the same as the maximum width of the oxide.

15. The method according to claim 11, characterized in that, After etching the oxide and the silicon-containing layer, the bottom surface of the first opening is higher than the interface between the second photoresist layer and the silicon-containing layer.

16. The method according to claim 11, characterized in that, After etching the oxide and the silicon-containing layer, the depth of the first portion of the second opening in the second photoresist layer is greater than the depth of the second portion of the second opening in the silicon-containing layer.

17. The method according to claim 11, characterized in that, Etching the oxide and the silicon-containing layer further includes etching the portion of the second photoresist layer adjacent to the oxide layer to form the sidewall of the second opening perpendicular to the interface between the second photoresist layer and the silicon-containing layer.

18. The method according to claim 11, characterized in that, The ratio of the third etch rate of the oxide to the fourth etch rate of the silicon-containing layer is between 2.5:1 and 3.5:

1.

19. The method according to claim 11, characterized in that, Patterning the second photoresist layer involves etching the second photoresist layer using an oxygen-based etchant.

20. The method according to claim 11, characterized in that, The first etchant includes a fluorine-containing gas and an oxygen-containing gas, and the second etchant includes the fluorine-containing gas.

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