Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a substrate, forming a gate structure on the substrate, forming an epitaxial layer in the substrate on both sides of the gate structure, performing a pre-amorphization doping step on the substrate, wherein a defect is generated in the epitaxial layer after the pre-amorphization doping step, forming an outer spacer on both sides of the gate structure, and performing a chemical cleaning step to remove a portion of the epitaxial layer and remove the defect in the epitaxial layer.

Description

Technical Field

[0001] This invention relates to a semiconductor fabrication process including a doping step. In particular, this invention relates to a method for repairing defects arising during the semiconductor doping fabrication process, thereby preventing the formation of epitaxial material dislocations. Background Technology

[0002] Existing semiconductor fabrication processes frequently employ doping techniques to implant desired dopants. While implanting dopants into the material can provide benefits such as adjusting the electrical properties of semiconductor devices, the damage caused by the implantation process often makes the devices more sensitive. To address this challenge, precise damage engineering has been developed in the field. This enhanced amorphization technique strengthens the amorphization phenomenon through implantation, subsequently reducing residual damage after annealing. A commonly used method is called a pre-amorphization implant (PAI), which can form a specific amorphous region on the target material.

[0003] However, the pre-amorphization doping step still has its drawbacks. For example, although the pre-amorphization doping step can form a specific amorphous region on the target, the lattice of the epitaxial material may also be affected after the pre-amorphization doping step, such as generating undesirable dislocations. These dislocation defects may then cause junction leakage current. In addition, the stress specifically stored in the epitaxial material may be relieved during subsequent rapid thermal processing. Summary of the Invention

[0004] The present invention provides a method for forming a semiconductor structure, comprising providing a substrate, forming a gate structure on the substrate, and forming an epitaxial layer in the substrate on both sides of the gate structure, performing a pre-amorphous doping step on the substrate, wherein after the pre-amorphous doping step, a defect is generated in the epitaxial layer to form an outer spacer wall next to the gate structure, and performing a chemical cleaning step to remove a portion of the epitaxial layer and remove the defect in the epitaxial layer.

[0005] This invention therefore proposes a novel semiconductor fabrication process. This novel semiconductor fabrication process includes a method for repairing defects generated during the doping step. Although the novel semiconductor fabrication process still involves a doping step, it prevents the formation of misalignments in the epitaxial stress material after the doping step, and prevents problems such as misalignments, junction leakage current, and stress relief in the epitaxial material, thereby obtaining semiconductor devices with better reliability and device speed. Attached Figure Description

[0006] Figures 1 to 7 This is a schematic diagram of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 101: Substrate

[0009] 102: Shallow trench isolation

[0010] 103: Area

[0011] 105: Amorphous region (defect)

[0012] 110: Gate structure

[0013] 111: Gate dielectric layer

[0014] 112: High dielectric constant layer

[0015] 113: Barrier Layer

[0016] 114: Gate material layer

[0017] 115: Hard Mask

[0018] 116: Internal spacer wall

[0019] 118: Dielectric layer

[0020] 120: Silicon-germanium layer

[0021] 121: Depression

[0022] 122: Epitaxial layer

[0023] 130: External spacer wall

[0024] 132: Concave top surface

[0025] 140: Source / Drain Region

[0026] P1: Pre-amorphization doping step

[0027] P2: Low-temperature heating manufacturing process

[0028] P3: Cleaning Steps

[0029] P4: Steps (Source / Drain doping steps and annealing steps) Detailed Implementation

[0030] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0031] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0032] Figures 1 to 7 This illustration depicts a method for fabricating a semiconductor structure according to an embodiment of the present invention. A key feature of the present invention is that it provides a method for repairing defects generated during the pre-amorphization doping step.

[0033] First, such as Figure 1 As shown, a substrate 101 is first provided. The substrate 101 can be a semiconductor substrate, such as silicon. Furthermore, several shallow trench isolations 102 for electrical isolation are pre-formed in the substrate 101. The steps for forming the shallow trench isolations 102 can be described as follows: First, a plurality of trenches (not shown) for forming the shallow trench isolations are etched in the substrate 101 using a hard mask (not shown). Region 103 of the substrate 101 can be used for PMOS or NMOS. Subsequently, insulating material (not shown) is filled into the previously formed trenches (not shown), and the shallow trench isolations 102 are obtained by planarization, removal of the hard mask (not shown), and removal of excess insulating material (not shown).

[0034] Furthermore, a gate structure 110 can be additionally formed on the substrate 101. The bottom of this gate structure 110 can be a composite structure. For example, the composite structure includes a gate dielectric layer 111, a high dielectric constant layer 112 (if necessary), and a barrier layer 113. The gate structure 110 contains a gate material layer 114, which is covered by a hard mask 115. The gate dielectric layer 111 directly contacts the substrate 101, serving as electrical insulation between the gate structure 110 and the substrate 101. If the gate structure 110 is a silicon gate, the gate dielectric layer 111 can contain silicon compounds, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. If the gate structure 110 is a metal gate, the gate dielectric layer 111 can contain oxides, such as silicon dioxide. The high dielectric constant layer 112, if required, may contain a material with a high dielectric constant, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), or strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3,PZT) and barium strontium titanate (Ba x Sr 1-x The group consists of TiO3 (BST). The barrier layer 113 serves as an isolation layer between the gate material layer 114 and the bottom, and may contain metal compounds such as titanium nitride.

[0035] Furthermore, the current gate material layer 114 can form a dummy gate, which is then replaced by a metal material to form a metal gate (not shown). In this case, the gate material layer 114 can be undoped polysilicon or doped polysilicon to form a silicon gate. The hard mask layer 115 can be a silicon-containing hard mask material.

[0036] The gate structure 110 may also have an inner spacer 116 located inside and an outer spacer (not shown) located outside. The inner spacer 116 is formed on the sidewall of the gate structure 110 by thermal oxidation, for example, by forming silicon oxide, and can simultaneously repair and etch multiple layers of materials such as the gate dielectric layer 111, the high dielectric constant layer 112, the barrier layer 113, the gate material layer 114, and the hard mask layer 115. In addition, after the inner spacer 116 is formed, a shallowly doped drain (LDD) implantation step (not shown) can usually be performed.

[0037] Secondly, such as Figure 2 As shown, an embedded semiconductor epitaxial layer, namely an embedded silicon-germanium layer 120, is formed in a substrate 101. The substrate 101 includes at least one recess 121, and the epitaxial layer (silicon-germanium) 122 fills the recess 121 to form the embedded silicon-germanium layer 120. The method for forming the embedded silicon-germanium layer 120 can be referenced in the following example. First, the exposed substrate 101 is etched once or multiple times through the shielding of the inner spacer wall 116 and the hard mask layer 115 to form the recess 121, and this recess 121 may have a special three-dimensional shape. For example, the recess 121 may extend laterally and partially occupy the gate channel 104 located below the gate structure 110. Depending on the situation, the recess 121 may be formed in the same step as etching the inner spacer wall 116. Next, after completing the cleaning fabrication process, the epitaxial layer 122 can be used to fill the recess 121 to obtain the embedded silicon-germanium layer 120.

[0038] Again, such as Figure 3 As shown, a pre-amorphization doping step P1 can be performed on the embedded silicon-germanium layer 120 to form an amorphous region 105. In this embodiment, arsenic can be used for this pre-amorphization doping step. The pre-amorphization fabrication process (PAI) can be a right-angled or angled PAI process to form an amorphous region 105 within the embedded silicon-germanium layer 120 on both sides of the gate structure 110. However, the applicant has found that defects are easily generated when using arsenic for the doping step. Specifically, the pre-amorphization doping step P1 generates considerable interstitial defects due to dopant impacts on the silicon lattice.

[0039] As previously mentioned, the pre-amorphization doping step P1 typically disrupts a portion of the epitaxial structure embedded in the silicon-germanium layer 120, creating amorphous regions 105. One objective of this invention is to repair these amorphous regions 105. This effectively avoids the drawbacks of current pre-amorphization doping steps; for example, dislocations may occur along the amorphous regions 105. Therefore, repairing the defects caused by the amorphous regions 105 reduces the occurrence of dislocations. In a preferred embodiment of this invention, pre-amorphization doping steps of varying depths can be performed on the silicon-germanium epitaxial material 120, allowing different regions of the silicon-germanium epitaxial material 120 to be selectively amorphized. For example, in this embodiment, the amorphous regions 105 are mainly distributed in the top region of the epitaxial layer 122.

[0040] In the following steps, such as Figure 4 As shown, a dielectric layer 118, such as silicon oxide, is uniformly deposited outside the inner spacer wall 116. In this embodiment, the deposition thickness of the dielectric layer 118 is approximately 740 angstroms or more, but is not limited to this. Notably, after depositing the dielectric layer 118, an additional low-temperature heating process P2 is performed. The temperature of this low-temperature heating step P2 is approximately 500 to 600 degrees Celsius, and the time is approximately 10 minutes. The purpose of this low-temperature heating process P2 is to repair the defects in the aforementioned amorphous region 105. According to the applicant's experiments, heating at a low temperature (around 500 to 600 degrees Celsius) for a longer time helps to repair the amorphous region 105, especially the area near the lower half of the amorphous region 105, because the degree of amorphization is lower, and therefore the repair effect is more obvious. Figure 4 The image shows the amorphous region 105 becoming shallower, indicating that the amorphous region 105 has been partially repaired.

[0041] Then as Figure 5 As shown, an etching step is performed to remove part of the dielectric layer 118, and the remaining material layer becomes the outer spacer 130. The outer spacer 130 can be a single layer or a composite layer, and the present invention is not limited thereto.

[0042] Continue, as Figure 6As shown, after the outer spacer wall 130 is completed, the source / drain region is subsequently formed within the epitaxial layer 122. However, in some embodiments, the aforementioned low-temperature heating fabrication process P2 fails to completely repair the defects in the amorphous region 105. According to the applicant's experiments, even extending the heating time or increasing the heating temperature has limited repair effect on the amorphous region 105. Observations show that although the depth of the amorphous region 105 becomes shallower, a portion of the amorphous region 105 may still remain on the surface of the epitaxial layer 122. If the epitaxial layer 122 is directly ion-doped in subsequent steps to form the source / drain, the amorphous region 105 here may cause adverse effects (e.g., increase the probability of differential packing). Therefore, in this embodiment, an additional cleaning step P3 is performed before forming the source / drain region. The cleaning step P3 here is, for example, a standard cleaning step SC-1 (or APM cleaning), which involves cleaning with a mixed solution of ammonia, hydrogen peroxide, and pure water at approximately 70 degrees Celsius. In this embodiment, the cleaning time is approximately 120 seconds. According to the applicant's experimental results, this cleaning step P3 can not only remove impurities from the chip surface but also remove a portion of the epitaxial layer 122, creating a recessed top surface 132 on the surface of the epitaxial layer 122. Simultaneously with the formation of the recessed top surface 132, the aforementioned residual amorphous region 105 is also removed.

[0043] Again, such as Figure 7 As shown, a source / drain doping step and an annealing step are performed. Figure 7 Step P4 (representing the source / drain doping step and an annealing step) forms a source / drain region 140 in the top region of the epitaxial layer 122. The source / drain doping step can dope different ions depending on the transistor type (N-type or P-type), and the annealing step can be a conventional source / drain annealing step used to activate the previously implanted dopants. Subsequently, other necessary semiconductor steps can be performed, such as replacing the gate material layer 114 with a suitable metal material to form a metal gate, metal silicide formation, contact hole formation, or contact plug formation, etc. These necessary subsequent processes are known to those skilled in the art and will not be described in detail here.

[0044] Based on the above description and figures, the present invention provides a method for forming a semiconductor structure, comprising providing a substrate 101, forming a gate structure 110 on the substrate 101, and forming an epitaxial layer 122 in the substrate 101 on both sides of the gate structure 110, performing a pre-amorphous doping step P1 on the substrate 101, wherein after the pre-amorphous doping step P1, a defect 105 is generated in the epitaxial layer 122, forming an outer spacer 130 next to the gate structure 110, and performing a chemical cleaning step P3 to remove a portion of the epitaxial layer 122 and remove the defect 105 in the epitaxial layer 122.

[0045] In some embodiments of the invention, defect 105 is located in a top region of epitaxial layer 122.

[0046] In some embodiments of the present invention, the method of forming the outer spacer wall 130 includes: covering a dielectric layer 118 on the gate structure 110 and the epitaxial layer 122, performing a low-temperature heating step P2 on the dielectric layer, and performing an etching step to remove a portion of the dielectric layer 118, wherein the remaining dielectric layer after the etching step is defined as the outer spacer wall 130.

[0047] In some embodiments of the present invention, the temperature of the low-temperature heating step P2 is between 500 and 600 degrees Celsius.

[0048] In some embodiments of the present invention, defects in the epitaxial layer 122 are partially repaired during the low-temperature heating step P2.

[0049] In some embodiments of the invention, the dielectric layer 118 has a thickness of 740 angstroms or more.

[0050] In some embodiments of the present invention, the pre-amorphization doping step P1 includes doping with arsenic ions.

[0051] In some embodiments of the present invention, an inner spacer wall 116 is formed prior to the formation of the outer spacer wall 130, wherein the inner spacer wall 116 is located between a side wall of the gate structure 110 and the outer spacer wall.

[0052] In some embodiments of the present invention, the chemical cleaning step P3 includes a standard cleaning step SC-1 (APM cleaning).

[0053] This invention therefore proposes a novel semiconductor fabrication process. This novel semiconductor fabrication process includes a method for repairing defects generated during the doping step. Although the novel semiconductor fabrication process still involves a doping step, it prevents the formation of misalignments in the epitaxial stress material after the doping step, and prevents problems such as misalignments, junction leakage current, and stress relief in the epitaxial material, thereby obtaining semiconductor devices with better reliability and device speed.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: Provide a base; A gate structure is formed on the substrate, and epitaxial layers are formed on both sides of the gate structure in the substrate. The substrate is subjected to a pre-amorphization doping step, wherein defects are generated in the epitaxial layer after the pre-amorphization doping step; Forming an outer spacer wall next to the gate structure, wherein the method of forming the outer spacer wall includes: covering the gate structure and the epitaxial layer with a dielectric layer; performing a low-temperature heating step on the dielectric layer, wherein during the low-temperature heating step, the defect in the epitaxial layer is partially repaired; and performing an etching step to remove a portion of the dielectric layer, wherein the remaining dielectric layer after the etching step is defined as the outer spacer wall. as well as A chemical cleaning step is performed to remove a portion of the epitaxial layer and the defect in the epitaxial layer, resulting in a concave top surface on the surface of the epitaxial layer. After the chemical cleaning step, the epitaxial layer is ion-doped to form source / drain regions within the epitaxial layer below the recessed top surface.

2. The formation method of claim 1, wherein the defect is located in the top region of the epitaxial layer.

3. The forming method as described in claim 1, wherein the temperature of the low-temperature heating step is between 500 and 600 degrees Celsius.

4. The forming method as described in claim 1, wherein the thickness of the dielectric layer is 740 angstroms or more.

5. The formation method of claim 1, wherein the pre-amorphization doping step comprises doping with arsenic ions.

6. The forming method of claim 1, wherein before forming the outer spacer wall, it further comprises forming an inner spacer wall, wherein the inner spacer wall is located between the sidewall of the gate structure and the outer spacer wall.

7. The forming method as described in claim 1, wherein the chemical cleaning step includes a standard cleaning step (SC-1 cleaning).

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