Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, and is applied to the technical field of semiconductors. Specifically, in the preparation method of the semiconductor structure, polycrystalline silicon gates of an SGT device structure are formed first, and then shielding gates of the structure are formed, so that an SGT preparation method which is more beneficial to stress improvement in a semiconductor process is provided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Power semiconductor devices are semiconductor devices that process electrical energy, serving as a bridge between low-voltage control and high-voltage operation. Over 75% of the electrical energy consumed by humans requires conversion by power semiconductor devices before it can be used. Power semiconductor technology makes electrical energy more efficient, energy-saving, and environmentally friendly, providing users with greater convenience. Therefore, it is a fundamental and core technology for energy conservation and emission reduction. Currently, power MOSFETs are commonly used in power supply and load control circuits. The lower the on-resistance of the device, the greater the current it can carry, making it the product with the largest market capacity and fastest-growing demand among power semiconductor switching devices. Trench MOSFET technology is one of the most important technological drivers for achieving this goal. Specifically, discrete gate or shielded gate MOSFETs are an improved UMOS device, offering faster switching speeds and lower switching losses compared to UMOS. Based on the poly structure, they are classified as top-and-bottom (UD SGT) and left-and-right (LR SGT). SGT devices utilize the charge balance principle, appropriately increasing the doping concentration of the epitaxial layer to reduce on-resistance; and using a shielded gate to reduce Cgd / Ciss, improving Dv / dt capability.

[0003] Currently, LR SGT (left-right structure) devices mainly meet the needs of high-voltage applications. The process used in this structure can optimize stress issues in the manufacturing process. The longer the effective field depth, the higher the breakdown voltage the device can withstand, thus meeting the needs of high-voltage applications. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure, thereby solving the problem of high stress in existing SGT devices by proposing a new method for fabricating a left-right structured SGT device.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for preparing a semiconductor structure, which may include at least the following steps:

[0006] A semiconductor substrate is provided, in which two first trenches are formed side by side and symmetrically arranged.

[0007] A gate oxide layer and a polysilicon gate are formed, wherein the first gate oxide layer covers the inner wall of the first trench, and the polysilicon gate covers the surface of the first gate oxide layer and at least fills the first trench;

[0008] A second trench is formed in the semiconductor substrate between the two first trenches, and a shielding gate constituting the LR-SGT device structure is formed in the second trench using a deposition process.

[0009] Furthermore, after the steps of forming the gate oxide layer and the polysilicon gate, the fabrication method may further include: forming a hard mask layer on the surface of the semiconductor substrate, and etching the semiconductor substrate using the hard mask layer as a mask to form the second trench in the semiconductor substrate.

[0010] Furthermore, the hard mask layer can be an ONO stacked structure.

[0011] Furthermore, after the step of forming the second trench and before the step of forming the shielding gate, the preparation method may further include: forming a shielding medium layer on the inner wall of the second trench, the shielding medium layer surrounding the second trench to form an accommodating space.

[0012] Furthermore, the step of forming the shielding barrier may include:

[0013] Polycrystalline silicon material is deposited in the accommodating space, and the polycrystalline silicon material is subjected to a back etching process so that the polycrystalline silicon material only fills the accommodating space.

[0014] Furthermore, the material of the shielding dielectric layer may include silicon dioxide.

[0015] Furthermore, after the step of forming the shielding gate, the preparation method may further include:

[0016] The semiconductor substrate is subjected to multiple ion implantation processes to form a P-body region and an N+ source region in the semiconductor substrate corresponding to the outer side of the first trench; and an interlayer dielectric layer is formed on the entire surface of the semiconductor substrate, and a metal plug is formed in the interlayer dielectric layer by etching and deposition processes.

[0017] Furthermore, before forming the P-body region, the fabrication method may further include: etching away the hard mask layer.

[0018] Furthermore, the semiconductor substrate may be a silicon substrate.

[0019] Secondly, based on the same inventive concept as the semiconductor structure fabrication method described above, the present invention also provides an LR-SGT device, namely, a transistor with a shielded gate trench structure, which can be fabricated using the semiconductor structure fabrication method described above. The specific fabrication method will not be repeated here.

[0020] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0021] This invention proposes a method for fabricating a semiconductor structure. By first forming a polysilicon gate of the SGT device structure and then forming a shielding gate of the structure, a method for fabricating SGTs that is more conducive to stress improvement in semiconductor manufacturing processes is proposed. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0023] Figures 2a to 2d This is a schematic diagram of the semiconductor structure fabrication method in one embodiment of the present invention during its fabrication process.

[0024] The reference numerals in the attached figures are as follows:

[0025] 100 - Semiconductor substrate; 110 - Gate oxide layer;

[0026] 120 - Polysilicon gate; 130 - Hard mask layer;

[0027] 140 - Shielding dielectric layer; 150 - Shielding grid;

[0028] 160 - Interlayer dielectric layer; 170 - Metal plug;

[0029] 101 - First trench; 102 - Second trench;

[0030] 103 - Storage space. Detailed Implementation

[0031] As described in the background section, discrete-gate or shielded-gate MOSFETs are currently an improved type of UMOS device, offering faster switching speeds and lower switching losses compared to UMOS. Based on their polystructure, they are classified as top-and-bottom (UD SGT) and left-and-right (LR SGT). SGT devices utilize the charge balance principle, appropriately increasing the doping concentration of the epitaxial layer to reduce on-resistance; and employing a shielded gate to reduce Cgd / Ciss, thereby improving Dv / dt capability.

[0032] Currently, LR SGT (left-right structure) devices mainly meet the needs of high-voltage applications. The process used in this structure can optimize stress issues in the manufacturing process. The longer the effective field depth, the higher the breakdown voltage the device can withstand, thus meeting the needs of high-voltage applications.

[0033] Therefore, the present invention provides a method for fabricating a semiconductor structure, thereby solving the problem of high stress in existing SGT devices by proposing a new method for fabricating a left-right structure SGT device.

[0034] For details, please refer to... Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, the method for fabricating the semiconductor structure provided by the present invention may include at least the following steps:

[0035] Step S100: A semiconductor substrate is provided, and two first trenches are formed in the semiconductor substrate in which they are arranged side by side and symmetrically.

[0036] Step S200: Forming a gate oxide layer and a polysilicon gate, wherein the first gate oxide layer covers the inner wall of the first trench, and the polysilicon gate covers the surface of the first gate oxide layer and at least fills the first trench.

[0037] In step S300, a second trench is formed in the semiconductor substrate between the two first trenches, and a shielding gate constituting the LR-SGT device structure is formed in the second trench using a deposition process.

[0038] That is, the present invention proposes a method for fabricating a semiconductor structure by first forming a polysilicon gate of the SGT device structure and then forming a shielding gate of the structure, thereby proposing an SGT fabrication method that is more conducive to stress improvement in semiconductor manufacturing process.

[0039] The semiconductor structure and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0040] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0041] The following is a detailed description of a method for fabricating a semiconductor structure provided by this invention. Figures 2a to 2d This is a schematic diagram of the semiconductor structure fabrication method in one embodiment of the present invention during its fabrication process.

[0042] In step S100, please refer to the following for details. Figure 2a As shown, a semiconductor substrate 100 is provided, which serves as an operational platform for subsequent processes to generate a transistor SGT device with a shielded gate trench structure. Specifically, in this embodiment of the invention, the transistor SGT device to be formed is a left-right structure SGT. The semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. For example, in this embodiment, the semiconductor substrate 100 is a silicon wafer. Subsequently, two first trenches 101 arranged side by side and spaced a certain distance apart can be formed in the semiconductor substrate 100 in a direction downward along the upper surface of the semiconductor substrate 100.

[0043] Specifically, the process for forming the first trench 101 can be a wet etching process, a dry etching process, or a hybrid process of wet or dry etching.

[0044] In step S200, continue to refer to Figure 2a As shown, a gate oxide layer 110 and a polysilicon gate 120 are formed. The gate oxide layer 110 covers the inner wall of the first trench 101, and the polysilicon gate 120 covers the surface of the gate oxide layer 110 and at least fills the first trench 101. The first trench 101 is a shallow trench.

[0045] In this embodiment, a gate oxide layer of a certain thickness, such as silicon dioxide, can be deposited on the inner wall of each of the first trenches 101 using a deposition process. This gate oxide layer 110 specifically serves to isolate the semiconductor substrate 100 from the subsequently formed polysilicon gate 120. Specifically, after forming the first trenches 101, polysilicon material can be deposited on the semiconductor substrate 100 to fill each of the first trenches 101 and extend to cover the surface of other semiconductor substrates 100 outside the first trenches 101. Then, the polysilicon material is masked using a chemical polishing (CMP) process to form a polysilicon gate 120 that only fills the first trenches 101. The formation of the gate oxide layer 110 can also utilize a chemical polishing (CMP) process, which is prior art and therefore will not be described in detail here.

[0046] As described above, in the formation process of the SGT device structure provided by this invention, the polysilicon gate of the SGT device structure is formed first, and then the shielding gate of the SGT device structure is formed. In contrast, in the prior art, the shielding gate of the SGT device structure is formed first, followed by the polysilicon gate. This is the main difference between this invention and the prior art, and it is also the key factor that allows this invention to reduce stress problems during the fabrication of the SGT device structure.

[0047] In step S300, please refer to the following for details. Figure 2b and Figure 2c As shown, a second trench 102 is formed in the semiconductor substrate 100 between the two first trenches 101, and a shielding gate 150 constituting the LR-SGT device structure is formed in the second trench 102 using a deposition process.

[0048] For details, please refer to Figure 2a As shown, after step S200 above, which forms the gate oxide layer 110 and the polysilicon gate 120, the fabrication method may further include the following steps:

[0049] A hard mask layer 130 is formed on the surface of the semiconductor substrate, and the semiconductor substrate 100 is etched using the hard mask layer 130 as a mask to form the second trench within the semiconductor substrate 100. The hard mask layer 130 is an ONO stacked structure, i.e., a stacked structure of oxide, nitride, and oxide.

[0050] Specifically, in this embodiment, after forming the gate oxide layer 110 and the polysilicon gate 120 in step S200, an ONO stack structure of oxide, nitride, and oxide can be deposited on the surface of the semiconductor substrate 100. Then, it is etched so that the etched hard mask layer 130 shields the surface of the semiconductor substrate 100 corresponding to the first trench 101 while exposing the middle region of the semiconductor substrate 100. Then, the second trench 102 can be formed by etching within the semiconductor substrate 100 exposed by the hard mask layer 130. Afterwards, a shielding gate 150 of an LR-SGT device structure is formed in the second trench 102 using a deposition process.

[0051] For further details, please refer to Figure 2b As shown, after the step of forming the second trench 102 and before the step of forming the shielding gate 150, the preparation method provided by the present invention may further include: forming a shielding dielectric layer 140 on the inner wall of the second trench 102, the shielding dielectric layer 140 surrounding and forming an accommodating space 103 in the second trench 102. The material of the shielding dielectric layer 140 may include silicon dioxide.

[0052] In this embodiment, a silicon dioxide shielding dielectric layer 140 of a certain thickness can be deposited in the second trench 102 to isolate the semiconductor substrate 100 from the shielding gate 150 formed in subsequent steps. Then, the shielding gate 150 is formed using the same process as the polysilicon gate 120 formed in the above steps, namely, deposition and chemical polishing (CMP) process. The present invention will not make specific limitations on this.

[0053] For further details, please refer to [link / reference]. Figure 2d As shown, in the formation of Figure 2c Following the steps of the shielding gate 150 shown, the preparation method provided by the present invention may further include the following steps:

[0054] The semiconductor substrate 100 is subjected to multiple ion implantation processes to form a P-body region 1 and an N+ source region (not shown) in the semiconductor substrate 100 corresponding to the outer side of the first trench 101; and an interlayer dielectric layer 160 is formed on the entire surface of the semiconductor substrate 100, and a metal plug 170 is formed in the interlayer dielectric layer by etching and deposition processes.

[0055] Furthermore, before forming the P-body region, the preparation method provided by the present invention may further include: etching away the hard mask layer 130.

[0056] Furthermore, based on the same inventive concept as the semiconductor structure fabrication method described above, the present invention also provides a transistor with a shielded gate trench structure, which can be fabricated using the semiconductor structure fabrication method described above. The specific fabrication method will not be repeated here.

[0057] In summary, the semiconductor structure fabrication method proposed in this invention first forms a polysilicon gate for the SGT device structure, and then forms a shielding gate for that structure, thereby providing a more favorable SGT fabrication method for stress improvement in semiconductor manufacturing processes.

[0058] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0059] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0060] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, It should include at least the following steps: A semiconductor substrate is provided, in which two first trenches are formed side by side and symmetrically arranged. A gate oxide layer and a polysilicon gate are formed, wherein the gate oxide layer covers the inner wall of the first trench, and the polysilicon gate covers the surface of the gate oxide layer and at least fills the first trench; A second trench is formed in the semiconductor substrate between the two first trenches, and a shielding gate constituting the LR-SGT device structure is formed in the second trench using a deposition process. The two first trenches are formed before the second trench, and the two first trenches and the second trench are independent of each other. The two sidewalls of the second trench are in contact with the outer sidewalls of the gate oxide layer formed in the two first trenches, which are closer to the second trench.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, After forming the gate oxide layer and the polysilicon gate, the fabrication method further includes: forming a hard mask layer on the surface of the semiconductor substrate, and etching the semiconductor substrate using the hard mask layer as a mask to form the second trench in the semiconductor substrate.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The hard mask layer is an ONO stacked structure.

4. The method for preparing the semiconductor structure as described in claim 3, characterized in that, After the step of forming the second trench and before the step of forming the shielding gate, the preparation method further includes: forming a shielding medium layer on the inner wall of the second trench, the shielding medium layer surrounding and forming an accommodating space in the second trench.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, The step of forming the shielding barrier includes: Polycrystalline silicon material is deposited in the accommodating space, and the polycrystalline silicon material is subjected to a back etching process so that the polycrystalline silicon material only fills the accommodating space.

6. The method for preparing a semiconductor structure as described in claim 4, characterized in that, The material of the shielding dielectric layer includes silicon dioxide.

7. The method for preparing a semiconductor structure as described in claim 5, characterized in that, After the step of forming the shielding gate, the preparation method further includes: The semiconductor substrate is subjected to multiple ion implantation processes to form a P-body region and an N+ source region in the semiconductor substrate corresponding to the outer side of the first trench; and an interlayer dielectric layer is formed on the entire surface of the semiconductor substrate, and a metal plug is formed in the interlayer dielectric layer by etching and deposition processes.

8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, Before forming the P-body region, the fabrication method further includes etching away the hard mask layer.

9. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The semiconductor substrate is a silicon substrate.

10. An LR-SGT device, characterized in that, It is prepared by the method for preparing the semiconductor structure as described in any one of claims 1 to 9.

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