Memory test circuit and device wafer
By using a combination of fuse elements and transistors in the memory test circuit, the destructive nature and insufficient leakage current detection in existing memory testing technologies are solved, achieving non-destructive and accurate leakage path detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-04-11
- Publication Date
- 2026-07-31
AI Technical Summary
Existing memory testing procedures are destructive to memory components, cannot provide local inspection, and cannot effectively detect leakage problems between multiple memory cells.
A memory test circuit is used, which includes a first fuse element and a first transistor. By controlling the on and off states of the transistor, the fuse element is melted or short-circuited to detect leakage paths in the memory array.
It enables non-destructive detection of leakage paths in memory arrays, provides the ability to perform local inspections, and improves the accuracy and reliability of testing.
Smart Images
Figure CN115775792B_ABST
Abstract
Description
Technical Field
[0001] This application claims priority to U.S. Patent Application No. 17 / 467,878 (i.e., priority date "September 7, 2021"), the contents of which are incorporated herein by reference in their entirety.
[0002] This disclosure relates to a test circuit and a component wafer. In particular, it relates to a memory test circuit and a component wafer including the memory test circuit. Background Technology
[0003] In recent decades, with the continuous improvement of electronic products, the demand for storage capacity has also increased. To increase the storage capacity of memory elements (such as a DRAM element), more memory cells are integrated into the memory element. As the integration density increases, the manufacturing process of memory elements becomes more complex, and the process window becomes quite narrow. Therefore, the increased integration density may lead to a higher possibility of leakage between multiple memory cells.
[0004] In addition to developing more advanced manufacturing processes, a testing procedure is needed to ensure low or no leakage current in the manufactured memory devices. However, current testing procedures are destructive to memory devices and cannot provide local inspection. Therefore, the results of these testing procedures can only provide limited information about the memory devices.
[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention
[0006] One embodiment of this disclosure provides a memory test circuit. The memory circuit is coupled to a memory array having a plurality of intersecting first and second signal lines, and includes: a first fuse element having a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, and the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first fuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first fuse element to the reference voltage, the first fuse element is configured to blow into an open circuit, and when the first transistor remains off to disconnect the second terminal of the first fuse element from the reference voltage, the first fuse element functions as a resistor.
[0007] Another embodiment of this disclosure provides a memory test circuit. The memory circuit is coupled to a memory array having a plurality of intersecting first and second signal lines, and includes: a first antifuse element having a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, and the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first antifuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first antifuse element to the reference voltage, the first antifuse element functions as a short-circuit circuit, and when the first transistor remains off to disconnect the second terminal of the first antifuse element from the reference voltage, the first antifuse element functions as an open-circuit circuit.
[0008] Another embodiment of this disclosure provides a device wafer. The device wafer has a plurality of die regions and a dicing region extending between the die regions, and includes: a plurality of memory arrays disposed in the die regions; a replicated memory array disposed in the dicing region and substantially identical to one of the memory arrays in the die regions; and a test circuit disposed in the dicing region and coupled to the replicated memory array. The test circuit includes: a first single-programmable element having a first terminal and a second terminal, the first terminal being coupled to a first group of first signal lines of the replicated memory array, the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first single-programmable element, the second source / drain terminal being coupled to a reference voltage.
[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description
[0010] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.
[0011] Figure 1A This is a circuit structure diagram illustrating a memory cell in a memory array according to some embodiments of the present disclosure.
[0012] Figure 1B This is a circuit structure diagram illustrating some embodiments of this disclosure, for example. Figure 1A The image shows a memory array comprising multiple memory cells.
[0013] Figure 2A This is a layout diagram illustrating some embodiments of this disclosure, for example. Figure 1B A portion of the memory array shown.
[0014] Figure 2B This is a layout diagram illustrating some embodiments of this disclosure, for example. Figure 2A The leakage path shown is between a capacitor contact and a neighboring bit line in the memory array.
[0015] Figure 2C This is a layout diagram, for example... Figure 2A The diagram shows a leakage path between multiple adjacent capacitor contacts in a memory array.
[0016] Figure 3A This is a planar schematic diagram illustrating component wafers of some embodiments of the present disclosure.
[0017] Figure 3B This is a plan view illustrating a memory array replicated under a test procedure according to some embodiments of the present disclosure.
[0018] Figure 4A This is a circuit diagram illustrating some embodiments of the present disclosure, such as... Figure 3A The diagram shows a replicated memory array and a test circuit in one of the test structures.
[0019] Figure 4B This is a circuit diagram illustrating some embodiments of this disclosure, for example. Figure 4A The image shows a replicated memory array with both transistors turned on, along with a test circuit.
[0020] Figure 5 This is a plan view illustrating some embodiments of the present disclosure, for example. Figure 4A and Figure 4B The fuse element shown.
[0021] Figure 6AThis is a circuit diagram illustrating a replicated memory array and a test circuit coupled to the replicated memory array, according to some embodiments of the present disclosure.
[0022] Figure 6B This is a circuit diagram illustrating a replicated memory array and a test circuit coupled to the replicated memory array, according to some embodiments of the present disclosure.
[0023] Figure 7 This is a circuit diagram illustrating a replicated memory array and a test circuit coupled to the replicated memory array, according to some embodiments of the present disclosure.
[0024] The reference numerals in the attached figures are explained as follows:
[0025] 10: Memory cell
[0026] 100: Memory Array
[0027] 100': Replicated memory array
[0028] 100CX: Central Area
[0029] 100CY: Central Area
[0030] 100PX: Surrounding Area
[0031] 100PY: Surrounding Area
[0032] 102: Active Zone
[0033] 104: Capacitor contact point
[0034] 300: Component Wafer
[0035] 302: Grain region
[0036] 304: Cutting Line Area
[0037] 306: Test Structure
[0038] 400: Test Circuit
[0039] 400a: Test Circuit
[0040] 400b: Test Circuit
[0041] 402: Fuse element
[0042] 404: Transistor
[0043] 406: Fuse element
[0044] 408: Transistor
[0045] 500: Conductive line section
[0046] 500a: Solder pad section
[0047] 500b: Tapered section
[0048] 500c: Bridging section
[0049] 700: Test Circuit
[0050] 702: Anti-fuse element
[0051] 706: Anti-fuse element
[0052] AT: Transistor
[0053] AT1: Transistor
[0054] AT2: Transistor
[0055] BL: Bitline
[0056] BL1: The First Elementary Line
[0057] BL2: Second Bit Line
[0058] BL2c: Center Second Bit Line
[0059] BL2p: Second bit line around
[0060] CS: Control signal
[0061] D: Direction
[0062] LK1: Leakage path
[0063] LK2: Leakage path
[0064] N1: Node
[0065] N2: Node
[0066] N3: Node
[0067] N4: Node
[0068] SC: Storage capacitor
[0069] V H Logic high voltage
[0070] V ON : On-state voltage
[0071] V SS Reference voltage
[0072] W 500a :width
[0073] W 500c :width
[0074] WL: Character Line
[0075] WL1: First character line
[0076] WL1c: Center First Character Line
[0077] WL1p: Surrounding first character line
[0078] WL2: Second character line
[0079] X: Direction
[0080] Y: direction Detailed Implementation
[0081] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.
[0082] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass not only the orientations shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.
[0083] Figure 1A This is a circuit structure diagram illustrating a memory cell 10 in a memory array according to some embodiments of the present disclosure.
[0084] Please refer to Figure 1A In some embodiments, the memory array is a DRAM array. In these embodiments, each memory cell 10 in the memory array may include a transistor AT and a storage capacitor SC. One terminal of the storage capacitor SC is coupled to a source / drain terminal of the transistor AT, while the other terminal of the storage capacitor SC may be coupled to a reference voltage (e.g., a ground voltage). The transistor AT acts as an access transistor of the memory cell 10, while the storage capacitor SC is configured to store charge.
[0085] During a write operation, a word line WL is established and coupled to a gate terminal of transistor AT to turn on transistor AT. A voltage applied to a bit line BL coupled to one source / drain terminal of transistor AT is transferred to a storage capacitor SC coupled to the other source / drain terminal of transistor AT. Accordingly, the storage capacitor SC can be charged or discharged, and a logic state "1" or a logic state "0" can be stored in the storage capacitor SC. During a read operation, transistor AT is also turned on, and the charge stored in the storage capacitor SC can pull up or down the pre-charged bit line BL. By comparing a voltage on bit line BL with a reference voltage, the charge stored in the storage capacitor SC can be sensed, and the logic state of memory cell 10 can be determined.
[0086] Figure 1B This is a circuit structure diagram illustrating a memory array 100 comprising multiple memory cells 10 in some embodiments of the present disclosure.
[0087] Please refer to Figure 1B The memory array 100 has multiple columns and multiple rows. The memory cells 10 in each column are arranged along a direction X, and the memory cells 10 in each row are arranged along a direction Y, which intersects the direction X. In some embodiments, the memory cells 10 in each column are connected in pairs. The transistors AT in each pair of memory cells 10 are interconnected by a common source / drain terminal, and this common source / drain terminal is coupled to a bit line BL. Furthermore, the other source / drain terminals of the transistors AT in each pair of memory cells 10 are respectively coupled to a storage capacitor SC, and the gate terminals of the transistors AT in each pair of memory cells 10 are respectively coupled to a word line WL. Moreover, each bit line BL can be shared by the memory cells 10 in a column. On the other hand, each word line WL is shared by the memory cells 10 arranged in a row and extends along the direction Y.
[0088] Figure 2A This is a layout diagram illustrating some embodiments of this disclosure, for example. Figure 1B A portion of the memory array 100 shown.
[0089] Please refer to Figure 2AThe transistors AT of the memory cell 10 are formed on a plurality of active regions 102. The active regions 102 may be multiple well regions in a semiconductor substrate, such as a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. Furthermore, the active regions 102 may be laterally surrounded by an insulating structure (not shown) extending from a front surface of the semiconductor substrate into the substrate, thus insulating them from each other. In some embodiments, a principal axis of each active region extends along a direction D, which intersects with directions X and Y. The active regions 102 may each be formed in an elliptical shape. However, those skilled in the art can modify the geometry of the active regions 102 according to design requirements, and this disclosure is not limited thereto.
[0090] Each of the word lines WL intersects a row of the active regions 102 arranged along the Y direction. Furthermore, the word lines WL are capacitively coupled to the active regions 102, and each connects to the gate terminal of a row of transistors AT. A portion of an active region 102 at opposite sides of a crossed word element WL serves as the source / drain terminal of the transistor AT formed at the intersection of the active region 102 and the word line WL. In some embodiments, the word lines WL are buried in a semiconductor substrate and may laterally pass through the active regions 102. Furthermore, in embodiments where the memory cells 10 are connected in pairs in each column, each active region 102 may intersect two word lines WL, and a pair of transistors AT are formed at the intersection of each active region 102 and the two word lines WL. In these embodiments, a portion of each active region 102 between two crossed word lines WL may serve as a common source / drain terminal of the corresponding transistor AT.
[0091] The bit lines BL extend over the active regions 102, each intersecting a column of active regions 102 arranged in the direction X. Each active region 102 is coupled to the intersecting bit lines BL as part of one of the source / drain terminals of a transistor AT. In embodiments where a pair of transistors AT is formed at the intersection of each active region 102 and two intersecting word lines WL, a portion of each active region 102 between the two intersecting word lines WL serves as a common source / drain terminal of the pair of transistors AT and is coupled to the intersecting bit lines BL. Although not shown, the active regions 102 may be coupled to the bit lines BL overlying them via a plurality of bit line contact points. The bit line contact points are located at the intersection of the active regions 102 and the bit lines BL and extend perpendicularly between the active regions 102 and the bit lines BL.
[0092] exist Figure 2AThe storage capacitor SC (not shown) is laid on the active region 102 and coupled to the active region 102 via a plurality of capacitor contacts 104. A portion of the source / drain terminals of each active region 102, which serves as a transistor AT, is coupled to one bit line BL and one storage capacitor SC, respectively. In this method, one capacitor contact 104 coupled to each active region 102 and one bit line contact (not shown) are located on opposite sides of a cross word line WL. In embodiments where a pair of transistors AT are formed at the intersection of each active region 102 and two cross word lines WL, the portion of each active region 102 between the two cross word lines WL is coupled to one bit line contact, and the portion of each active region 102 on opposite sides of the two cross word lines WL is coupled to two capacitor contacts 104. The capacitor contacts 104 may extend perpendicularly between the active region 102 and the storage capacitor SC (in… Figure 2A (Not shown) and can form a circular shape. However, those skilled in the art can modify the geometry of the capacitor contact 104 according to design needs, and this disclosure is not limited thereto.
[0093] The capacitor contact 104 should be insulated from the bit line BL. However, in some examples, leakage paths may form between some capacitor contacts 104 and their adjacent bit lines BL, thus causing lithography overlay problems, etch damage, defects, or other issues during the fabrication of the memory array 100.
[0094] Figure 2B This is a layout diagram illustrating some embodiments of this disclosure, for example. Figure 2A The leakage path LK1 shown is between a capacitor contact 104 and a neighboring bit line BL in the memory array 100.
[0095] Please refer to Figure 2B A capacitor contact 104 of a transistor AT (represented as transistor AT1) may unintendedly short-circuit to a bit line BL coupled to an adjacent transistor AT (represented as transistor AT2), which is represented as a leakage path LK1. Due to this leakage, the capacitor contact 104 of transistor AT1 can charge or discharge the bit line BL coupled to transistor AT2. Accordingly, if the word line WL coupled to transistor AT2 is determined, the storage capacitor SC stored at the capacitor contact 104 coupled to transistor AT2 (in...) Figure 2BThe charge in (not shown) can be unexpectedly altered by the voltage on bit line BL coupled to transistor AT2. Furthermore, since the voltage on bit line BL coupled to transistor AT2 is pulled up or pulled down, it may affect other storage capacitors SC coupled to this bit line BL. Figure 2B (Not shown in the image). Alternatively, the bit line BL coupled to transistor AT2 can be coupled to the storage capacitor SC at capacitor contact 104 of transistor AT1 (in... Figure 2B (Not shown) Charging or discharging is performed. Therefore, the charge in the storage capacitor SC, which is coupled to the capacitor contact 104 of the transistor AT1, can be changed, even when the word line WL coupled to the transistor AT1 is not determined.
[0096] Furthermore, adjacent capacitor contacts 104 should be insulated from each other. However, in some examples, leakage paths may form between adjacent capacitor contacts 104, thus causing lithography overlay problems, etching damage, defects, or other issues during the fabrication of the memory array 100. In some embodiments, adjacent capacitor contacts 104 on opposite sides of a word line WL are susceptible to such short-circuit problems.
[0097] Figure 2C This is a layout diagram, for example... Figure 2A A leakage path LK2 is shown, which is between multiple adjacent capacitor contacts 104 in the memory array 100.
[0098] Please refer to Figure 2C The capacitor contact 104 of transistor AT1 may be unintendedly short-circuited with the capacitor contact 104 of transistor AT2, which is represented as a leakage path LK2. Typically, the storage capacitor SC coupled to the capacitor contact 104 of transistor AT1 (in...) Figure 2C (Not shown) and the storage capacitor SC coupled to capacitor contact 104 of transistor AT2 should be accessed via different bit lines BL. Due to the leakage path LK2, one of these storage capacitors SC can be charged and discharged without controlling the corresponding bit line BL. For example, when transistor AT2 remains off, if the storage capacitor SC of transistor AT1 is charged via the corresponding bit line BL, then the storage capacitor SC coupled to capacitor contact 104 of transistor AT2 can still be charged via the leakage path LK2 through the storage capacitor SC coupled to capacitor contact 104 of transistor AT1.
[0099] Besides reference Figure 2B and Figure 2CIn addition to the described leakage paths LK1 and LK2, there may be more leakage paths in the memory array 100. To resolve these short-circuit issues, the memory array 100 must be inspected during or after the manufacturing process.
[0100] Figure 3A This is a plan view illustrating a component wafer 300 of some embodiments of the present disclosure.
[0101] Please refer to Figure 3A A single-element wafer 300 may include multiple die regions 302 arranged along multiple columns and rows. Each die region 302 may include a reference. Figure 1B and Figure 2A The plurality of memory arrays 100 are described. Although not shown in the figures, each die region 302 may also include a drive circuit to operate the memory array 100. In some embodiments, a sealing ring (not shown) extends along an inner boundary of each die region 302.
[0102] The die regions 302 are laterally separated from each other by a dicing line region 304. During a singulation process, the device wafer 300 can be diced via the dicing line region 304, and the die regions 302 can be singulated to form a plurality of semiconductor dies. In embodiments where sealing rings are formed in the die regions 302, the sealing rings can protect the surrounding memory array 100 and drive circuitry from possible damage during singulation.
[0103] Multiple test structures 306 may be laid in the dicing region 304. Multiple test procedures may be performed on the test structures 306 during or after the fabrication of the memory array 100. Each test structure 306 may include at least one replicated memory array 100'. The replicated memory array 100' in the test structure 306 may be substantially identical to the memory array 100 formed in the die region 302. Evaluation of the memory array 100 in the die region 302 can be achieved by testing the replicated memory array 100' in the test structure 306. In some embodiments, the test structures 306 are individually laid in the dicing region 304. Those skilled in the art can adjust the arrangement or position of the test structures 306, and this disclosure is not limited thereto.
[0104] Figure 3B This is a plan view illustrating a memory array 100' replicated under a test procedure according to some embodiments of the present disclosure.
[0105] Please refer to Figure 3BThe character lines WL can be divided into multiple first character lines WL1 and multiple second character lines WL2. The first character lines WL1 and second character lines WL2 can be alternately arranged and configured to receive a turn-on voltage and a pass voltage, respectively. The first character line WL1 can turn on the coupled transistor AT by receiving the turn-on voltage. On the other hand, the transistor AT coupled to the second character line WL2 and maintained at the pass voltage can remain off. In embodiments where the transistor AT is an N-type field-effect transistor, the turn-on voltage can be a positive voltage, while the pass voltage can be a ground voltage. Furthermore, in embodiments where each active region 102 and the intersecting bit line BL are shared by a pair of transistors AT, one transistor AT in each pair is on while the other remains off. In these embodiments, one of the storage capacitors (in the active region 102 and coupled to the transistor AT via a capacitor contact 104) shares an active region 102. Figure 3B (Not shown in the image) can be controlled via the cross bit line BL, while the other should be inaccessible.
[0106] Similarly, the bit line BL can be divided into a plurality of alternating first bit lines BL1 and a plurality of second bit lines BL2. The second bit lines BL2 are configured to receive a high voltage. The capacitor contact 104 coupled to the transistor AT, which is turned on by the first bit line BL1, and the storage capacitor SC connected to the second bit line BL2 (in Figure 3B (Not shown) is charged using this high voltage. On the other hand, the first bit line BL1 is configured to receive a low voltage, such as a ground voltage. The capacitor contact 104 coupled to the transistor AT, which is turned on by the first bit line WL1, and the storage capacitor SC connected to the first bit line WL1 should be discharged, while the storage capacitor SC coupled to the capacitor contact 104 of the transistor AT in an off state and connected to the first bit line BL1 or the second bit line BL2 is electrically floating.
[0107] As described above, the first bit line BL1 should be maintained at a low voltage (e.g., a ground voltage), while the second bit line BL2 receives a high voltage. If some of the first bit lines BL1 are pulled up, i.e., current can flow through these first bit lines BL1, then there should be multiple leakage paths in the replicated memory array 100', and also in the memory array 100 in the die region 302. For example, if a leakage path LK1 is generated, a storage capacitor SC coupled to the capacitor contact 104 of a transistor AT in a conducting state and connected to a second bit line BL2 can pull up an adjacent first bit line BL1 via the leakage path LK1. Therefore, current can be detected on this adjacent first bit line BL1. Furthermore, considering the existence of leakage path LK2, a storage capacitor SC coupled to capacitor contact 104 of a transistor AT in a conducting state and connected to a second bit line BL2 can charge an adjacent storage capacitor SC coupled to capacitor contact 104 of a transistor AT in a conducting state and connected to a first bit line BL1. This adjacent storage capacitor SC can also charge the first bit line BL1. Therefore, current can be detected on this first bit line BL1. Thus, by detecting the current on the first bit line BL1, at least two possible types of leakage paths can be detected.
[0108] Figure 4A This is a circuit diagram illustrating some embodiments of the present disclosure, such as... Figure 3A The replicated memory array 100' and a test circuit 400 are shown in one of the test structures 306.
[0109] Please refer to Figure 3B and Figure 4A In some embodiments, the first word line WL1 and the second bit line BL2 of the replicated memory array 100' are coupled to a test circuit 400. The test circuit 400 is configured to selectively provide a turn-on voltage V. ON A logic high voltage VH is selectively provided to the first word line WL1 and to the second word line BL2. Conversely, the second word line WL2 can be coupled to an access voltage. Furthermore, the first word line BL1 can be coupled to a low voltage and used for current sensing to detect a reference voltage. Figure 3B The described example has multiple possible leakage paths. In some embodiments, the voltage through and the low voltage are respectively a ground voltage.
[0110] The first character line WL1 can be further divided into multiple peripheral first character lines WL1p and multiple central first character lines WL1c. The peripheral first character lines WL1p are located within multiple peripheral regions 100PY of the replicated memory array 100', extending along opposite sides of the replicated memory array 100'. Furthermore, the peripheral first character lines WL1p are routed to a node N1, which serves as a terminal of a fuse element 402 in the test circuit 400. On the other hand, the central first character lines WL1c are located within a central region 100CY of the replicated memory array 100', situated between the peripheral regions 100PY of the replicated memory array 100'. Furthermore, the central first character line 100CY is routed to a node N2 and the on-state voltage V. ON Node N2 is used as another terminal of fuse element 402. (See reference...) Figure 3B The aforementioned circuit is capable of conducting voltages coupled to the on-state voltage V. ON The transistor AT at the gate terminal, coupled to the storage capacitor SC, may become accessible.
[0111] Fuse 402 is a single-programmable element that functions as a resistor when not blown into an open circuit. When fuse 402 functions as a resistor, node N1 is coupled to node N2, which has a voltage drop. In other words, both node N2 and node N1 are coupled to the on-state voltage V. ON Accordingly, the transistor AT coupled to the surrounding first word line WL1p and the transistor AT coupled to the central first word line WL1c are both capable of leakage current testing in both the central region 100CY and the surrounding region 100PY of the replicated memory array 100'. On the other hand, when the fuse element 402 blows into an open circuit, node N1 is connected to node N2 and the on-state voltage V. ON Disconnect. In other words, when fuse element 402 blows to an open circuit, the transistor AT coupled to the surrounding first word line WL1p will not conduct, while the transistor AT coupled to the central first word line WL1c will still conduct. Therefore, only the central region 100CY of the replicated memory array 100' can be tested for leakage current.
[0112] In some embodiments, the switching of fuse element 402 is controlled by a transistor 404. For example, transistor 404 may be an N-type field-effect transistor. One source / drain terminal of transistor 404 may be coupled to a reference voltage V. SS For example, a ground voltage. When transistor 404 is in an off state, when the node N1 of one terminal of fuse element 402 is connected to the reference voltage V... SSThe connection is broken, and the potential difference across fuse element 402 is insufficient to cause fuse element 402 to open. In this case, fuse element 402 can function as a resistor. On the other hand, when transistor 404 is turned on, the first node N1, which acts as a terminal of fuse element 402, is coupled to the reference voltage V. SS Meanwhile, node N2 of the other terminal of fuse element 402 is coupled to the on-state voltage V. ON A current passing through fuse element 402, resulting in a large potential difference between nodes N1 and N2, can melt fuse element 402. Therefore, the test circuit 400 is open-circuited at fuse element 402. In some embodiments, a control signal CS is provided to a gate terminal of transistor 404 to switch transistor 404.
[0113] Similar to the first word line WL1, the second bit line BL2 can be further divided into multiple peripheral second bit lines BL2p and multiple central second bit lines BL2c. The peripheral second bit lines BL2p are located within the peripheral region 100PX of the replicated memory array 100, extending along opposite sides of the replicated memory array 100'. The peripheral region 100PX intersects with the peripheral region 100PY in which the peripheral first word line WL1p extends. Furthermore, the peripheral second bit lines BL2p are routed to a node N3, which serves as a terminal of a fuse element 406 in the test circuit 400. On the other hand, the central second bit lines BL2c are located within a central region 100CX of the replicated memory array 100', situated between the peripheral regions 100PX of the replicated memory array 100'. Furthermore, the central second bit lines BL2c are routed to a node N4 and a logic high voltage V. H Node N4 is used as another terminal of fuse element 406. (See reference...) Figure 3B The above provides a logic high voltage V. H The coupled storage capacitor SC is charged.
[0114] Similar to fuse 402, fuse 406 is a single-programmable element. When fuse 406 is not blown into an open circuit, node N3 is coupled to node N4, which has a slight voltage drop. In other words, both node N3 and node N4 are coupled to the logic high voltage V. HAccordingly, the accessible storage capacitors SC coupled to the peripheral second bit line BL2p and the storable storage capacitors SC coupled to the central second bit line BL2c can be charged. Due to this charging source, both the peripheral region 100PX and the central region 100CX can be tested for leakage current. On the other hand, when the fuse element 406 blows to an open circuit, node N4 is disconnected from node N3. In other words, the storage capacitors SC coupled to the peripheral second bit line BL2p (even if they are storable) are not charged, while the accessible storage capacitors SC coupled to the central second bit line BL2c can still be charged. Therefore, only the central region 100CX of the replicated memory array 100' can be tested for leakage current.
[0115] In some embodiments, the switching of fuse element 406 is controlled by a transistor 408. For example, transistor 408 may be an N-type field-effect transistor. One source / drain terminal of transistor 408 is coupled to the first node N4, and the other source / drain terminal of transistor 408 may be coupled to a reference voltage V. SS When transistor 408 is in an off state, node N4, which is a terminal of fuse element 406, receives voltage from the reference voltage V. SS Disconnection. Because an insufficient potential difference crosses fuse element 406, fuse element 406 will not blow into an open circuit. Of course, fuse element 406 can be used as a resistor. On the other hand, when transistor 408 is turned on, node N4, which acts as one terminal of fuse element 406, is coupled to the reference voltage V. SS Meanwhile, node N3, which serves as the other terminal of fuse element 406, is coupled to the logic high voltage V. H A current flowing between nodes N3 and N4 can blow fuse element 406. Therefore, the test circuit 400 is open-circuited at fuse element 406. In some embodiments, the control signal CS is coupled to a terminal of transistor 404 and a terminal of transistor 408. In these embodiments, the switching of transistor 404 and the switching of transistor 408 can be controlled simultaneously.
[0116] As described above, the portion of the storage capacitor SC that is accessible in the replicated memory array 100' and is being charged can be tested for leakage current because it has a charging source for potential leakage. On the other hand, the portion of the storage capacitor SC that is accessible in the replicated memory array 100' and the portion of the storage capacitor SC that is not being charged in the replicated memory array 100' may not be tested for leakage current. In other words, only testing the first word line WL1 in the replicated memory array 100' coupled to the on-state voltage V... ON And the second bit line BL2 is coupled to the logic high voltage V.H Therefore, by switching transistors 406 and 408 to selectively provide an on-state voltage VON and a logic high voltage NH to the first word line WL1 and the second bit line BL2, a localized leakage test can be performed.
[0117] During one step of the test procedure, each of transistors 406 and 408 is in an off state. Therefore, all first word lines WL1 are coupled to the on-state voltage V. ON All second bit lines BL2 are coupled to the logic high voltage V. H Therefore, the storage capacitor SC coupled to all first word lines WL1 and all second word lines BL2 is accessible and charged. In other words, a charging source is provided to the entire replicated memory array 100'. Accordingly, the entire replicated memory array 100' undergoes a leakage test.
[0118] Figure 4B This is a circuit diagram illustrating a replicated memory array 100' and a test circuit 400 when both dual transistors 404 and 408 are turned on, according to some embodiments of this disclosure.
[0119] Please refer to Figure 4B During other steps of the test procedure, both transistors 404 and 408 are turned on by the control signal CS, and fuses 402 and 406 are both blown, creating an open circuit. Therefore, only the center first word line WL1c is coupled to the on-state voltage VON, and only the center second word line BL2c is coupled to the logic high voltage V. H Therefore, only the storage capacitor SC coupled to the central first word line WL1c and the central second word line BL2c is accessible and chargeable. In other words, the charging source is only provided at the intersection of the central region 100CX and the central region 100CY. Accordingly, the leakage test is narrowed down to the intersection of the central region 100CX and the central region 100CY of the replicated memory array 100'.
[0120] By comparing a test result of the entire replicated memory array 100' with a test result of a central portion of the replicated memory array 100' (e.g., the intersection of central regions 100CX and 100CY), it can be determined whether a leakage path is more likely to occur in the central portion or in a surrounding portion. In other words, localized information can be extracted from these test results.
[0121] Figure 5 This is a plan view illustrating some embodiments of the present disclosure, for example. Figure 4A and Figure 4BThe fuse element shown is 402 / 406.
[0122] Please refer to Figure 5 The fuse element 402 / 406 may include a conductive line segment 500. The conductive line segment 500 may have a plurality of pad portions 500a, a plurality of tapered portions 500b, and a bridging portion 500c. The pad portions 500a are located on opposite sides of the conductive line segment 500. The tapered portions 500b extend from the inner sides of each of the pad portions 500a and gradually taper away from the inner sides of each of the pad portions 500a. The bridging portion 500c connects the narrow ends of each of the tapered portions 500b. A width W of the bridging portion 500c is... 500c It can be approximately equal to the width of each narrow end of the tapered portion 100b, and much smaller than the width W of the pad portion 500a. 500a It is approximately equal to the width of each wide end of the tapered portion 500b.
[0123] One pad portion 500a can be coupled to node N2 / N3, while the other pad portion 500a can be coupled to node N1 / N4. Nodes N2 / N3 are coupled to the on-state voltage V. ON Or logic high voltage V H For reference Figure 4A and Figure 4B As described. When nodes N1 / N4 are coupled to the reference voltage V SS At that time, due to a large potential difference between the pad portions 500a, a large current can flow through the conductive line segment 500. Since the bridging portion 500c is along a neck of the conductive line segment 500, the bridging portion 500c may break due to current congestion effect and / or Joule heating effect, thus the conductive line segment 500 (e.g., fuse element 402 / 406) may melt and become an open circuit. On the other hand, when node N1 / N4 is at a reference voltage V SS When disconnected, the current passing through the conductive section 500 (e.g., fuse element 402 / 406) may not be large enough to break the bridging portion 500c of the conductive section 500, and the conductive section 500 can be used as a resistor.
[0124] Figure 6A This is a circuit diagram illustrating a replicated memory array 100' and a test circuit 400a coupled to the replicated memory array 100', according to some embodiments of the present disclosure. The test circuit 400a is similar to that described in Reference 100. Figure 4A The test circuit 400 is described. Therefore, only the differences between test circuits 400 and 400a will be described. Similar or identical parts of test circuits 400 and 400a will not be repeated.
[0125] Please refer to Figure 6A The test circuit 400a may lack references, etc. Figure 4A The described fuse element 406 and transistor 408 are used. Therefore, all second bit lines BL2 are routed to node N3, which is coupled to the logic high voltage V. H And logic high voltage V H All second bit lines BL2 can be supplied without selection. Accordingly, the storage capacitors SC accessible in the surrounding area 100PX and the storage capacitors SC accessible in the central area 100CX can be charged.
[0126] On the other hand, the on-voltage V ON The first word line WL1 can still be selectively supplied via control transistor 404. When transistor 404 is in an off state, all first word lines WL1 are coupled to the on-state voltage V. ON Accordingly, the transistors AT coupled to all first word lines WL1 are turned on, and the storage capacitors SC coupled to these transistors AT are accessible. Since the logic high voltage VH is provided indiscriminately to the second bit line BL2, all these accessible storage capacitors SC can be charged. In other words, a charging source is provided to the entire replicated memory array 100'. Accordingly, the entire replicated memory array 100' undergoes a leakage test.
[0127] During another step of the test procedure, transistor 404 is turned on, and the center first word line WL1 is coupled to the turn-on voltage V. ON Simultaneously, due to the breakage of fuse element 402, the surrounding first character line WL3p is affected by the conduction voltage V. ON Disconnect. Therefore, only the storage capacitor SC coupled to the center first word line WL1c is accessible. Due to the logic high voltage V H The charge is supplied indiscriminately to the second bit line BL2, so all these accessible storage capacitors SC can be charged. In other words, the charging source is provided in the central region 100CY, but not in the surrounding region 100PY. Accordingly, the leakage test is narrowed down to the central region 100CY of the replicated memory array 100'.
[0128] By comparing a test result of the entire replicated memory array 100' with a test result of the central area 100CY of the replicated memory array 100', it can be determined whether a leakage path is more likely to occur in the central area CY or the surrounding area 100PY.
[0129] Figure 6B This is a circuit diagram illustrating a replicated memory array 100' and a test circuit 400b coupled to the replicated memory array 100', according to some embodiments of the present disclosure. The test circuit 400b is similar to that described in Reference 100. Figure 4AThe test circuit 400 is described. Therefore, only the differences between test circuits 400 and 400b will be described. Similar or identical parts of test circuits 400 and 400b will not be repeated.
[0130] Please refer to Figure 6B The test circuit 400b may lack references, etc. Figure 4A The described fuse element 402 and transistor 404 are used. Therefore, all ground word lines WL1 are routed to node N2, which is coupled to the on-state voltage V. ON And the on-state voltage V ON It can be provided to all first character lines WL1 without selection. Accordingly, the storage capacitor SC in the surrounding area 100PY and the storage capacitor SC in the central area 100CY can both be accessed.
[0131] On the other hand, logic high voltage V H The second bit line BL2 can still be selectively supplied via control transistor 406. When transistor 406 is in an off state, all second bit lines BL2 are coupled to the logic high voltage V. H Accordingly, all accessible storage capacitors SC in the surrounding area 100PY and the central area 100CY can be charged. In other words, the charging source provides power to the entire replicated memory array 100'. Accordingly, the entire replicated memory array 100' can be subjected to leakage current testing.
[0132] During another step of the test procedure, transistor 406 is turned on, and the center second bit line BL2c is coupled to the logic high voltage V. H Simultaneously, due to the breakage of fuse element 406, the surrounding second bit line BL2p is affected by the logic high voltage V. H Disconnect. Therefore, only the accessible storage capacitor SC coupled to the central second bit line BL2c can be charged. In other words, the charging source is provided in the central region 100CX, but not in the surrounding region 100X. Accordingly, the leakage test is narrowed down to the central region 100CX of the replicated memory array 100'.
[0133] By comparing a test result of the entire replicated memory array 100' with a test result of the central area 100CX of the replicated memory array 100', it can be determined whether a leakage path is more likely to occur in the central area CX or the surrounding area 100PX.
[0134] Figure 7 This is a circuit diagram illustrating a replicated memory array 100' and a test circuit 700 coupled to the replicated memory array 100', according to some embodiments of the present disclosure. The test circuit 700 is similar to that shown in the referenced document. Figure 4AThe test circuit 400 is described. Therefore, only the differences between test circuits 400 and 700 will be described. Similar or identical parts of test circuits 400 and 700 will not be repeated.
[0135] Please refer to Figure 7 Node N2 is connected to node N1 via an antifuse element 702, which is also a single-programmable element. For example, the antifuse element 702 is a capacitor. When a potential difference across the antifuse element 702 is insufficient to cause dielectric breakdown, the capacitor acts as an open circuit. On the other hand, when a sufficient potential difference is applied across the antifuse element 702, the antifuse element 702 may become a short circuit due to dielectric breakdown.
[0136] When transistor 404 is in an off state, node N1 receives voltage from the reference voltage V. SS Disconnect. The potential difference across antifuse element 702 may not be large enough to cause dielectric collapse; therefore, antifuse element 702 can be considered an open circuit. Accordingly, the forward voltage V ON A signal is provided to the central first word line WL1c, but not to the surrounding first word lines WL1p. Therefore, only the transistors AT coupled to the central first word line WL1c are turned on, and only the storage capacitors SC coupled to these transistors AT are accessible. On the other hand, when transistor 404 is turned on, node N1 is coupled to the reference voltage V. SS Therefore, a large potential difference across the antifuse element 702 can cause dielectric breakdown, and the antifuse element 702 can become a short-circuit circuit. Accordingly, both node N1 and node N2 can be coupled to the on-state voltage V. ON The transistor AT is conductively coupled to the central first word line WL1c and the surrounding first word lines WL1p. Therefore, the storage capacitor SC coupled to these transistors AT is accessible.
[0137] Similarly, node N3 is connected to node N4 via an antifuse element 706. When transistor 408 is in an off state, node N4 is connected to the reference voltage V. SS The connection is broken, and the antifuse element 706 can be treated as an open circuit. Accordingly, the logic high voltage V... H It is supplied to the central second bit line BL2c, but not to the surrounding second bit line BL2p. Therefore, only the accessible storage capacitor SC coupled to the central second bit line BL2c is charged. On the other hand, when transistor 408 is turned on, node N3 is coupled to the reference voltage V. SS Furthermore, the antifuse element 706 can be converted into a short-circuit circuit. Accordingly, both node N3 and node N4 can be coupled to the logic high voltage V. HAnd the accessible storage capacitor SC coupled to the second bit line BL2c and the surrounding second bit line BL2p is charged.
[0138] Therefore, by turning on transistors 404 and 408, the charging source can provide power to the entire replicated memory array 100', and leakage current testing can be performed on the entire replicated memory array 100'. On the other hand, by keeping transistors 404 and 408 in an off state, the charging source can only provide power at the intersection of the central regions 100PY and 100PX, and the leakage current test is narrowed down to this small area. Therefore, leakage current test results for a specific region can be obtained. By comparing the localized leakage current test results with the overall leakage current test results, localized leakage current information can be extracted.
[0139] Similar to the reference Figure 6A The described differences are that the antifuse element 706 and transistor 408 can be omitted from the test circuit 700, and the logic high voltage V H It can be provided to all second-bit lines BL2 without selection. Furthermore, similar to the reference... Figure 6B The differences described are that the antifuse element 702 and transistor 404 can be omitted from the test circuit 700, and the turn-on voltage V ON It can be provided to all first character lines WL1 without selection.
[0140] As described above, this disclosure provides a method for evaluating leakage current in a memory array formed in a diced region, the memory array being disposed within a die region. Therefore, this evaluation method is non-destructive to the memory array within the die region. Furthermore, to obtain an overall leakage current result and a local leakage current result, a test circuit coupled to the replicated memory array is configured to selectively provide a charging source to the entire replicated memory array or a portion thereof. By comparing the overall leakage current result with the local leakage current result, local leakage current information can be extracted.
[0141] One embodiment of this disclosure provides a memory test circuit. The memory circuit is coupled to a memory array having a plurality of intersecting first and second signal lines, and includes: a first fuse element having a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, and the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first fuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first fuse element to the reference voltage, the first fuse element is configured to blow into an open circuit, and when the first transistor remains off to disconnect the second terminal of the first fuse element from the reference voltage, the first fuse element functions as a resistor.
[0142] Another embodiment of this disclosure provides a memory test circuit. The memory circuit is coupled to a memory array having a plurality of intersecting first and second signal lines, and includes: a first antifuse element having a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, and the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first antifuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first antifuse element to the reference voltage, the first antifuse element functions as a short-circuit circuit, and when the first transistor remains off to disconnect the second terminal of the first antifuse element from the reference voltage, the first antifuse element functions as an open-circuit circuit.
[0143] Another embodiment of this disclosure provides a device wafer. The device wafer has a plurality of die regions and a dicing region extending between the die regions, and includes: a plurality of memory arrays disposed in the die regions; a replicated memory array disposed in the dicing region and substantially identical to one of the memory arrays in the die regions; and a test circuit disposed in the dicing region and coupled to the replicated memory array. The test circuit includes: a first single-programmable element having a first terminal and a second terminal, the first terminal being coupled to a first group of first signal lines of the replicated memory array, the second terminal being coupled to a second and third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first single-programmable element, the second source / drain terminal being coupled to a reference voltage.
[0144] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.
[0145] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.
Claims
1. A memory test circuit coupled to a memory array having a plurality of intersecting first signal lines and second signal lines, and comprising: A first fuse element has a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, the second terminal being coupled to a second and a third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; as well as A first transistor has a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of a first fuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first fuse element to the reference voltage, the first fuse element is configured to melt and open, and when the first transistor remains off to disconnect the second terminal of the first fuse element from the reference voltage, the first fuse element functions as a resistor.
2. The memory test circuit as claimed in claim 1, wherein when the first fuse element is blown into an open circuit, the second and third groups of the first signal lines are coupled to the reference voltage, and when the first fuse element is used as a resistor, the second and third groups of the first signal lines are coupled to the first test voltage via the first fuse element.
3. The memory test circuit of claim 1, wherein the first group of the first signal lines extends between the second and third groups of the first signal lines.
4. The memory test circuit as described in claim 1, further comprising: A second fuse element has a first terminal and a second terminal, the first terminal being coupled to a first group of the second signal lines, the second terminal being coupled to a second and a third group of the second signal lines, wherein the first terminal is coupled to a second test voltage; as well as A second transistor has a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the second fuse element, and the second source / drain terminal being coupled to the reference voltage, wherein when the second transistor is turned on to couple the second terminal of the second fuse element to the reference voltage, the second fuse element is configured to melt and open, and when the second transistor remains off to disconnect the second terminal of the second fuse element from the reference voltage, the second fuse element functions as a resistor.
5. The memory test circuit as claimed in claim 4, wherein when the second fuse element is blown into an open circuit, the second and third groups of the second signal lines are coupled to the reference voltage, and when the second fuse element is used as a resistor, the second and third groups of the second signal lines are coupled to the second test voltage via the second fuse element.
6. The memory test circuit of claim 4, wherein the first group of the second signal lines extends between the second and third groups of the second signal lines.
7. The memory test circuit of claim 4, wherein the first transistor and each gate terminal of the second transistor are coupled to a control signal.
8. The memory test circuit of claim 1, wherein all the second signal lines are coupled to a second test voltage.
9. The memory test circuit of claim 1, wherein the memory array further comprises a plurality of third signal lines and a plurality of fourth signal lines, wherein the first signal lines and the third signal lines are alternately arranged along a first direction, and the second signal lines and the fourth signal lines are alternately arranged along a second direction.
10. The memory test circuit of claim 9, wherein the third signal line is not coupled to the first test voltage, the second signal line is selectively or arbitrarily coupled to a second test voltage, and the fourth signal line is not coupled to the second test voltage.
11. The memory test circuit of claim 9, wherein the memory array is a dynamic random access memory array.
12. The memory test circuit of claim 11, wherein the first signal line and the third signal line are word lines, and the second signal line and the fourth signal line are bit lines.
13. The memory test circuit of claim 11, wherein the first signal line and the third signal line are bit lines, and the second signal line and the fourth signal line are word lines.
14. A memory test circuit coupled to a memory array having a plurality of intersecting first signal lines and second signal lines, and comprising: A first antifuse element has a first terminal and a second terminal, the first terminal being coupled to a first group of the first signal lines, the second terminal being coupled to a second and a third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; as well as A first transistor has a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of a first antifuse element, and the second source / drain terminal being coupled to a reference voltage, wherein when the first transistor is turned on to couple the second terminal of the first antifuse element to the reference voltage, the first antifuse element functions as a short-circuit circuit, and when the first transistor remains off to disconnect the second terminal of the first antifuse element from the reference voltage, the first antifuse element functions as an open-circuit circuit.
15. The memory test circuit of claim 14, wherein when the first antifuse element is used as a short-circuit circuit, the second and third groups of the first signal lines are coupled to the first test voltage, and when the first antifuse element is used as an open-circuit circuit, the second and third groups of the first signal lines are coupled to the reference voltage.
16. The memory test circuit of claim 14, further comprising: A second antifuse element has a first terminal and a second terminal, the first terminal being coupled to a first group of the second signal lines, the second terminal being coupled to a second and a third group of the second signal lines, wherein the first terminal is coupled to a second test voltage; as well as A second transistor has a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the second antifuse element, and the second source / drain terminal being coupled to the reference voltage. When the second transistor is turned on to couple the second terminal of the second antifuse element to the reference voltage, the second antifuse element functions as a short-circuit circuit. When the second transistor remains off to disconnect the second terminal of the second antifuse element from the reference voltage, the second antifuse element functions as an open-circuit circuit.
17. The memory test circuit of claim 16, wherein the first transistor and each gate terminal of the second transistor are coupled to a control signal.
18. The memory test circuit of claim 14, wherein all the second signal lines are coupled to a second test voltage.
19. A component wafer having a plurality of grain regions and a dicing region extending between the grain regions, and comprising: Multiple memory arrays are disposed in the grain region; A replicated memory array is disposed in the dicing region and is substantially the same as one of the memory arrays in the grain region; as well as A test circuit, disposed in the cut-line region and coupled to the replicated memory array, includes: A first single-programmable element has a first terminal and a second terminal, the first terminal being coupled to a first group of first signal lines of the replicated memory array, the second terminal being coupled to a second and a third group of the first signal lines, wherein the first terminal is coupled to a first test voltage; as well as A first transistor has a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the first single-programmable element, and the second source / drain terminal being coupled to a reference voltage.
20. The component wafer of claim 19, wherein the test circuit further comprises: A second single-programmable element having a first terminal and a second terminal, the first terminal being coupled to a first group of second signal lines of the replicated memory array, the second terminal being coupled to a second and a third group of the second signal lines, wherein the first terminal is coupled to a second test voltage; as well as A second transistor having a first source / drain terminal and a second source / drain terminal, the first source / drain terminal being coupled to the second terminal of the second single-programmable element, and the second source / drain terminal being coupled to the reference voltage.