Semiconductor device and method of manufacturing the same
By epitaxially growing high carrier mobility materials on conductive nanosheets of CMOS devices to form composite nanosheets that surround the gate, the problems of parasitic resistance and integration density are solved, and the driving performance of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-05-29
Smart Images
Figure CN115775825B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] As CMOS (Complementary Metal-Oxide-Semiconductor) devices continue to shrink along Moore's Law, mass production has entered the 5-3nm technology node. Among these advancements, the use of gate-all-around (GAA) devices effectively suppresses short-channel effects.
[0003] However, for CMOS devices, their driving performance remains one of the main factors limiting their use. Current approaches based on silicon-based materials include increasing the number of stacked layers or widening the nanosheet channel. However, the former increases parasitic resistance in the device, while the latter reduces integration density. Therefore, any of these approaches has significant drawbacks in improving the driving performance of CMOS devices.
[0004] Therefore, improving the driving performance of devices while avoiding the increase of parasitic resistance or the reduction of device integration density has become an urgent problem to be solved. Summary of the Invention
[0005] To address the aforementioned problems, the semiconductor device and its fabrication method provided by this invention, by forming composite nanosheets as conductive channels, can improve the driving performance of the device without increasing parasitic resistance or reducing device integration density.
[0006] In a first aspect, the present invention provides a semiconductor device, comprising: a substrate;
[0007] Source and drain electrodes positioned opposite each other on the substrate;
[0008] The nano-stacked structure is disposed on a substrate; the source and drain are located on opposite sides of the nano-stacked structure; the nano-stacked structure includes multiple conductive nanosheets, which are parallel to the surface of the substrate and stacked at intervals along a direction perpendicular to the substrate, with the source and drain embedded at their respective ends;
[0009] and all-around gate;
[0010] The conductive nanosheets have receiving grooves formed parallel to the surface of the substrate;
[0011] The containment groove is filled with an epitaxial layer. The carrier mobility of the epitaxial layer is higher than that of the conductive nanosheet. The epitaxial layer and the corresponding conductive nanosheet form a composite nanosheet.
[0012] A surrounding gate is arranged around the periphery of multiple composite nanosheets.
[0013] Alternatively, the material of the conductive nanosheets includes silicon.
[0014] Optionally, the depth of the receiving groove is not less than 1 nm.
[0015] Optionally, the thickness of the conductive nanosheet at the receiving groove location ranges from 1 nm to 3 nm.
[0016] Optionally, the epitaxial layer may be made of at least one of germanium and silicon germanium.
[0017] Optionally, the concentration of germanium in the epitaxial layer is not less than 5%.
[0018] Optionally, the epitaxial layer may be made of at least one of gallium arsenide, gallium nitride, and indium phosphide.
[0019] Optionally, the semiconductor device also includes: a protective dielectric layer and three sets of contact electrodes;
[0020] A protective dielectric layer covers the source, drain, and gate. Contact electrodes penetrate the protective dielectric layer, and the three sets of contact electrodes make electrical contact with the source, drain, and all-around gate, respectively.
[0021] Secondly, a method for fabricating a semiconductor device includes:
[0022] Provide substrate;
[0023] A source, a drain, and a stacked region are formed on the substrate. The source and the drain are disposed on opposite sides of the stacked region. The stacked region includes a nano-stacked structure and multiple sacrificial layers. The nano-stacked structure includes multiple conductive nanosheets. The multiple conductive nanosheets are parallel to the surface of the substrate. The multiple conductive nanosheets and the multiple sacrificial layers are alternately stacked along a direction perpendicular to the substrate. The layer structure closest to the substrate in the stacked region is the sacrificial layer. The source and drain are respectively embedded at both ends of the conductive nanosheets.
[0024] Release the stacked region to remove the sacrificial layer;
[0025] The conductive nanosheets are selectively etched to form receiving grooves on the surface of the conductive nanosheets parallel to the substrate;
[0026] An epitaxial layer is extended inside and outside the receiving groove. The carrier mobility of the epitaxial layer is higher than that of the conductive nanosheet. The epitaxial layer and the corresponding conductive nanosheet form a composite nanosheet.
[0027] A surrounding gate is formed, the surrounding gate surrounding the periphery of the plurality of composite nanosheets.
[0028] Optionally, the step of forming the source, drain, and stacked regions on the substrate further includes:
[0029] Sidewalls, a first dielectric layer, and a dummy gate are formed on the substrate. The first dielectric layer is disposed on the side of the substrate facing the source electrode, covering the source electrode and the drain electrode. The dummy gate is disposed on the side of the stacked region facing away from the substrate. The sidewalls are disposed on opposite sides of the dummy gate and the stacked region. The ends of the dummy gate and the sidewalls facing away from the substrate expose the first dielectric layer. The two ends of the conductive nanosheet pass through the corresponding sidewalls and are embedded in the source electrode and the drain electrode, respectively. The sidewalls are used to isolate the dummy gate and the sacrificial layer from the source electrode and the drain electrode.
[0030] Optionally, prior to the step of selectively etching the conductive nanosheets, the fabrication method further includes:
[0031] Remove the spurious gate;
[0032] The step of forming the all-around gate includes:
[0033] A high-k dielectric layer is deposited on the inner wall of the sidewall, the exposed surface of the composite nanosheet, and the surface of the first dielectric layer;
[0034] The remaining space between the opposing side walls is filled with gate material to form the all-around gate.
[0035] Optionally, after the step of forming the all-around gate, the fabrication method further includes:
[0036] A dielectric material is deposited to form a second dielectric layer, the second dielectric layer covering the first dielectric layer and the all-around gate;
[0037] The first dielectric layer and the second dielectric layer are etched to form contact holes and expose the source, the all-around gate and the drain.
[0038] The contact hole is filled with conductive material to lead out the contact electrode.
[0039] The semiconductor device and its fabrication method provided in this invention improve channel carrier mobility by epitaxially growing materials on conductive nanosheets, building upon existing semiconductor device fabrication processes. Specifically, suspended conductive nanosheets are used as selective epitaxial templates to grow high carrier mobility materials required for NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor). Ultimately, the driving capability of the device is improved without significantly altering the existing oxide semiconductor fabrication process framework and flow, and the operation is simple. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of this application in the xx direction;
[0042] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;
[0043] Figures 3 to 9 These are cross-sectional structural diagrams in the xx direction at various stages of the semiconductor device fabrication process according to an embodiment of this application;
[0044] Figure 10 To and Figure 5 Cross-sectional structural diagram along the yy direction at the same stage;
[0045] Figure 11 To and Figure 6 Cross-sectional structural diagram along the yy direction at the same stage;
[0046] Figure 12 To and Figure 7 Cross-sectional structural diagram along the yy direction at the same stage;
[0047] Figure 13 To and Figure 8 A cross-sectional view of the structure along the yy direction at the same stage.
[0048] It should be noted that in the above figures, the xx direction is the fin direction of the semiconductor device, and the yy direction is the direction perpendicular to the fin direction of the semiconductor device.
[0049] Figure Labels
[0050] 1. Substrate; 2. Source; 3. Drain; 4. Nanostructure stacked structure; 41. Conductive nanosheet; 411. Receptacle trench; 42. Epitaxial layer; 43. Composite nanosheet; 5. All-around gate; 61. High-k dielectric layer; 62. Protective dielectric layer; 621. First dielectric layer; 622. Second dielectric layer; 623. Contact hole; 63. Contact electrode; 64. Sidewall; 65. Gate insulating dielectric layer; 66. Dummy gate; 7. Stacked region; 71. Sacrificial layer. Detailed Implementation
[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0053] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0054] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0056] Firstly, this embodiment provides a semiconductor device, see [link to previous document]. Figure 1 The semiconductor device includes: substrate 1, source 2, drain 3, nano-stacked structure 4, and all-around gate 5.
[0057] Source 2, drain 3, nano-stacked structure 4, and all-around gate 5 are all located above substrate 1. Source 2 and drain 3 are located on opposite sides of nano-stacked structure 4. Nano-stacked structure 4 includes multiple conductive nanosheets 41. The material of substrate 1 may be bulk silicon. The material of conductive nanosheets 41 is silicon, but not limited to it. Multiple conductive nanosheets 41 are parallel to the surface of substrate 1, and are stacked at intervals along a direction perpendicular to substrate 1. Source 2 and drain 3 are embedded at both ends of conductive nanosheets 41, respectively. In this embodiment, the materials of source 2 and drain 3 are both silicon-germanium, and the material of all-around gate 5 is aluminum or tungsten, but not limited to these.
[0058] A receiving groove 411 is formed parallel to the surface of the substrate 1 on the conductive nanosheet 41. Specifically, the receiving groove 411 is formed on the upper surface and / or lower surface of the conductive nanosheet 41. The depth of the receiving groove 411 is not less than 1 nm, and can be 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, and 12 nm, etc. The thickness of the conductive nanosheet 41 at the location of the receiving groove 411 is between 1 nm and 3 nm, and can be 1 nm, 2 nm, and 3 nm, etc. In this embodiment, the thickness of the conductive nanosheet 41 at the location of the receiving groove 411 is 2 nm, and the receiving groove 411 is formed on the upper and lower surfaces of the conductive nanosheet 41. It should be noted that the thickness range of the conductive nanosheet 41 can be from 3 nm to 30 nm, and this is not specifically limited in this embodiment.
[0059] An epitaxial layer 42 is filled within the receiving trench 411. The carrier mobility of the epitaxial layer 42 is higher than that of the conductive nanosheet 41. The concentration of germanium in the epitaxial layer 42 ranges from 5% to 100%, and the material of the epitaxial layer 42 is preferably at least one of high hole mobility materials such as germanium and silicon-germanium, thus forming a nanosheet stacked structure suitable for PMOS. Alternatively, the material of the epitaxial layer 42 is preferably at least one of high electron mobility materials such as gallium arsenide, gallium nitride, and indium phosphide, thus forming a nanosheet stacked structure suitable for NMOS.
[0060] In this embodiment, the epitaxial layer 42 and the corresponding conductive nanosheets 41 form composite nanosheets 43, that is, the nano-stacked structure 4 includes multiple composite nanosheets 43 stacked at intervals along the vertical direction to form multiple conductive channels. A surrounding gate 5 surrounds the periphery of the multiple composite nanosheets 43 relative to the straight line direction from the drain 3 towards the source 2.
[0061] In one optional embodiment, the semiconductor device further includes a high-k dielectric layer 61, a protective dielectric layer 62, and three sets of contact electrodes 63. The protective dielectric layer 62 covers the source 2, drain 3, and gate. The contact electrodes 63 penetrate the protective dielectric layer 62, and the three sets of contact electrodes 63 make electrical contact with the source 2, drain 3, and all-around gate 5, respectively. The high-k dielectric layer 61 covers the periphery and bottom of the all-around gate 5. In this optional embodiment, the number of each set of contact electrodes 63 is not specifically limited.
[0062] The protective dielectric layer 62 is made of silicon dioxide, the contact electrode 63 is made of the same material as the all-around gate 5, and the high-K dielectric layer 61 is made of materials such as HfO2 or Al2O3, but is not limited to these.
[0063] In an alternative embodiment, the semiconductor device further includes a sidewall 64.
[0064] Sidewalls 64 are disposed on both sides of the all-around gate 5 facing the source 2 and drain 3, respectively, to electrically isolate the all-around gate 5 from the source 2 and drain 3. The conductive nanosheets 41 pass through the corresponding sidewalls 64 at both ends and are embedded in the source 2 and drain 3.
[0065] The high-K dielectric layer 61 is located inside the sidewall 64, and the sidewall of the receiving groove 411 is flush with the inner wall of the sidewall 64.
[0066] In this embodiment, the semiconductor device is a GAA device. Based on the existing fabrication process of GAA devices, the channel carrier mobility is improved by epitaxially growing materials on the conductive nanosheets 41. Specifically, the suspended conductive nanosheets 41 are used as selective epitaxial templates to grow materials with high carrier mobility required for NMOS and PMOS. Ultimately, the driving capability of the device can be improved without significantly altering the existing GAA fabrication process framework and flow. The operation is simple and easy to fabricate.
[0067] Secondly, this embodiment provides a method for fabricating a semiconductor device, see [link to relevant documentation]. Figure 2 The preparation method includes steps S101 to S106:
[0068] Step S101: Provide substrate 1.
[0069] Step S102: Combining Figure 3 Source 2, drain 3 and stacked region 7 are formed on substrate 1.
[0070] Source 2 and drain 3 are disposed on opposite sides of stacked region 7. Stacked region 7 includes a nano-stacked structure 4 and multiple sacrificial layers 71. The nano-stacked structure 4 includes multiple conductive nanosheets 41, which are parallel to the surface of substrate 1. The multiple conductive nanosheets 41 and multiple sacrificial layers 71 are alternately stacked in a direction perpendicular to substrate 1. The layer structure closest to substrate 1 in stacked region 7 is the sacrificial layer 71. Source 2 and drain 3 are embedded at both ends of conductive nanosheets 41, respectively. It should be noted that stacked region 7 can be understood as a fin, and stacked region 7 is orthogonal to dummy gate 66 in the horizontal direction.
[0071] In an alternative embodiment, the step of forming a source 2, a drain 3 and a stacked region 7 on the substrate 1 further includes forming a sidewall 64, a first dielectric layer 621 and a dummy gate 66 on the substrate 1.
[0072] A first dielectric layer 621 is disposed on the side of the substrate 1 facing the source electrode 2, covering the source electrode 2 and the drain electrode 3. A dummy gate 66 is disposed on the side of the stacked region 7 away from the substrate 1. Sidewalls 64 are disposed on opposite sides of the dummy gate 66 and the stacked region 7, with the ends of the dummy gate 66 and the sidewalls 64 away from the substrate 1 exposing the first dielectric layer 621. The two ends of the conductive nanosheet 41 pass through the corresponding sidewalls 64 and are embedded in the source electrode 2 and the drain electrode 3, respectively. The sidewalls 64 are used to isolate the dummy gate 66 and the sacrificial layer 71 from the source electrode 2 and the drain electrode 3. The material of the sidewalls 64 is silicon nitride, but it is not limited to this.
[0073] Prior to the step of selectively etching the conductive nanosheet 41, the fabrication method further includes removing the dummy gate 66. Specifically, the dummy gate 66 can be selectively removed from the space containing it using TMAH (tetramethylammonium hydroxide). The dummy gate 66 is made of polycrystalline silicon.
[0074] In an optional embodiment, prior to the step of removing the dummy gate 66, the preparation method further includes: removing the natural oxide layer on the surface of the dummy gate 66 with a 100:1 diluted HF solution for a duration of 5s to 60s.
[0075] The step of forming a source 2, a drain 3, a stacked region 7, a sidewall 64, a first dielectric layer 621, and a dummy gate 66 on the substrate 1 further includes forming a gate insulating dielectric layer 65 on the substrate 1. The gate insulating dielectric layer 65 is located between the stacked region 7 and the dummy gate 66, and the material of the gate insulating dielectric layer 65 is silicon dioxide, but is not limited thereto.
[0076] After removing the dummy gate 66, combined Figure 4 The preparation method further includes removing the gate insulating dielectric layer 65. Specifically, the gate insulating dielectric layer 65 above the dummy stacked region 7 is selectively removed in the space where the gate insulating dielectric layer 65 is located using a 100:1 diluted DHF (dilute hydrofluoric acid) solution or BOE (buffered oxide etchant).
[0077] Step S103: Combining Figure 5 and Figure 10 Release stacked region 7 to remove sacrificial layer 71.
[0078] In this embodiment, the sacrificial layer 71 is made of silicon-germanium. Specifically, the sacrificial layer 71 is removed by selectively etching it using a remote plasma source with a mixed solution of NF3, NH3, O2, and He in a ratio of 1:2:5:20, or a mixed solution of CF4, O2, and He in a ratio of 1:5:1. This embodiment does not impose specific limitations on this method.
[0079] Step S104: Combining Figure 6 and Figure 11 Selectively etch conductive nanosheets 41 to form receiving grooves 411 on the surface of conductive nanosheets 41 parallel to the substrate 1.
[0080] The conductive nanosheets 41 can be selectively etched away using halogen gases such as HCl, ClF3, BrF3, and IF5 via a purely chemithermic reaction. Preferably, ClF3 is used to etch the conductive nanosheets 41 at 30°C. The conductive nanosheets 41 are made of silicon, and the thickness of the removed conductive nanosheets 41 is >1 nm. The thickness of the conductive nanosheets 41 at the etched site ranges from 1 nm to 3 nm, preferably 2 nm.
[0081] Step S105: Combining Figure 7 and Figure 12 An epitaxial layer 42 is extended inside and outside the receiving groove 411.
[0082] The carrier mobility of the epitaxial layer 42 is higher than that of the conductive nanosheet 41, and the epitaxial layer 42 and the corresponding conductive nanosheet 41 form a composite nanosheet 43. Specifically, a single-crystal channel material is epitaxially grown on the thinned conductive nanosheet 41 using depressurized selective epitaxy. For PMOS, materials with high hole mobility such as Ge or SiGe are preferred, and for NMOS, materials with high electron mobility such as GaAs, GaN, or InP are preferred, but not limited to these.
[0083] Step S106: Combining Figure 8 and Figure 13 This forms a surrounding gate 5.
[0084] Specifically, a high-k dielectric layer 61 is deposited on the inner wall of the sidewall 64, the exposed surface of the composite nanosheet 43, and the surface of the first dielectric layer 621; the remaining space between the opposing sidewalls 64 is filled with gate material to form a surrounding gate 5, so that the surrounding gate 5 surrounds the periphery of the plurality of composite nanosheets 43.
[0085] In one alternative embodiment, combined with Figure 1 and Figure 9 After the step of forming the all-around gate 5, the fabrication method further includes: depositing a dielectric material to form a second dielectric layer 622, the second dielectric layer 622 covering the first dielectric layer 621 and the all-around gate 5; etching the first dielectric layer 621 and the second dielectric layer 622 to form a contact hole 623 and expose the source 2, the all-around gate 5 and the drain 3; filling the contact hole 623 with a conductive material to lead out the contact electrode 63.
[0086] It should be noted that after depositing the high-k dielectric layer 61 and filling it with gate material, a planarization process is required to remove the high-k dielectric layer 61 and gate material on the first dielectric layer 621, thereby forming a surround gate 5. Meanwhile, the first dielectric layer 621 and the second dielectric layer 622 are made of the same material. In this embodiment, the first dielectric layer 621 and the second dielectric layer 622 are both made of the aforementioned protective dielectric layer 62, which is made of silicon dioxide. Furthermore, the semiconductor device is a GAA device. Apart from the step of forming the composite nanosheet 43, other steps in preparing the GAA device can also be obtained through existing preparation methods, which will not be described in detail in this embodiment.
[0087] This fabrication method enhances channel carrier mobility by epitaxially growing materials on conductive nanosheets 41, building upon existing GAA device fabrication processes. Specifically, it uses the released, suspended conductive nanosheets 41 as selective epitaxial templates to grow materials with high carrier mobility required for both NMOS and PMOS. Ultimately, this method improves device driving capability without significantly altering the existing GAA fabrication process framework and workflow, and is simple to operate.
[0088] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor device, comprising: Substrate; The source and drain electrodes are disposed opposite to each other on the substrate; A nano-stacked structure disposed on the substrate; The source and the drain are located on opposite sides of the nano-stacked structure, respectively. The nano-stacked structure includes multiple conductive nanosheets, which are parallel to the surface of the substrate and stacked at intervals along a direction perpendicular to the substrate. The source and drain electrodes are respectively embedded at both ends of the conductive nanosheets. and all-around gate; The conductive nanosheet is characterized by having a receiving groove formed parallel to the surface of the substrate; The receiving groove is filled with an epitaxial layer, the carrier mobility of which is higher than that of the conductive nanosheet, and the epitaxial layer and the corresponding conductive nanosheet form a composite nanosheet. The surrounding gate surrounds the periphery of the plurality of composite nanosheets; The semiconductor device also includes: sidewalls disposed on both sides of the all-around gate facing the source and drain respectively, so as to electrically isolate the all-around gate from the source and drain; the two ends of the conductive nanosheet pass through the corresponding sidewalls and are embedded in the source and drain respectively; and the sidewall of the receiving trench is flush with the inner wall of the sidewall.
2. The semiconductor device according to claim 1, characterized in that, The conductive nanosheets are made of silicon; The depth of the receiving groove is not less than 1 nm; The thickness of the conductive nanosheet at the location of the receiving groove ranges from 1 nm to 3 nm.
3. The semiconductor device according to claim 1, characterized in that, The material of the epitaxial layer includes at least one of germanium and silicon germanium.
4. The semiconductor device according to claim 1 or 3, characterized in that, The concentration of germanium in the epitaxial layer is not less than 5%.
5. The semiconductor device according to claim 1, characterized in that, The material of the epitaxial layer includes at least one of gallium arsenide, gallium nitride, and indium phosphide.
6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a protective dielectric layer and three sets of contact electrodes; The protective dielectric layer covers the source, the drain, and the gate. The contact electrode penetrates the protective dielectric layer, and the three sets of contact electrodes are respectively in electrical contact with the source, the drain, and the all-around gate.
7. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A source, a drain, and a stacked region are formed on the substrate. The source and the drain are disposed on opposite sides of the stacked region. The stacked region includes a nano-stacked structure and multiple sacrificial layers. The nano-stacked structure includes multiple conductive nanosheets, which are parallel to the surface of the substrate. The conductive nanosheets and the sacrificial layers are alternately stacked along a direction perpendicular to the substrate. The layer closest to the substrate in the stacked region is the sacrificial layer. The source and drain are respectively embedded at both ends of the conductive nanosheets. The step of forming the source, drain, and stacked region on the substrate is further... The steps include: forming sidewalls, a first dielectric layer, and a dummy gate on the substrate; the first dielectric layer is disposed on the side of the substrate facing the source electrode, covering the source electrode and the drain electrode; the dummy gate is disposed on the side of the stacked region facing away from the substrate; the sidewalls are disposed on opposite sides of the dummy gate and the stacked region; the ends of the dummy gate and the sidewalls facing away from the substrate both expose the first dielectric layer; the two ends of the conductive nanosheet pass through the corresponding sidewalls and are embedded in the source electrode and the drain electrode, respectively; the sidewalls are used to isolate the dummy gate and the sacrificial layer from the source electrode and the drain electrode. Release the stacked region to remove the sacrificial layer; The conductive nanosheets are selectively etched to form receiving grooves on the surface of the conductive nanosheets parallel to the substrate; An epitaxial layer is extended inside and outside the receiving groove. The carrier mobility of the epitaxial layer is higher than that of the conductive nanosheet. The epitaxial layer and the corresponding conductive nanosheet form a composite nanosheet. A surrounding gate is formed, the surrounding gate surrounding the periphery of the plurality of composite nanosheets.
8. The preparation method according to claim 7, characterized in that, Prior to the step of selectively etching the conductive nanosheets, the fabrication method further includes: Remove the spurious gate; The step of forming the all-around gate includes: A high-k dielectric layer is deposited on the inner wall of the sidewall, the exposed surface of the composite nanosheet, and the surface of the first dielectric layer; The remaining space between the opposing side walls is filled with gate material to form the all-around gate.
9. The preparation method according to claim 7, characterized in that, After the step of forming the all-around gate, the fabrication method further includes: A dielectric material is deposited to form a second dielectric layer, the second dielectric layer covering the first dielectric layer and the all-around gate; The first dielectric layer and the second dielectric layer are etched to form contact holes and expose the source, the all-around gate and the drain. The contact hole is filled with conductive material to lead out the contact electrode.